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Full support for Ginger Console
[linux-ginger.git] / drivers / usb / musb / am3517.c
blob8b8648d6e1be69ca40c0b316687b493ffc9104c3
1 /*
2 * Texas Instruments AM3517 "glue layer"
3 *
4 * Copyright (c) 2008, MontaVista Software, Inc. <source@mvista.com>
5 *
6 * Based on the DaVinci "glue layer" code.
7 * Copyright (C) 2005-2006 by Texas Instruments
8 *
9 * This file is part of the Inventra Controller Driver for Linux.
10 *
11 * The Inventra Controller Driver for Linux is free software; you
12 * can redistribute it and/or modify it under the terms of the GNU
13 * General Public License version 2 as published by the Free Software
14 * Foundation.
15 *
16 * The Inventra Controller Driver for Linux is distributed in
17 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
18 * without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 * License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with The Inventra Controller Driver for Linux ; if not,
24 * write to the Free Software Foundation, Inc., 59 Temple Place,
25 * Suite 330, Boston, MA 02111-1307 USA
26 *
27 */
28
29 #include <linux/init.h>
30 #include <linux/clk.h>
31 #include <linux/io.h>
32
33 #include <plat/am3517.h>
34 #include <plat/control.h>
35 #include "cppi41.h"
36
37 #include "musb_core.h"
38 #include "cppi41_dma.h"
39
40 struct musb *g_musb;
41 /*
42 * AM3517 specific definitions
43 */
44
45 /* CPPI 4.1 queue manager registers */
46 #define QMGR_PEND0_REG 0x4090
47 #define QMGR_PEND1_REG 0x4094
48 #define QMGR_PEND2_REG 0x4098
49
50 /* USB 2.0 PHY Control */
51 #define CONF2_PHY_GPIOMODE (1 << 23)
52 #define CONF2_OTGMODE (3 << 14)
53 #define CONF2_SESENDEN (1 << 13) /* Vsess_end comparator */
54 #define CONF2_VBDTCTEN (1 << 12) /* Vbus comparator */
55 #define CONF2_REFFREQ_24MHZ (2 << 8)
56 #define CONF2_REFFREQ_26MHZ (7 << 8)
57 #define CONF2_REFFREQ_13MHZ (6 << 8)
58 #define CONF2_REFFREQ (0xf << 8)
59 #define CONF2_PHYCLKGD (1 << 7)
60 #define CONF2_VBUSSENSE (1 << 6)
61 #define CONF2_PHY_PLLON (1 << 5) /* override PLL suspend */
62 #define CONF2_RESET (1 << 4)
63 #define CONF2_PHYPWRDN (1 << 3)
64 #define CONF2_OTGPWRDN (1 << 2)
65 #define CONF2_DATPOL (1 << 1)
66
67
68 #define AM3517_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */
69 #define AM3517_RX_EP_MASK 0xfffe /* 15 Rx EPs */
70
71 #define AM3517_TX_INTR_MASK (AM3517_TX_EP_MASK << USB_INTR_TX_SHIFT)
72 #define AM3517_RX_INTR_MASK (AM3517_RX_EP_MASK << USB_INTR_RX_SHIFT)
73
74 #define A_WAIT_BCON_TIMEOUT 1100 /* in ms */
75
76 /* AM3517 specific read/write functions */
77 u16 musb_readw(const void __iomem *addr, unsigned offset)
78 {
79 u32 tmp;
80 u16 val;
81
82 if (addr == g_musb->mregs) {
83
84 switch (offset) {
85 case MUSB_INTRTXE:
86 if (g_musb->read_mask & AM3517_READ_ISSUE_INTRTXE)
87 return g_musb->intrtxe;
88 case MUSB_INTRRXE:
89 if (g_musb->read_mask & AM3517_READ_ISSUE_INTRRXE)
90 return g_musb->intrrxe;
91 default:
92 break;
93 }
94 }
95
96 tmp = __raw_readl(addr + (offset & ~3));
97
98 switch (offset & 0x3) {
99 case 0:
100 val = (tmp & 0xffff);
101 break;
102 case 1:
103 val = (tmp >> 8) & 0xffff;
104 break;
105 case 2:
106 case 3:
107 default:
108 val = (tmp >> 16) & 0xffff;
109 break;
110 }
111 return val;
112 }
113 void musb_writew(void __iomem *addr, unsigned offset, u16 data)
114 {
115 if (addr == g_musb->mregs) {
116
117 switch (offset) {
118 case MUSB_INTRTXE:
119 g_musb->read_mask |= AM3517_READ_ISSUE_INTRTXE;
120 g_musb->intrtxe = data;
121 break;
122 case MUSB_INTRRXE:
123 g_musb->read_mask |= AM3517_READ_ISSUE_INTRRXE;
124 g_musb->intrrxe = data;
125 default:
126 break;
127 }
128 }
129
130 __raw_writew(data, addr + offset);
131 }
132 u8 musb_readb(const void __iomem *addr, unsigned offset)
133 {
134 u32 tmp;
135 u8 val;
136
137 if (addr == g_musb->mregs) {
138
139 switch (offset) {
140 case MUSB_FADDR:
141 if (g_musb->read_mask & AM3517_READ_ISSUE_FADDR)
142 return g_musb->faddr;
143 case MUSB_POWER:
144 if (g_musb->read_mask & AM3517_READ_ISSUE_POWER) {
145 return g_musb->power;
146 } else {
147 tmp = __raw_readl(addr);
148 val = (tmp >> 8);
149 if (tmp & 0xffff0000) {
150 DBG(2, "Missing Tx interrupt\
151 event = 0x%x\n", (u16)\
152 ((tmp & 0xffff0000) >> 16));
153 }
154 g_musb->power = val;
155 g_musb->read_mask |= AM3517_READ_ISSUE_POWER;
156 return val;
157 }
158 case MUSB_INTRUSBE:
159 if (g_musb->read_mask & AM3517_READ_ISSUE_INTRUSBE)
160 return g_musb->intrusbe;
161 default:
162 break;
163 }
164 }
165
166 tmp = __raw_readl(addr + (offset & ~3));
167
168 switch (offset & 0x3) {
169 case 0:
170 val = tmp & 0xff;
171 break;
172 case 1:
173 val = (tmp >> 8);
174 break;
175 case 2:
176 val = (tmp >> 16);
177 break;
178 case 3:
179 default:
180 val = (tmp >> 24);
181 break;
182 }
183 return val;
184 }
185 void musb_writeb(void __iomem *addr, unsigned offset, u8 data)
186 {
187 if (addr == g_musb->mregs) {
188
189 switch (offset) {
190 case MUSB_FADDR:
191 g_musb->read_mask |= AM3517_READ_ISSUE_FADDR;
192 g_musb->faddr = data;
193 break;
194 case MUSB_POWER:
195 g_musb->read_mask |= AM3517_READ_ISSUE_POWER;
196 g_musb->power = data;
197 break;
198 case MUSB_INTRUSBE:
199 g_musb->read_mask |= AM3517_READ_ISSUE_INTRUSBE;
200 g_musb->intrusbe = data;
201 default:
202 break;
203 }
204 }
205
206 __raw_writeb(data, addr + offset);
207 }
208 #ifdef CONFIG_USB_TI_CPPI41_DMA
209
210 /*
211 * CPPI 4.1 resources used for USB OTG controller module:
212 *
213 * USB DMA DMA QMgr Tx Src
214 * Tx Rx QNum Port
215 * ---------------------------------
216 * EP0 0 0 0 16,17 1
217 * ---------------------------------
218 * EP1 1 1 0 18,19 2
219 * ---------------------------------
220 * EP2 2 2 0 20,21 3
221 * ---------------------------------
222 * EP3 3 3 0 22,23 4
223 * ---------------------------------
224 */
225
226 static const u16 tx_comp_q[] = { 63, 64 };
227 static const u16 rx_comp_q[] = { 65, 66 };
228
229 const struct usb_cppi41_info usb_cppi41_info = {
230 .dma_block = 0,
231 .ep_dma_ch = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 },
232 .q_mgr = 0,
233 .num_tx_comp_q = 2,
234 .num_rx_comp_q = 2,
235 .tx_comp_q = tx_comp_q,
236 .rx_comp_q = rx_comp_q
237 };
238
239 /* Fair scheduling */
240 u32 dma_sched_table[] = {
241 0x81018000, 0x83038202, 0x85058404, 0x87078606,
242 0x89098808, 0x8b0b8a0a, 0x8d0d8c0c, 0x00008e0e
243 };
244
245 /* DMA block configuration */
246 static const struct cppi41_tx_ch tx_ch_info[] = {
247 [0] = {
248 .port_num = 1,
249 .num_tx_queue = 2,
250 .tx_queue = { {0, 32} , {0, 33} }
251 },
252 [1] = {
253 .port_num = 2,
254 .num_tx_queue = 2,
255 .tx_queue = { {0, 34} , {0, 35} }
256 },
257 [2] = {
258 .port_num = 3,
259 .num_tx_queue = 2,
260 .tx_queue = { {0, 36} , {0, 37} }
261 },
262 [3] = {
263 .port_num = 4,
264 .num_tx_queue = 2,
265 .tx_queue = { {0, 38} , {0, 39} }
266 },
267 [4] = {
268 .port_num = 5,
269 .num_tx_queue = 2,
270 .tx_queue = { {0, 40} , {0, 41} }
271 },
272 [5] = {
273 .port_num = 6,
274 .num_tx_queue = 2,
275 .tx_queue = { {0, 42} , {0, 43} }
276 },
277 [6] = {
278 .port_num = 7,
279 .num_tx_queue = 2,
280 .tx_queue = { {0, 44} , {0, 45} }
281 },
282 [7] = {
283 .port_num = 8,
284 .num_tx_queue = 2,
285 .tx_queue = { {0, 46} , {0, 47} }
286 },
287 [8] = {
288 .port_num = 9,
289 .num_tx_queue = 2,
290 .tx_queue = { {0, 48} , {0, 49} }
291 },
292 [9] = {
293 .port_num = 10,
294 .num_tx_queue = 2,
295 .tx_queue = { {0, 50} , {0, 51} }
296 },
297 [10] = {
298 .port_num = 11,
299 .num_tx_queue = 2,
300 .tx_queue = { {0, 52} , {0, 53} }
301 },
302 [11] = {
303 .port_num = 12,
304 .num_tx_queue = 2,
305 .tx_queue = { {0, 54} , {0, 55} }
306 },
307 [12] = {
308 .port_num = 13,
309 .num_tx_queue = 2,
310 .tx_queue = { {0, 56} , {0, 57} }
311 },
312 [13] = {
313 .port_num = 14,
314 .num_tx_queue = 2,
315 .tx_queue = { {0, 58} , {0, 59} }
316 },
317 [14] = {
318 .port_num = 15,
319 .num_tx_queue = 2,
320 .tx_queue = { {0, 60} , {0, 61} }
321 }
322 };
323
324 struct cppi41_dma_block cppi41_dma_block[CPPI41_NUM_DMA_BLOCK] = {
325 [0] = {
326 .num_tx_ch = 15,
327 .num_rx_ch = 15,
328 .tx_ch_info = tx_ch_info
329 }
330 };
331 EXPORT_SYMBOL(cppi41_dma_block);
332
333 /* Queues 0 to 66 are pre-assigned, others are spare */
334 static const u32 assigned_queues[] = { 0xffffffff, 0xffffffff, 0x7 };
335
336 /* Queue manager information */
337 struct cppi41_queue_mgr cppi41_queue_mgr[CPPI41_NUM_QUEUE_MGR] = {
338 [0] = {
339 .num_queue = 96,
340 .queue_types = CPPI41_FREE_DESC_BUF_QUEUE |
341 CPPI41_UNASSIGNED_QUEUE,
342 .base_fdbq_num = 0,
343 .assigned = assigned_queues
344 }
345 };
346 EXPORT_SYMBOL(cppi41_queue_mgr);
347
348 int __init cppi41_init(struct musb *musb)
349 {
350 u16 numch, blknum = usb_cppi41_info.dma_block, order;
351
352 /* init mappings */
353 cppi41_queue_mgr[0].q_mgr_rgn_base = musb->ctrl_base + 0x4000;
354 cppi41_queue_mgr[0].desc_mem_rgn_base = musb->ctrl_base + 0x5000;
355 cppi41_queue_mgr[0].q_mgmt_rgn_base = musb->ctrl_base + 0x6000;
356 cppi41_queue_mgr[0].q_stat_rgn_base = musb->ctrl_base + 0x6800;
357
358 cppi41_dma_block[0].global_ctrl_base = musb->ctrl_base + 0x1000;
359 cppi41_dma_block[0].ch_ctrl_stat_base = musb->ctrl_base + 0x1800;
360 cppi41_dma_block[0].sched_ctrl_base = musb->ctrl_base + 0x2000;
361 cppi41_dma_block[0].sched_table_base = musb->ctrl_base + 0x2800;
362
363 /* Initialize for Linking RAM region 0 alone */
364 cppi41_queue_mgr_init(usb_cppi41_info.q_mgr, 0, 0x3fff);
365
366 numch = USB_CPPI41_NUM_CH * 2;
367 order = get_count_order(numch);
368
369 /* TODO: check two teardown desc per channel (5 or 7 ?)*/
370 if (order < 5)
371 order = 5;
372
373 cppi41_dma_block_init(blknum, usb_cppi41_info.q_mgr, order,
374 dma_sched_table, numch);
375 return 0;
376 }
377
378 #endif /* CONFIG_USB_TI_CPPI41_DMA */
379
380 #ifdef CONFIG_USB_TI_CPPI41_DMA
381 int cppi41_disable_sched_rx(void)
382 {
383 u16 numch = 7, blknum = usb_cppi41_info.dma_block;
384
385 dma_sched_table[0] = 0x02810100;
386 dma_sched_table[1] = 0x830382;
387
388 cppi41_dma_sched_tbl_init(blknum, usb_cppi41_info.q_mgr,
389 dma_sched_table, numch);
390 return 0;
391 }
392
393 int cppi41_enable_sched_rx(void)
394 {
395 u16 numch = 8, blknum = usb_cppi41_info.dma_block;
396
397 dma_sched_table[0] = 0x81018000;
398 dma_sched_table[1] = 0x83038202;
399
400 cppi41_dma_sched_tbl_init(blknum, usb_cppi41_info.q_mgr,
401 dma_sched_table, numch);
402 return 0;
403 }
404 #endif
405
406 /*
407 * REVISIT (PM): we should be able to keep the PHY in low power mode most
408 * of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0
409 * and, when in host mode, autosuspending idle root ports... PHYPLLON
410 * (overriding SUSPENDM?) then likely needs to stay off.
411 */
412
413 static inline void phy_on(void)
414 {
415 u32 devconf2;
416
417 /*
418 * Start the on-chip PHY and its PLL.
419 */
420 devconf2 = omap_ctrl_readl(OMAP3517_CONTROL_DEVCONF2);
421
422 devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN |
423 CONF2_OTGMODE | CONF2_REFFREQ | CONF2_PHY_GPIOMODE);
424 devconf2 |= CONF2_SESENDEN | CONF2_VBDTCTEN | CONF2_PHY_PLLON |
425 CONF2_REFFREQ_13MHZ | CONF2_DATPOL;
426
427 omap_ctrl_writel(devconf2, OMAP3517_CONTROL_DEVCONF2);
428
429 DBG(1, "Waiting for PHY clock good...\n");
430 while (!(omap_ctrl_readl(OMAP3517_CONTROL_DEVCONF2)
431 & CONF2_PHYCLKGD))
432 cpu_relax();
433 }
434
435 static inline void phy_off(void)
436 {
437 u32 devconf2;
438
439 /*
440 * Power down the on-chip PHY.
441 */
442 devconf2 = omap_ctrl_readl(OMAP3517_CONTROL_DEVCONF2);
443
444 devconf2 &= ~CONF2_PHY_PLLON;
445 devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN;
446 omap_ctrl_writel(devconf2, OMAP3517_CONTROL_DEVCONF2);
447 }
448
449 /*
450 * Because we don't set CTRL.UINT, it's "important" to:
451 * - not read/write INTRUSB/INTRUSBE (except during
452 * initial setup, as a workaround);
453 * - use INTSET/INTCLR instead.
454 */
455
456 /**
457 * musb_platform_enable - enable interrupts
458 */
459 void musb_platform_enable(struct musb *musb)
460 {
461 void __iomem *reg_base = musb->ctrl_base;
462 u32 epmask, coremask;
463
464 /* Workaround: setup IRQs through both register sets. */
465 epmask = ((musb->epmask & AM3517_TX_EP_MASK) << USB_INTR_TX_SHIFT) |
466 ((musb->epmask & AM3517_RX_EP_MASK) << USB_INTR_RX_SHIFT);
467 coremask = (0x01ff << USB_INTR_USB_SHIFT);
468
469 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
470 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, coremask);
471
472 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
473 if (is_otg_enabled(musb))
474 musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
475 USB_INTR_DRVVBUS << USB_INTR_USB_SHIFT);
476 }
477
478 /**
479 * musb_platform_disable - disable HDRC and flush interrupts
480 */
481 void musb_platform_disable(struct musb *musb)
482 {
483 void __iomem *reg_base = musb->ctrl_base;
484
485 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, USB_INTR_USB_MASK);
486 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
487 AM3517_TX_INTR_MASK | AM3517_RX_INTR_MASK);
488 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
489 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
490 }
491
492 /* REVISIT: it's not clear whether AM3517 can support full OTG. */
493
494 static int vbus_state = -1;
495
496 #ifdef CONFIG_USB_MUSB_HDRC_HCD
497 #define portstate(stmt) stmt
498 #else
499 #define portstate(stmt)
500 #endif
501
502 static void am3517_source_power(struct musb *musb, int is_on, int immediate)
503 {
504 if (is_on)
505 is_on = 1;
506
507 if (vbus_state == is_on)
508 return;
509 vbus_state = is_on; /* 0/1 vs "-1 == unknown/init" */
510 }
511
512 static void am3517_set_vbus(struct musb *musb, int is_on)
513 {
514 WARN_ON(is_on && is_peripheral_active(musb));
515 am3517_source_power(musb, is_on, 0);
516 }
517
518 #define POLL_SECONDS 2
519
520 static struct timer_list otg_workaround;
521
522 static void otg_timer(unsigned long _musb)
523 {
524 struct musb *musb = (void *)_musb;
525 void __iomem *mregs = musb->mregs;
526 u8 devctl;
527 unsigned long flags;
528
529 /* We poll because DaVinci's won't expose several OTG-critical
530 * status change events (from the transceiver) otherwise.
531 */
532 devctl = musb_readb(mregs, MUSB_DEVCTL);
533 DBG(7, "Poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
534
535 spin_lock_irqsave(&musb->lock, flags);
536 switch (musb->xceiv->state) {
537 case OTG_STATE_A_WAIT_BCON:
538 devctl &= ~MUSB_DEVCTL_SESSION;
539 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
540
541 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
542 if (devctl & MUSB_DEVCTL_BDEVICE) {
543 musb->xceiv->state = OTG_STATE_B_IDLE;
544 MUSB_DEV_MODE(musb);
545 } else {
546 musb->xceiv->state = OTG_STATE_A_IDLE;
547 MUSB_HST_MODE(musb);
548 }
549 break;
550 case OTG_STATE_A_WAIT_VFALL:
551 /*
552 * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
553 * RTL seems to mis-handle session "start" otherwise (or in
554 * our case "recover"), in routine "VBUS was valid by the time
555 * VBUSERR got reported during enumeration" cases.
556 */
557 if (devctl & MUSB_DEVCTL_VBUS) {
558 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
559 break;
560 }
561 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
562 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
563 MUSB_INTR_VBUSERROR << USB_INTR_USB_SHIFT);
564 break;
565 case OTG_STATE_B_IDLE:
566 if (!is_peripheral_enabled(musb))
567 break;
568
569 /*
570 * There's no ID-changed IRQ, so we have no good way to tell
571 * when to switch to the A-Default state machine (by setting
572 * the DEVCTL.SESSION flag).
573 *
574 * Workaround: whenever we're in B_IDLE, try setting the
575 * session flag every few seconds. If it works, ID was
576 * grounded and we're now in the A-Default state machine.
577 *
578 * NOTE: setting the session flag is _supposed_ to trigger
579 * SRP but clearly it doesn't.
580 */
581 devctl = musb_readb(mregs, MUSB_DEVCTL);
582 if (devctl & MUSB_DEVCTL_BDEVICE)
583 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
584 else
585 musb->xceiv->state = OTG_STATE_A_IDLE;
586 break;
587 default:
588 break;
589 }
590 spin_unlock_irqrestore(&musb->lock, flags);
591 }
592
593 void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
594 {
595 static unsigned long last_timer;
596
597 if (!is_otg_enabled(musb))
598 return;
599
600 if (timeout == 0)
601 timeout = jiffies + msecs_to_jiffies(3);
602
603 /* Never idle if active, or when VBUS timeout is not set as host */
604 if (musb->is_active || (musb->a_wait_bcon == 0 &&
605 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
606 DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
607 del_timer(&otg_workaround);
608 last_timer = jiffies;
609 return;
610 }
611
612 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
613 DBG(4, "Longer idle timer already pending, ignoring...\n");
614 return;
615 }
616 last_timer = timeout;
617
618 DBG(4, "%s inactive, starting idle timer for %u ms\n",
619 otg_state_string(musb), jiffies_to_msecs(timeout - jiffies));
620 mod_timer(&otg_workaround, timeout);
621 }
622
623 static irqreturn_t am3517_interrupt(int irq, void *hci)
624 {
625 struct musb *musb = hci;
626 void __iomem *reg_base = musb->ctrl_base;
627 unsigned long flags;
628 irqreturn_t ret = IRQ_NONE;
629 u32 pend1 = 0, pend2 = 0, tx, rx;
630 u32 epintr, usbintr, lvl_intr;
631
632 spin_lock_irqsave(&musb->lock, flags);
633
634 /*
635 * NOTE: AM3517 shadows the Mentor IRQs. Don't manage them through
636 * the Mentor registers (except for setup), use the TI ones and EOI.
637 */
638
639 /*
640 * CPPI 4.1 interrupts share the same IRQ and the EOI register but
641 * don't get reflected in the interrupt source/mask registers.
642 */
643 if (is_cppi41_enabled()) {
644 /*
645 * Check for the interrupts from Tx/Rx completion queues; they
646 * are level-triggered and will stay asserted until the queues
647 * are emptied. We're using the queue pending register 0 as a
648 * substitute for the interrupt status register and reading it
649 * directly for speed.
650 */
651 pend1 = musb_readl(reg_base, QMGR_PEND1_REG);
652 pend2 = musb_readl(reg_base, QMGR_PEND2_REG);
653
654 /* AM3517 uses 63,64,65 and 66 queues as completion queue */
655 if ((pend1 & (1 << 31)) || (pend2 & (7 << 0))) {
656 tx = (pend1 >> 31) | ((pend2 & 1) ? (1 << 1) : 0);
657 rx = (pend2 >> 1) & 0x3;
658
659 DBG(4, "CPPI 4.1 IRQ: Tx %x, Rx %x\n", tx, rx);
660 cppi41_completion(musb, rx, tx);
661 ret = IRQ_HANDLED;
662 }
663
664 /* TODO: check if this is required */
665 /* handle the undocumented starvation interrupt bit:28 */
666 /* if(pend0 & 0x10000000)
667 ret = IRQ_HANDLED;
668 */
669 }
670
671 /* Acknowledge and handle non-CPPI interrupts */
672 /* Get endpoint interrupts */
673 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
674
675 if (epintr) {
676 musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
677
678 musb->int_rx =
679 (epintr & AM3517_RX_INTR_MASK) >> USB_INTR_RX_SHIFT;
680 musb->int_tx =
681 (epintr & AM3517_TX_INTR_MASK) >> USB_INTR_TX_SHIFT;
682 }
683
684 /* Get usb core interrupts */
685 usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
686 if (!usbintr && !epintr)
687 goto eoi;
688
689 if (usbintr) {
690 musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
691
692 musb->int_usb =
693 (usbintr & USB_INTR_USB_MASK) >> USB_INTR_USB_SHIFT;
694 /* musb->int_regs = regs; */
695 }
696 /*
697 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
698 * AM3517's missing ID change IRQ. We need an ID change IRQ to
699 * switch appropriately between halves of the OTG state machine.
700 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
701 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
702 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
703 */
704 if (usbintr & (USB_INTR_DRVVBUS << USB_INTR_USB_SHIFT)) {
705 int drvvbus = musb_readl(reg_base, USB_STAT_REG);
706 void __iomem *mregs = musb->mregs;
707 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
708 int err;
709
710 err = is_host_enabled(musb) && (musb->int_usb &
711 MUSB_INTR_VBUSERROR);
712 if (err) {
713 /*
714 * The Mentor core doesn't debounce VBUS as needed
715 * to cope with device connect current spikes. This
716 * means it's not uncommon for bus-powered devices
717 * to get VBUS errors during enumeration.
718 *
719 * This is a workaround, but newer RTL from Mentor
720 * seems to allow a better one: "re"-starting sessions
721 * without waiting for VBUS to stop registering in
722 * devctl.
723 */
724 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
725 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
726 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
727 WARNING("VBUS error workaround (delay coming)\n");
728 } else if (is_host_enabled(musb) && drvvbus) {
729 musb->is_active = 1;
730 MUSB_HST_MODE(musb);
731 musb->xceiv->default_a = 1;
732 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
733 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
734 del_timer(&otg_workaround);
735 } else {
736 musb->is_active = 0;
737 MUSB_DEV_MODE(musb);
738 musb->xceiv->default_a = 0;
739 musb->xceiv->state = OTG_STATE_B_IDLE;
740 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
741 }
742
743 /* NOTE: this must complete power-on within 100 ms. */
744 am3517_source_power(musb, drvvbus, 0);
745 DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
746 drvvbus ? "on" : "off",
747 otg_state_string(musb),
748 err ? " ERROR" : "",
749 devctl);
750 ret = IRQ_HANDLED;
751 }
752
753 if (musb->int_tx || musb->int_rx || musb->int_usb) {
754 irqreturn_t mret;
755
756 mret = musb_interrupt(musb);
757 if (mret == IRQ_HANDLED)
758 ret = IRQ_HANDLED;
759 }
760
761 /* musb->int_regs = NULL; */
762
763 eoi:
764 /* EOI needs to be written for the IRQ to be re-asserted. */
765 if (ret == IRQ_HANDLED || epintr || usbintr) {
766 /* clear level interrupt */
767 lvl_intr = omap_ctrl_readl(OMAP3517_CONTROL_LVL_INTR_CLEAR);
768 lvl_intr |= AM3517_USBOTG_INT_CLR;
769 omap_ctrl_writel(lvl_intr, OMAP3517_CONTROL_LVL_INTR_CLEAR);
770 /* write EOI */
771 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
772 }
773
774 /* Poll for ID change */
775 if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
776 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
777
778 spin_unlock_irqrestore(&musb->lock, flags);
779
780 if (ret != IRQ_HANDLED) {
781 if (epintr || usbintr)
782 /*
783 * We sometimes get unhandled IRQs in the peripheral
784 * mode from EP0 and SOF...
785 */
786 DBG(2, "Unhandled USB IRQ %08x-%08x\n",
787 epintr, usbintr);
788 else if (printk_ratelimit())
789 /*
790 * We've seen series of spurious interrupts in the
791 * peripheral mode after USB reset and then after some
792 * time a real interrupt storm starting...
793 */
794 DBG(2, "Spurious IRQ, CPPI 4.1 status %08x, %08x\n",
795 pend1, pend2);
796 }
797 return ret;
798 }
799
800 int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
801 {
802 /* TODO: implement this using CONF0 */
803 WARNING("FIXME: %s not implemented\n", __func__);
804 return -EIO;
805 }
806
807 int __init musb_platform_init(struct musb *musb)
808 {
809 void __iomem *reg_base = musb->ctrl_base;
810 struct clk *otg_fck;
811 u32 rev, lvl_intr, sw_reset;
812
813 g_musb = musb;
814
815 usb_nop_xceiv_register();
816
817 musb->xceiv = otg_get_transceiver();
818 if (!musb->xceiv)
819 return -ENODEV;
820
821 /* mentor is at offset of 0x400 in am3517 */
822 musb->mregs += USB_MENTOR_CORE_OFFSET;
823
824 /* not required as clock is set in usb-musb.c file in arch */
825 /* musb->clock = clk_get(NULL, "usbotg_ck"); */
826 if (IS_ERR(musb->clock))
827 return PTR_ERR(musb->clock);
828
829 if (musb->set_clock)
830 musb->set_clock(musb->clock, 1);
831 else
832 clk_enable(musb->clock);
833
834 DBG(2, "usbotg_ck=%lud\n", clk_get_rate(musb->clock));
835 otg_fck = clk_get(NULL, "usbotg_phy_ck");
836 clk_enable(otg_fck);
837
838 DBG(2, "usbotg_phy_ck=%lud\n", clk_get_rate(otg_fck));
839 /* Returns zero if e.g. not clocked */
840 rev = musb_readl(reg_base, USB_REVISION_REG);
841 if (!rev)
842 return -ENODEV;
843
844 if (is_host_enabled(musb))
845 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
846
847 musb->board_set_vbus = am3517_set_vbus;
848 am3517_source_power(musb, 0, 1);
849
850 #if 0 /* follow recommended reset procedure */
851 /* Reset the controller */
852 musb_writel(reg_base, USB_CTRL_REG, USB_SOFT_RESET_MASK);
853
854 /* wait till reset bit clears */
855 while ((musb_readl(reg_base, USB_CTRL_REG) & 0x1))
856 cpu_relax();
857
858 /* clock disable */
859 clk_disable(musb->clock);
860
861 /* Start the on-chip PHY and its PLL. */
862 phy_on();
863
864 msleep(5);
865
866 /* clock enable */
867 clk_enable(musb->clock);
868
869 #else
870 /* global reset */
871 sw_reset = omap_ctrl_readl(OMAP3517_CONTROL_IP_SW_RESET);
872
873 sw_reset |= AM3517_USBOTG_SW_RST;
874 omap_ctrl_writel(sw_reset, OMAP3517_CONTROL_IP_SW_RESET);
875
876 sw_reset &= ~AM3517_USBOTG_SW_RST;
877 omap_ctrl_writel(sw_reset, OMAP3517_CONTROL_IP_SW_RESET);
878
879 /* Reset the controller */
880 musb_writel(reg_base, USB_CTRL_REG, USB_SOFT_RESET_MASK);
881
882 /* Start the on-chip PHY and its PLL. */
883 phy_on();
884
885 msleep(15);
886 #endif
887
888 #ifdef CONFIG_USB_TI_CPPI41_DMA
889 cppi41_init(musb);
890 #endif
891
892 /* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */
893 printk("AM3517 OTG revision %08x, PHY %03x, control %02x\n",
894 rev, omap_ctrl_readl(OMAP3517_CONTROL_DEVCONF2),
895 musb_readb(reg_base, USB_CTRL_REG));
896
897 musb->a_wait_bcon = A_WAIT_BCON_TIMEOUT;
898 musb->isr = am3517_interrupt;
899 /* update the HS EOF tiing */
900 /* musb_writeb(musb->mregs, 0x7C, 0x40); */
901
902 /* clear level interrupt */
903 lvl_intr = omap_ctrl_readl(OMAP3517_CONTROL_LVL_INTR_CLEAR);
904 lvl_intr |= AM3517_USBOTG_INT_CLR;
905 omap_ctrl_writel(lvl_intr, OMAP3517_CONTROL_LVL_INTR_CLEAR);
906
907 return 0;
908 }
909
910 int musb_platform_exit(struct musb *musb)
911 {
912 if (is_host_enabled(musb))
913 del_timer_sync(&otg_workaround);
914
915 am3517_source_power(musb, 0 /* off */, 1);
916
917 /* Delay to avoid problems with module reload... */
918 if (is_host_enabled(musb) && musb->xceiv->default_a) {
919 int maxdelay = 30;
920 u8 devctl, warn = 0;
921
922 /*
923 * If there's no peripheral connected, this can take a
924 * long time to fall...
925 */
926 do {
927 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
928 if (!(devctl & MUSB_DEVCTL_VBUS))
929 break;
930 if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
931 warn = devctl & MUSB_DEVCTL_VBUS;
932 DBG(1, "VBUS %d\n",
933 warn >> MUSB_DEVCTL_VBUS_SHIFT);
934 }
935 msleep(1000);
936 maxdelay--;
937 } while (maxdelay > 0);
938
939 /* In OTG mode, another host might be connected... */
940 if (devctl & MUSB_DEVCTL_VBUS)
941 DBG(1, "VBUS off timeout (devctl %02x)\n", devctl);
942 }
943
944 phy_off();
945
946 usb_nop_xceiv_unregister();
947
948 #ifdef CONFIG_USB_TI_CPPI41_DMA
949 cppi41_exit();
950 #endif
951 return 0;
952 }
953
954 #ifdef CONFIG_PM
955 void musb_platform_save_context(struct musb_context_registers
956 *musb_context)
957 {
958 /* Save CPPI41 DMA related registers */
959 phy_off();
960 }
961
962 void musb_platform_restore_context(struct musb_context_registers
963 *musb_context)
964 {
965 /* Restore CPPI41 DMA related registers */
966 phy_on();
967 }
968 #endif
Linux for Ginger Game Console