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Full support for Ginger Console
[linux-ginger.git] / drivers / usb / musb / cppi41.c
blob1ba7b49f1954f4716924afdb6afec27228df948c
1 /*
2 * CPPI 4.1 support
3 *
4 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
5 *
6 * Based on the PAL CPPI 4.1 implementation
7 * Copyright (C) 1998-2006 Texas Instruments Incorporated
8 *
9 * This file contains the main implementation for CPPI 4.1 common peripherals,
10 * including the DMA Controllers and the Queue Managers.
11 *
12 * This program is free software; you can distribute it and/or modify it
13 * under the terms of the GNU General Public License (Version 2) as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * for more details.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
24 *
25 */
26
27 #include <linux/io.h>
28 #include <linux/init.h>
29 #include <linux/module.h>
30 #include <linux/dma-mapping.h>
31
32 #include "cppi41.h"
33
34 #undef CPPI41_DEBUG
35
36 #ifdef CPPI41_DEBUG
37 #define DBG(format, args...) printk(format, ##args)
38 #else
39 #define DBG(format, args...)
40 #endif
41
42 static struct {
43 void *virt_addr;
44 dma_addr_t phys_addr;
45 } linking_ram[CPPI41_NUM_QUEUE_MGR];
46
47 static u32 *allocated_queues[CPPI41_NUM_QUEUE_MGR];
48
49 /* First 32 packet descriptors are reserved for unallocated memory regions. */
50 static u32 next_desc_index[CPPI41_NUM_QUEUE_MGR] = { 1 << 5 };
51 static u8 next_mem_rgn[CPPI41_NUM_QUEUE_MGR];
52
53 static struct {
54 size_t rgn_size;
55 void *virt_addr;
56 dma_addr_t phys_addr;
57 struct cppi41_queue_obj queue_obj;
58 u8 mem_rgn;
59 } dma_teardown[CPPI41_NUM_DMA_BLOCK];
60
61 /******************** CPPI 4.1 Functions (External Interface) *****************/
62
63 int cppi41_queue_mgr_init(u8 q_mgr, dma_addr_t rgn0_base, u16 rgn0_size)
64 {
65 void __iomem *q_mgr_regs;
66 void *ptr;
67
68 if (q_mgr >= cppi41_num_queue_mgr)
69 return -EINVAL;
70
71 q_mgr_regs = cppi41_queue_mgr[q_mgr].q_mgr_rgn_base;
72 ptr = dma_alloc_coherent(NULL, rgn0_size * 4,
73 &linking_ram[q_mgr].phys_addr,
74 GFP_KERNEL | GFP_DMA);
75 if (ptr == NULL) {
76 printk(KERN_ERR "ERROR: %s: Unable to allocate "
77 "linking RAM.\n", __func__);
78 return -ENOMEM;
79 }
80 linking_ram[q_mgr].virt_addr = ptr;
81
82 __raw_writel(linking_ram[q_mgr].phys_addr,
83 q_mgr_regs + QMGR_LINKING_RAM_RGN0_BASE_REG);
84 DBG("Linking RAM region 0 base @ %p, value: %x\n",
85 q_mgr_regs + QMGR_LINKING_RAM_RGN0_BASE_REG,
86 __raw_readl(q_mgr_regs + QMGR_LINKING_RAM_RGN0_BASE_REG));
87
88 __raw_writel(rgn0_size, q_mgr_regs + QMGR_LINKING_RAM_RGN0_SIZE_REG);
89 DBG("Linking RAM region 0 size @ %p, value: %x\n",
90 q_mgr_regs + QMGR_LINKING_RAM_RGN0_SIZE_REG,
91 __raw_readl(q_mgr_regs + QMGR_LINKING_RAM_RGN0_SIZE_REG));
92
93 ptr = kzalloc(BITS_TO_LONGS(cppi41_queue_mgr[q_mgr].num_queue),
94 GFP_KERNEL);
95 if (ptr == NULL) {
96 printk(KERN_ERR "ERROR: %s: Unable to allocate queue bitmap.\n",
97 __func__);
98 dma_free_coherent(NULL, rgn0_size * 4,
99 linking_ram[q_mgr].virt_addr,
100 linking_ram[q_mgr].phys_addr);
101 return -ENOMEM;
102 }
103 allocated_queues[q_mgr] = ptr;
104
105 return 0;
106 }
107 EXPORT_SYMBOL(cppi41_queue_mgr_init);
108
109 int cppi41_dma_sched_tbl_init(u8 dma_num, u8 q_mgr,
110 u32 *sched_tbl, u8 tbl_size)
111 {
112 struct cppi41_dma_block *dma_block;
113 int num_reg, k, i, val = 0;
114
115 dma_block = (struct cppi41_dma_block *)&cppi41_dma_block[dma_num];
116
117 num_reg = (tbl_size + 3) / 4;
118 for (k = i = 0; i < num_reg; i++) {
119 #if 0
120 for (val = j = 0; j < 4; j++, k++) {
121 val >>= 8;
122 if (k < tbl_size)
123 val |= sched_tbl[k] << 24;
124 }
125 #endif
126 val = sched_tbl[i];
127 __raw_writel(val, dma_block->sched_table_base +
128 DMA_SCHED_TABLE_WORD_REG(i));
129 DBG("DMA scheduler table @ %p, value written: %x\n",
130 dma_block->sched_table_base + DMA_SCHED_TABLE_WORD_REG(i),
131 val);
132 }
133 return 0;
134 }
135 EXPORT_SYMBOL(cppi41_dma_sched_tbl_init);
136
137 int cppi41_dma_block_init(u8 dma_num, u8 q_mgr, u8 num_order,
138 u32 *sched_tbl, u8 tbl_size)
139 {
140 const struct cppi41_dma_block *dma_block;
141 struct cppi41_teardown_desc *curr_td;
142 dma_addr_t td_addr;
143 unsigned num_desc, num_reg;
144 void *ptr;
145 int error, i;
146 u16 q_num;
147 u32 val;
148
149 if (dma_num >= cppi41_num_dma_block ||
150 q_mgr >= cppi41_num_queue_mgr ||
151 !tbl_size || sched_tbl == NULL)
152 return -EINVAL;
153
154 error = cppi41_queue_alloc(CPPI41_FREE_DESC_QUEUE |
155 CPPI41_UNASSIGNED_QUEUE, q_mgr, &q_num);
156 if (error) {
157 printk(KERN_ERR "ERROR: %s: Unable to allocate teardown "
158 "descriptor queue.\n", __func__);
159 return error;
160 }
161 DBG("Teardown descriptor queue %d in queue manager 0 "
162 "allocated\n", q_num);
163
164 /*
165 * Tell the hardware about the Teardown descriptor
166 * queue manager and queue number.
167 */
168 dma_block = &cppi41_dma_block[dma_num];
169 __raw_writel((q_mgr << DMA_TD_DESC_QMGR_SHIFT) |
170 (q_num << DMA_TD_DESC_QNUM_SHIFT),
171 dma_block->global_ctrl_base +
172 DMA_TEARDOWN_FREE_DESC_CTRL_REG);
173 DBG("Teardown free descriptor control @ %p, value: %x\n",
174 dma_block->global_ctrl_base + DMA_TEARDOWN_FREE_DESC_CTRL_REG,
175 __raw_readl(dma_block->global_ctrl_base +
176 DMA_TEARDOWN_FREE_DESC_CTRL_REG));
177
178 num_desc = 1 << num_order;
179 dma_teardown[dma_num].rgn_size = num_desc *
180 sizeof(struct cppi41_teardown_desc);
181
182 /* Pre-allocate teardown descriptors. */
183 ptr = dma_alloc_coherent(NULL, dma_teardown[dma_num].rgn_size,
184 &dma_teardown[dma_num].phys_addr,
185 GFP_KERNEL | GFP_DMA);
186 if (ptr == NULL) {
187 printk(KERN_ERR "ERROR: %s: Unable to allocate teardown "
188 "descriptors.\n", __func__);
189 error = -ENOMEM;
190 goto free_queue;
191 }
192 dma_teardown[dma_num].virt_addr = ptr;
193
194 error = cppi41_mem_rgn_alloc(q_mgr, dma_teardown[dma_num].phys_addr, 5,
195 num_order, &dma_teardown[dma_num].mem_rgn);
196 if (error) {
197 printk(KERN_ERR "ERROR: %s: Unable to allocate queue manager "
198 "memory region for teardown descriptors.\n", __func__);
199 goto free_mem;
200 }
201
202 error = cppi41_queue_init(&dma_teardown[dma_num].queue_obj, 0, q_num);
203 if (error) {
204 printk(KERN_ERR "ERROR: %s: Unable to initialize teardown "
205 "free descriptor queue.\n", __func__);
206 goto free_rgn;
207 }
208
209 /*
210 * Push all teardown descriptors to the free teardown queue
211 * for the CPPI 4.1 system.
212 */
213 curr_td = dma_teardown[dma_num].virt_addr;
214 td_addr = dma_teardown[dma_num].phys_addr;
215
216 for (i = 0; i < num_desc; i++) {
217 cppi41_queue_push(&dma_teardown[dma_num].queue_obj, td_addr,
218 sizeof(*curr_td), 0);
219 td_addr += sizeof(*curr_td);
220 }
221
222 /* Initialize the DMA scheduler. */
223 num_reg = (tbl_size + 3) / 4;
224 for (i = 0; i < num_reg; i++) {
225 val = sched_tbl[i];
226 __raw_writel(val, dma_block->sched_table_base +
227 DMA_SCHED_TABLE_WORD_REG(i));
228 DBG("DMA scheduler table @ %p, value written: %x\n",
229 dma_block->sched_table_base + DMA_SCHED_TABLE_WORD_REG(i),
230 val);
231 }
232
233 __raw_writel((tbl_size - 1) << DMA_SCHED_LAST_ENTRY_SHIFT |
234 DMA_SCHED_ENABLE_MASK,
235 dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG);
236 DBG("DMA scheduler control @ %p, value: %x\n",
237 dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG,
238 __raw_readl(dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG));
239
240 return 0;
241
242 free_rgn:
243 cppi41_mem_rgn_free(q_mgr, dma_teardown[dma_num].mem_rgn);
244 free_mem:
245 dma_free_coherent(NULL, dma_teardown[dma_num].rgn_size,
246 dma_teardown[dma_num].virt_addr,
247 dma_teardown[dma_num].phys_addr);
248 free_queue:
249 cppi41_queue_free(q_mgr, q_num);
250 return error;
251 }
252 EXPORT_SYMBOL(cppi41_dma_block_init);
253
254 /*
255 * cppi41_mem_rgn_alloc - allocate a memory region within the queue manager
256 */
257 int cppi41_mem_rgn_alloc(u8 q_mgr, dma_addr_t rgn_addr, u8 size_order,
258 u8 num_order, u8 *mem_rgn)
259 {
260 void __iomem *desc_mem_regs;
261 u32 num_desc = 1 << num_order, index, ctrl;
262 int rgn;
263
264 DBG("%s called with rgn_addr = %08x, size_order = %d, num_order = %d\n",
265 __func__, rgn_addr, size_order, num_order);
266
267 if (q_mgr >= cppi41_num_queue_mgr ||
268 size_order < 5 || size_order > 13 ||
269 num_order < 5 || num_order > 12 ||
270 (rgn_addr & ((1 << size_order) - 1)))
271 return -EINVAL;
272
273 rgn = next_mem_rgn[q_mgr];
274 index = next_desc_index[q_mgr];
275 if (rgn >= CPPI41_MAX_MEM_RGN || index + num_desc > 0x4000)
276 return -ENOSPC;
277
278 next_mem_rgn[q_mgr] = rgn + 1;
279 next_desc_index[q_mgr] = index + num_desc;
280
281 desc_mem_regs = cppi41_queue_mgr[q_mgr].desc_mem_rgn_base;
282
283 /* Write the base register */
284 __raw_writel(rgn_addr, desc_mem_regs + QMGR_MEM_RGN_BASE_REG(rgn));
285 DBG("Descriptor region base @ %p, value: %x\n",
286 desc_mem_regs + QMGR_MEM_RGN_BASE_REG(rgn),
287 __raw_readl(desc_mem_regs + QMGR_MEM_RGN_BASE_REG(rgn)));
288
289 /* Write the control register */
290 ctrl = ((index << QMGR_MEM_RGN_INDEX_SHIFT) &
291 QMGR_MEM_RGN_INDEX_MASK) |
292 (((size_order - 5) << QMGR_MEM_RGN_DESC_SIZE_SHIFT) &
293 QMGR_MEM_RGN_DESC_SIZE_MASK) |
294 (((num_order - 5) << QMGR_MEM_RGN_SIZE_SHIFT) &
295 QMGR_MEM_RGN_SIZE_MASK);
296 __raw_writel(ctrl, desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(rgn));
297 DBG("Descriptor region control @ %p, value: %x\n",
298 desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(rgn),
299 __raw_readl(desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(rgn)));
300
301 *mem_rgn = rgn;
302 return 0;
303 }
304 EXPORT_SYMBOL(cppi41_mem_rgn_alloc);
305
306 /*
307 * cppi41_mem_rgn_free - free the memory region within the queue manager
308 */
309 int cppi41_mem_rgn_free(u8 q_mgr, u8 mem_rgn)
310 {
311 void __iomem *desc_mem_regs;
312
313 DBG("%s called.\n", __func__);
314
315 if (q_mgr >= cppi41_num_queue_mgr || mem_rgn >= next_mem_rgn[q_mgr])
316 return -EINVAL;
317
318 desc_mem_regs = cppi41_queue_mgr[q_mgr].desc_mem_rgn_base;
319
320 if (__raw_readl(desc_mem_regs + QMGR_MEM_RGN_BASE_REG(mem_rgn)) == 0)
321 return -ENOENT;
322
323 __raw_writel(0, desc_mem_regs + QMGR_MEM_RGN_BASE_REG(mem_rgn));
324 __raw_writel(0, desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(mem_rgn));
325
326 return 0;
327 }
328 EXPORT_SYMBOL(cppi41_mem_rgn_free);
329
330 /*
331 * cppi41_tx_ch_init - initialize a CPPI 4.1 Tx channel object
332 *
333 * Verify the channel info (range checking, etc.) and store the channel
334 * information within the object structure.
335 */
336 int cppi41_tx_ch_init(struct cppi41_dma_ch_obj *tx_ch_obj,
337 u8 dma_num, u8 ch_num)
338 {
339 if (dma_num >= cppi41_num_dma_block ||
340 ch_num >= cppi41_dma_block[dma_num].num_tx_ch)
341 return -EINVAL;
342
343 /* Populate the channel object structure */
344 tx_ch_obj->base_addr = cppi41_dma_block[dma_num].ch_ctrl_stat_base +
345 DMA_CH_TX_GLOBAL_CFG_REG(ch_num);
346 tx_ch_obj->global_cfg = __raw_readl(tx_ch_obj->base_addr);
347 return 0;
348 }
349 EXPORT_SYMBOL(cppi41_tx_ch_init);
350
351 /*
352 * cppi41_rx_ch_init - initialize a CPPI 4.1 Rx channel object
353 *
354 * Verify the channel info (range checking, etc.) and store the channel
355 * information within the object structure.
356 */
357 int cppi41_rx_ch_init(struct cppi41_dma_ch_obj *rx_ch_obj,
358 u8 dma_num, u8 ch_num)
359 {
360 if (dma_num >= cppi41_num_dma_block ||
361 ch_num >= cppi41_dma_block[dma_num].num_rx_ch)
362 return -EINVAL;
363
364 /* Populate the channel object structure */
365 rx_ch_obj->base_addr = cppi41_dma_block[dma_num].ch_ctrl_stat_base +
366 DMA_CH_RX_GLOBAL_CFG_REG(ch_num);
367 rx_ch_obj->global_cfg = __raw_readl(rx_ch_obj->base_addr);
368 return 0;
369 }
370 EXPORT_SYMBOL(cppi41_rx_ch_init);
371
372 /*
373 * We have to cache the last written Rx/Tx channel global configration register
374 * value due to its bits other than enable/teardown being write-only. Yet there
375 * is a caveat related to caching the enable bit: this bit may be automatically
376 * cleared as a result of teardown, so we can't trust its cached value!
377 * When modifying the write only register fields, we're making use of the fact
378 * that they read back as zeros, and not clearing them explicitly...
379 */
380
381 /*
382 * cppi41_dma_ch_default_queue - set CPPI 4.1 channel default completion queue
383 */
384 void cppi41_dma_ch_default_queue(struct cppi41_dma_ch_obj *dma_ch_obj,
385 u8 q_mgr, u16 q_num)
386 {
387 u32 val = dma_ch_obj->global_cfg;
388
389 /* Clear the fields to be modified. */
390 val &= ~(DMA_CH_TX_DEFAULT_QMGR_MASK | DMA_CH_TX_DEFAULT_QNUM_MASK |
391 DMA_CH_TX_ENABLE_MASK);
392
393 /* Set the default completion queue. */
394 val |= ((q_mgr << DMA_CH_TX_DEFAULT_QMGR_SHIFT) &
395 DMA_CH_TX_DEFAULT_QMGR_MASK) |
396 ((q_num << DMA_CH_TX_DEFAULT_QNUM_SHIFT) &
397 DMA_CH_TX_DEFAULT_QNUM_MASK);
398
399 /* Get the current state of the enable bit. */
400 dma_ch_obj->global_cfg = val |= __raw_readl(dma_ch_obj->base_addr);
401 __raw_writel(val, dma_ch_obj->base_addr);
402 DBG("Channel global configuration @ %p, value written: %x, "
403 "value read: %x\n", dma_ch_obj->base_addr, val,
404 __raw_readl(dma_ch_obj->base_addr));
405
406 }
407 EXPORT_SYMBOL(cppi41_dma_ch_default_queue);
408
409 /*
410 * cppi41_rx_ch_configure - configure CPPI 4.1 Rx channel
411 */
412 void cppi41_rx_ch_configure(struct cppi41_dma_ch_obj *rx_ch_obj,
413 struct cppi41_rx_ch_cfg *cfg)
414 {
415 void __iomem *base = rx_ch_obj->base_addr;
416 u32 val = __raw_readl(rx_ch_obj->base_addr);
417
418 val |= ((cfg->sop_offset << DMA_CH_RX_SOP_OFFSET_SHIFT) &
419 DMA_CH_RX_SOP_OFFSET_MASK) |
420 ((cfg->default_desc_type << DMA_CH_RX_DEFAULT_DESC_TYPE_SHIFT) &
421 DMA_CH_RX_DEFAULT_DESC_TYPE_MASK) |
422 ((cfg->retry_starved << DMA_CH_RX_ERROR_HANDLING_SHIFT) &
423 DMA_CH_RX_ERROR_HANDLING_MASK) |
424 ((cfg->rx_queue.q_mgr << DMA_CH_RX_DEFAULT_RQ_QMGR_SHIFT) &
425 DMA_CH_RX_DEFAULT_RQ_QMGR_MASK) |
426 ((cfg->rx_queue.q_num << DMA_CH_RX_DEFAULT_RQ_QNUM_SHIFT) &
427 DMA_CH_RX_DEFAULT_RQ_QNUM_MASK);
428
429 rx_ch_obj->global_cfg = val;
430 __raw_writel(val, base);
431 DBG("Rx channel global configuration @ %p, value written: %x, "
432 "value read: %x\n", base, val, __raw_readl(base));
433
434 base -= DMA_CH_RX_GLOBAL_CFG_REG(0);
435
436 /*
437 * Set up the packet configuration register
438 * based on the descriptor type...
439 */
440 switch (cfg->default_desc_type) {
441 case DMA_CH_RX_DEFAULT_DESC_EMBED:
442 val = ((cfg->cfg.embed_pkt.fd_queue.q_mgr <<
443 DMA_CH_RX_EMBED_FDQ_QMGR_SHIFT) &
444 DMA_CH_RX_EMBED_FDQ_QMGR_MASK) |
445 ((cfg->cfg.embed_pkt.fd_queue.q_num <<
446 DMA_CH_RX_EMBED_FDQ_QNUM_SHIFT) &
447 DMA_CH_RX_EMBED_FDQ_QNUM_MASK) |
448 ((cfg->cfg.embed_pkt.num_buf_slot <<
449 DMA_CH_RX_EMBED_NUM_SLOT_SHIFT) &
450 DMA_CH_RX_EMBED_NUM_SLOT_MASK) |
451 ((cfg->cfg.embed_pkt.sop_slot_num <<
452 DMA_CH_RX_EMBED_SOP_SLOT_SHIFT) &
453 DMA_CH_RX_EMBED_SOP_SLOT_MASK);
454
455 __raw_writel(val, base + DMA_CH_RX_EMBED_PKT_CFG_REG_B(0));
456 DBG("Rx channel embedded packet configuration B @ %p, "
457 "value written: %x\n",
458 base + DMA_CH_RX_EMBED_PKT_CFG_REG_B(0), val);
459
460 val = ((cfg->cfg.embed_pkt.free_buf_pool[0].b_pool <<
461 DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(0)) &
462 DMA_CH_RX_EMBED_FBP_PNUM_MASK(0)) |
463 ((cfg->cfg.embed_pkt.free_buf_pool[0].b_mgr <<
464 DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(0)) &
465 DMA_CH_RX_EMBED_FBP_BMGR_MASK(0)) |
466 ((cfg->cfg.embed_pkt.free_buf_pool[1].b_pool <<
467 DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(1)) &
468 DMA_CH_RX_EMBED_FBP_PNUM_MASK(1)) |
469 ((cfg->cfg.embed_pkt.free_buf_pool[1].b_mgr <<
470 DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(1)) &
471 DMA_CH_RX_EMBED_FBP_BMGR_MASK(1)) |
472 ((cfg->cfg.embed_pkt.free_buf_pool[2].b_pool <<
473 DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(2)) &
474 DMA_CH_RX_EMBED_FBP_PNUM_MASK(2)) |
475 ((cfg->cfg.embed_pkt.free_buf_pool[2].b_mgr <<
476 DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(2)) &
477 DMA_CH_RX_EMBED_FBP_BMGR_MASK(2)) |
478 ((cfg->cfg.embed_pkt.free_buf_pool[3].b_pool <<
479 DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(3)) &
480 DMA_CH_RX_EMBED_FBP_PNUM_MASK(3)) |
481 ((cfg->cfg.embed_pkt.free_buf_pool[3].b_mgr <<
482 DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(3)) &
483 DMA_CH_RX_EMBED_FBP_BMGR_MASK(3));
484
485 __raw_writel(val, base + DMA_CH_RX_EMBED_PKT_CFG_REG_A(0));
486 DBG("Rx channel embedded packet configuration A @ %p, "
487 "value written: %x\n",
488 base + DMA_CH_RX_EMBED_PKT_CFG_REG_A(0), val);
489 break;
490 case DMA_CH_RX_DEFAULT_DESC_HOST:
491 val = ((cfg->cfg.host_pkt.fdb_queue[0].q_num <<
492 DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(0)) &
493 DMA_CH_RX_HOST_FDQ_QNUM_MASK(0)) |
494 ((cfg->cfg.host_pkt.fdb_queue[0].q_mgr <<
495 DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(0)) &
496 DMA_CH_RX_HOST_FDQ_QMGR_MASK(0)) |
497 ((cfg->cfg.host_pkt.fdb_queue[1].q_num <<
498 DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(1)) &
499 DMA_CH_RX_HOST_FDQ_QNUM_MASK(1)) |
500 ((cfg->cfg.host_pkt.fdb_queue[1].q_mgr <<
501 DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(1)) &
502 DMA_CH_RX_HOST_FDQ_QMGR_MASK(1));
503
504 __raw_writel(val, base + DMA_CH_RX_HOST_PKT_CFG_REG_A(0));
505 DBG("Rx channel host packet configuration A @ %p, "
506 "value written: %x\n",
507 base + DMA_CH_RX_HOST_PKT_CFG_REG_A(0), val);
508
509 val = ((cfg->cfg.host_pkt.fdb_queue[2].q_num <<
510 DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(2)) &
511 DMA_CH_RX_HOST_FDQ_QNUM_MASK(2)) |
512 ((cfg->cfg.host_pkt.fdb_queue[2].q_mgr <<
513 DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(2)) &
514 DMA_CH_RX_HOST_FDQ_QMGR_MASK(2)) |
515 ((cfg->cfg.host_pkt.fdb_queue[3].q_num <<
516 DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(3)) &
517 DMA_CH_RX_HOST_FDQ_QNUM_MASK(3)) |
518 ((cfg->cfg.host_pkt.fdb_queue[3].q_mgr <<
519 DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(3)) &
520 DMA_CH_RX_HOST_FDQ_QMGR_MASK(3));
521
522 __raw_writel(val, base + DMA_CH_RX_HOST_PKT_CFG_REG_B(0));
523 DBG("Rx channel host packet configuration B @ %p, "
524 "value written: %x\n",
525 base + DMA_CH_RX_HOST_PKT_CFG_REG_B(0), val);
526 break;
527 case DMA_CH_RX_DEFAULT_DESC_MONO:
528 val = ((cfg->cfg.mono_pkt.fd_queue.q_num <<
529 DMA_CH_RX_MONO_FDQ_QNUM_SHIFT) &
530 DMA_CH_RX_MONO_FDQ_QNUM_MASK) |
531 ((cfg->cfg.mono_pkt.fd_queue.q_mgr <<
532 DMA_CH_RX_MONO_FDQ_QMGR_SHIFT) &
533 DMA_CH_RX_MONO_FDQ_QMGR_MASK) |
534 ((cfg->cfg.mono_pkt.sop_offset <<
535 DMA_CH_RX_MONO_SOP_OFFSET_SHIFT) &
536 DMA_CH_RX_MONO_SOP_OFFSET_MASK);
537
538 __raw_writel(val, base + DMA_CH_RX_MONO_PKT_CFG_REG(0));
539 DBG("Rx channel monolithic packet configuration @ %p, "
540 "value written: %x\n",
541 base + DMA_CH_RX_MONO_PKT_CFG_REG(0), val);
542 break;
543 }
544 }
545 EXPORT_SYMBOL(cppi41_rx_ch_configure);
546
547 /*
548 * cppi41_dma_ch_teardown - teardown a given Tx/Rx channel
549 */
550 void cppi41_dma_ch_teardown(struct cppi41_dma_ch_obj *dma_ch_obj)
551 {
552 u32 val = __raw_readl(dma_ch_obj->base_addr);
553
554 /* Initiate channel teardown. */
555 val |= dma_ch_obj->global_cfg & ~DMA_CH_TX_ENABLE_MASK;
556 dma_ch_obj->global_cfg = val |= DMA_CH_TX_TEARDOWN_MASK;
557 __raw_writel(val, dma_ch_obj->base_addr);
558 DBG("Tear down channel @ %p, value written: %x, value read: %x\n",
559 dma_ch_obj->base_addr, val, __raw_readl(dma_ch_obj->base_addr));
560 }
561 EXPORT_SYMBOL(cppi41_dma_ch_teardown);
562
563 /*
564 * cppi41_dma_ch_enable - enable Tx/Rx DMA channel in hardware
565 *
566 * Makes the channel ready for data transmission/reception.
567 */
568 void cppi41_dma_ch_enable(struct cppi41_dma_ch_obj *dma_ch_obj)
569 {
570 u32 val = dma_ch_obj->global_cfg | DMA_CH_TX_ENABLE_MASK;
571
572 /* Teardown bit remains set after completion, so clear it now... */
573 dma_ch_obj->global_cfg = val &= ~DMA_CH_TX_TEARDOWN_MASK;
574 __raw_writel(val, dma_ch_obj->base_addr);
575 DBG("Enable channel @ %p, value written: %x, value read: %x\n",
576 dma_ch_obj->base_addr, val, __raw_readl(dma_ch_obj->base_addr));
577 }
578 EXPORT_SYMBOL(cppi41_dma_ch_enable);
579
580 /*
581 * cppi41_dma_ch_disable - disable Tx/Rx DMA channel in hardware
582 */
583 void cppi41_dma_ch_disable(struct cppi41_dma_ch_obj *dma_ch_obj)
584 {
585 dma_ch_obj->global_cfg &= ~DMA_CH_TX_ENABLE_MASK;
586 __raw_writel(dma_ch_obj->global_cfg, dma_ch_obj->base_addr);
587 DBG("Disable channel @ %p, value written: %x, value read: %x\n",
588 dma_ch_obj->base_addr, dma_ch_obj->global_cfg,
589 __raw_readl(dma_ch_obj->base_addr));
590 }
591 EXPORT_SYMBOL(cppi41_dma_ch_disable);
592
593 void cppi41_free_teardown_queue(int dma_num)
594 {
595 unsigned long td_addr;
596
597 while ((td_addr =
598 cppi41_queue_pop(&dma_teardown[dma_num].queue_obj)) != 0)
599 DBG("pop tdDesc(%p) from tdQueue\n", td_addr);
600 }
601 EXPORT_SYMBOL(cppi41_free_teardown_queue);
602
603 void cppi41_exit(void)
604 {
605 int i;
606 for (i = 0; i < CPPI41_NUM_QUEUE_MGR; i++) {
607 if (linking_ram[i].virt_addr != NULL)
608 dma_free_coherent(NULL, 0x10000,
609 linking_ram[i].virt_addr,
610 linking_ram[i].phys_addr);
611 if (allocated_queues[i] != NULL)
612 kfree(allocated_queues[i]);
613 }
614 for (i = 0; i < CPPI41_NUM_DMA_BLOCK; i++)
615 if (dma_teardown[i].virt_addr != NULL) {
616
617 cppi41_mem_rgn_free(0, dma_teardown[i].mem_rgn);
618 dma_free_coherent(NULL, dma_teardown[i].rgn_size,
619 dma_teardown[i].virt_addr,
620 dma_teardown[i].phys_addr);
621 }
622 }
623 EXPORT_SYMBOL(cppi41_exit);
624
625 /**
626 * alloc_queue - allocate a queue in the given range
627 * @allocated: pointer to the bitmap of the allocated queues
628 * @excluded: pointer to the bitmap of the queues excluded from allocation
629 * (optional)
630 * @start: starting queue number
631 * @count: number of queues available
632 *
633 * Returns queue number on success, -ENOSPC otherwise.
634 */
635 static int alloc_queue(u32 *allocated, const u32 *excluded, unsigned start,
636 unsigned count)
637 {
638 u32 bit, mask = 0;
639 int index = -1;
640
641 /*
642 * We're starting the loop as if we've just wrapped around 32 bits
643 * in order to save on preloading the bitmasks.
644 */
645 for (bit = 0; count--; start++, bit <<= 1) {
646 /* Have we just wrapped around 32 bits? */
647 if (!bit) {
648 /* Start over with the next bitmask word */
649 bit = 1;
650 index++;
651 /* Have we just entered the loop? */
652 if (!index) {
653 /* Calculate the starting values */
654 bit <<= start & 0x1f;
655 index = start >> 5;
656 }
657 /*
658 * Load the next word of the allocated bitmask OR'ing
659 * it with the excluded bitmask if it's been passed.
660 */
661 mask = allocated[index];
662 if (excluded != NULL)
663 mask |= excluded[index];
664 }
665 /*
666 * If the bit in the combined bitmask is zero,
667 * we've just found a free queue.
668 */
669 if (!(mask & bit)) {
670 allocated[index] |= bit;
671 return start;
672 }
673 }
674 return -ENOSPC;
675 }
676
677 /*
678 * cppi41_queue_alloc - allocate a queue of a given type in the queue manager
679 */
680 int cppi41_queue_alloc(u8 type, u8 q_mgr, u16 *q_num)
681 {
682 int res = -ENOSPC;
683
684 if (q_mgr >= cppi41_num_queue_mgr)
685 return -EINVAL;
686
687 /* Mask out the unsupported queue types */
688 type &= cppi41_queue_mgr[q_mgr].queue_types;
689 /* First see if a free descriptor queue was requested... */
690 if (type & CPPI41_FREE_DESC_QUEUE)
691 res = alloc_queue(allocated_queues[q_mgr], NULL,
692 cppi41_queue_mgr[q_mgr].base_fdq_num, 16);
693
694 /* Then see if a free descriptor/buffer queue was requested... */
695 if (res < 0 && (type & CPPI41_FREE_DESC_BUF_QUEUE))
696 res = alloc_queue(allocated_queues[q_mgr], NULL,
697 cppi41_queue_mgr[q_mgr].base_fdbq_num, 16);
698
699 /* Last see if an unassigned queue was requested... */
700 if (res < 0 && (type & CPPI41_UNASSIGNED_QUEUE))
701 res = alloc_queue(allocated_queues[q_mgr],
702 cppi41_queue_mgr[q_mgr].assigned, 0,
703 cppi41_queue_mgr[q_mgr].num_queue);
704
705 /* See if any queue was allocated... */
706 if (res < 0)
707 return res;
708
709 /* Return the queue allocated */
710 *q_num = res;
711 return 0;
712 }
713 EXPORT_SYMBOL(cppi41_queue_alloc);
714
715 /*
716 * cppi41_queue_free - free the given queue in the queue manager
717 */
718 int cppi41_queue_free(u8 q_mgr, u16 q_num)
719 {
720 int index = q_num >> 5, bit = 1 << (q_num & 0x1f);
721
722 if (q_mgr >= cppi41_num_queue_mgr ||
723 q_num >= cppi41_queue_mgr[q_mgr].num_queue ||
724 !(allocated_queues[q_mgr][index] & bit))
725 return -EINVAL;
726
727 allocated_queues[q_mgr][index] &= ~bit;
728 return 0;
729 }
730 EXPORT_SYMBOL(cppi41_queue_free);
731
732 /*
733 * cppi41_queue_init - initialize a CPPI 4.1 queue object
734 */
735 int cppi41_queue_init(struct cppi41_queue_obj *queue_obj, u8 q_mgr, u16 q_num)
736 {
737 if (q_mgr >= cppi41_num_queue_mgr ||
738 q_num >= cppi41_queue_mgr[q_mgr].num_queue)
739 return -EINVAL;
740
741 queue_obj->base_addr = cppi41_queue_mgr[q_mgr].q_mgmt_rgn_base +
742 QMGR_QUEUE_STATUS_REG_A(q_num);
743
744 return 0;
745 }
746 EXPORT_SYMBOL(cppi41_queue_init);
747
748 /*
749 * cppi41_queue_push - push a descriptor into the given queue
750 */
751 void cppi41_queue_push(const struct cppi41_queue_obj *queue_obj, u32 desc_addr,
752 u32 desc_size, u32 pkt_size)
753 {
754 u32 val;
755
756 /*
757 * Write to the tail of the queue.
758 * TODO: Can't think of a reason why a queue to head may be required.
759 * If it is, the API may have to be extended.
760 */
761 #if 0
762 /*
763 * Also, can't understand why packet size is required to queue up a
764 * descriptor. The spec says packet size *must* be written prior to
765 * the packet write operation.
766 */
767 if (pkt_size)
768 val = (pkt_size << QMGR_QUEUE_PKT_SIZE_SHIFT) &
769 QMGR_QUEUE_PKT_SIZE_MASK;
770 __raw_writel(val, queue_obj->base_addr + QMGR_QUEUE_REG_C(0));
771 #endif
772
773 val = (((desc_size - 24) >> (2 - QMGR_QUEUE_DESC_SIZE_SHIFT)) &
774 QMGR_QUEUE_DESC_SIZE_MASK) |
775 (desc_addr & QMGR_QUEUE_DESC_PTR_MASK);
776
777 DBG("Pushing value %x to queue @ %p\n", val, queue_obj->base_addr);
778
779 __raw_writel(val, queue_obj->base_addr + QMGR_QUEUE_REG_D(0));
780 }
781 EXPORT_SYMBOL(cppi41_queue_push);
782
783 /*
784 * cppi41_queue_pop - pop a descriptor from a given queue
785 */
786 unsigned long cppi41_queue_pop(const struct cppi41_queue_obj *queue_obj)
787 {
788 u32 val = __raw_readl(queue_obj->base_addr + QMGR_QUEUE_REG_D(0));
789
790 DBG("Popping value %x from queue @ %p\n", val, queue_obj->base_addr);
791
792 return val & QMGR_QUEUE_DESC_PTR_MASK;
793 }
794 EXPORT_SYMBOL(cppi41_queue_pop);
795
796 /*
797 * cppi41_get_teardown_info - extract information from a teardown descriptor
798 */
799 int cppi41_get_teardown_info(unsigned long addr, u32 *info)
800 {
801 struct cppi41_teardown_desc *desc;
802 int dma_num;
803
804 for (dma_num = 0; dma_num < cppi41_num_dma_block; dma_num++)
805 if (addr >= dma_teardown[dma_num].phys_addr &&
806 addr < dma_teardown[dma_num].phys_addr +
807 dma_teardown[dma_num].rgn_size)
808 break;
809
810 if (dma_num == cppi41_num_dma_block)
811 return -EINVAL;
812
813 desc = addr - dma_teardown[dma_num].phys_addr +
814 dma_teardown[dma_num].virt_addr;
815
816 if ((desc->teardown_info & CPPI41_DESC_TYPE_MASK) !=
817 (CPPI41_DESC_TYPE_TEARDOWN << CPPI41_DESC_TYPE_SHIFT))
818 return -EINVAL;
819
820 *info = desc->teardown_info;
821 #if 1
822 /* Hardware is not giving the current DMA number as of now. :-/ */
823 *info |= (dma_num << CPPI41_TEARDOWN_DMA_NUM_SHIFT) &
824 CPPI41_TEARDOWN_DMA_NUM_MASK;
825 #else
826 dma_num = (desc->teardown_info & CPPI41_TEARDOWN_DMA_NUM_MASK) >>
827 CPPI41_TEARDOWN_DMA_NUM_SHIFT;
828 #endif
829
830 cppi41_queue_push(&dma_teardown[dma_num].queue_obj, addr,
831 sizeof(struct cppi41_teardown_desc), 0);
832
833 return 0;
834 }
835 EXPORT_SYMBOL(cppi41_get_teardown_info);
836
837 MODULE_DESCRIPTION("TI CPPI 4.1 support");
838 MODULE_AUTHOR("MontaVista Software");
839 MODULE_LICENSE("GPL");
Linux for Ginger Game Console