drivers/usb/musb/cppi41.h

   1 /*
   2  * CPPI 4.1 definitions
   3  *
   4  * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
   5  *
   6  * This program is free software; you can distribute it and/or modify it
   7  * under the terms of the GNU General Public License (Version 2) as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, write to the Free Software Foundation, Inc.,
  17  * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  18  *
  19  */
  20
  21 #include <linux/types.h>
  22
  23 /*
  24  * Queue Manager - Control Registers Region
  25  */
  26 #define QMGR_REVISION_REG               0x00    /* Major and minor versions */
  27                                                 /* of the module */
  28 #define QMGR_QUEUE_DIVERSION_REG        0x08    /* Queue Diversion register */
  29 #define QMGR_FREE_DESC_BUF_STARVED_REG(n) (0x20 + ((n) << 2)) /* Free Desc./ */
  30                                                 /* Buffer Starvation Count */
  31 #define QMGR_FREE_DESC_STARVED_REG(n)   (0x30 + ((n) << 2)) /* Free Desc. */
  32                                                 /* Starvation Count */
  33 #define QMGR_LINKING_RAM_RGN0_BASE_REG  0x80    /* Linking RAM Region 0 Base */
  34                                                 /* Address */
  35 #define QMGR_LINKING_RAM_RGN0_SIZE_REG  0x84    /* Linking RAM Region 0 Size */
  36 #define QMGR_LINKING_RAM_RGN1_BASE_REG  0x88    /* Linking RAM Region 1 Base */
  37                                                 /* Address */
  38 #define QMGR_QUEUE_PENDING_REG(n)       (0x90 + ((n) << 2)) /* Pending status */
  39                                                 /* for all queues */
  40
  41 /*
  42  * Queue Manager - Memory Region Registers
  43  */
  44 #define QMGR_MEM_RGN_BASE_REG(r)        (0x00 + ((r) << 4))
  45 #define QMGR_MEM_RGN_CTRL_REG(r)        (0x04 + ((r) << 4))
  46
  47 /* Memory Region R Control Register bits */
  48 #define QMGR_MEM_RGN_INDEX_SHIFT        16
  49 #define QMGR_MEM_RGN_INDEX_MASK         (0x3fff << QMGR_MEM_RGN_INDEX_SHIFT)
  50 #define QMGR_MEM_RGN_DESC_SIZE_SHIFT    8
  51 #define QMGR_MEM_RGN_DESC_SIZE_MASK     (0xf << QMGR_MEM_RGN_DESC_SIZE_SHIFT)
  52 #define QMGR_MEM_RGN_SIZE_SHIFT         0
  53 #define QMGR_MEM_RGN_SIZE_MASK          (7 << QMGR_MEM_RGN_SIZE_SHIFT)
  54
  55 /*
  56  * Queue Manager - Queues Region
  57  */
  58 #define QMGR_QUEUE_REG_A(n)             (0x00 + ((n) << 4))
  59 #define QMGR_QUEUE_REG_B(n)             (0x04 + ((n) << 4))
  60 #define QMGR_QUEUE_REG_C(n)             (0x08 + ((n) << 4))
  61 #define QMGR_QUEUE_REG_D(n)             (0x0C + ((n) << 4))
  62
  63 /* Queue N Register C bits */
  64 #define QMGR_QUEUE_HEAD_TAIL_SHIFT      31
  65 #define QMGR_QUEUE_HEAD_TAIL_MASK       (1 << QMGR_QUEUE_HEAD_TAIL_SHIFT)
  66 #define QMGR_QUEUE_PKT_SIZE_SHIFT       0
  67 #define QMGR_QUEUE_PKT_SIZE_MASK        (0x3fff << QMGR_QUEUE_PKT_SIZE_SHIFT)
  68 /* Queue N Register D bits */
  69 #define QMGR_QUEUE_DESC_PTR_SHIFT       5
  70 #define QMGR_QUEUE_DESC_PTR_MASK        (0x7ffffff << QMGR_QUEUE_DESC_PTR_SHIFT)
  71 #define QMGR_QUEUE_DESC_SIZE_SHIFT      0
  72 #define QMGR_QUEUE_DESC_SIZE_MASK       (0x1f << QMGR_QUEUE_DESC_SIZE_SHIFT)
  73
  74 /*
  75  * Queue Manager - Queue Status Region
  76  */
  77 #define QMGR_QUEUE_STATUS_REG_A(n)      (0x00 + ((n) << 4))
  78 #define QMGR_QUEUE_STATUS_REG_B(n)      (0x04 + ((n) << 4))
  79 #define QMGR_QUEUE_STATUS_REG_C(n)      (0x08 + ((n) << 4))
  80
  81 /*
  82  * DMA Controller - Global Control Registers Region
  83  */
  84 #define DMA_REVISION_REG                0x00    /* Major and minor versions */
  85                                                 /* of the module */
  86 #define DMA_TEARDOWN_FREE_DESC_CTRL_REG 0x04    /* Queue  manager and queue */
  87                                                 /* number for Teardown free */
  88                                                 /* descriptor queue */
  89 #define DMA_EMULATION_CTRL_REG          0x08    /* Emulation control register */
  90
  91 /* Teardown Free Descriptor Queue Control Register bits */
  92 #define DMA_TD_DESC_QMGR_SHIFT          12
  93 #define DMA_TD_DESC_QMGR_MASK           (3 << DMA_TD_DESC_QMGR_SHIFT)
  94 #define DMA_TD_DESC_QNUM_SHIFT          0
  95 #define DMA_TD_DESC_QNUM_MASK           (0xfff << DMA_TD_DESC_QNUM_SHIFT)
  96
  97 /*
  98  * DMA Controller - Channel Control / Status Registers Region
  99  */
 100 #define DMA_CH_TX_GLOBAL_CFG_REG(n)      (0x00 + ((n) << 5))
 101 #define DMA_CH_RX_GLOBAL_CFG_REG(n)      (0x08 + ((n) << 5))
 102 #define DMA_CH_RX_HOST_PKT_CFG_REG_A(n)  (0x0C + ((n) << 5))
 103 #define DMA_CH_RX_HOST_PKT_CFG_REG_B(n)  (0x10 + ((n) << 5))
 104 #define DMA_CH_RX_EMBED_PKT_CFG_REG_A(n) (0x14 + ((n) << 5))
 105 #define DMA_CH_RX_EMBED_PKT_CFG_REG_B(n) (0x18 + ((n) << 5))
 106 #define DMA_CH_RX_MONO_PKT_CFG_REG(n)    (0x1C + ((n) << 5))
 107
 108 /* Tx Channel N Global Configuration Register bits */
 109 #define DMA_CH_TX_ENABLE_SHIFT          31
 110 #define DMA_CH_TX_ENABLE_MASK           (1 << DMA_CH_TX_ENABLE_SHIFT)
 111 #define DMA_CH_TX_TEARDOWN_SHIFT        30
 112 #define DMA_CH_TX_TEARDOWN_MASK         (1 << DMA_CH_TX_TEARDOWN_SHIFT)
 113 #define DMA_CH_TX_DEFAULT_QMGR_SHIFT    12
 114 #define DMA_CH_TX_DEFAULT_QMGR_MASK     (3 << DMA_CH_TX_DEFAULT_QMGR_SHIFT)
 115 #define DMA_CH_TX_DEFAULT_QNUM_SHIFT    0
 116 #define DMA_CH_TX_DEFAULT_QNUM_MASK     (0xfff << DMA_CH_TX_DEFAULT_QNUM_SHIFT)
 117
 118 /* Rx Channel N Global Configuration Register bits */
 119 #define DMA_CH_RX_ENABLE_SHIFT          31
 120 #define DMA_CH_RX_ENABLE_MASK           (1 << DMA_CH_RX_ENABLE_SHIFT)
 121 #define DMA_CH_RX_TEARDOWN_SHIFT        30
 122 #define DMA_CH_RX_TEARDOWN_MASK         (1 << DMA_CH_RX_TEARDOWN_SHIFT)
 123 #define DMA_CH_RX_ERROR_HANDLING_SHIFT  24
 124 #define DMA_CH_RX_ERROR_HANDLING_MASK   (1 << DMA_CH_RX_ERROR_HANDLING_SHIFT)
 125 #define DMA_CH_RX_SOP_OFFSET_SHIFT      16
 126 #define DMA_CH_RX_SOP_OFFSET_MASK       (0xff << DMA_CH_RX_SOP_OFFSET_SHIFT)
 127 #define DMA_CH_RX_DEFAULT_DESC_TYPE_SHIFT 14
 128 #define DMA_CH_RX_DEFAULT_DESC_TYPE_MASK  (3 << \
 129                                            DMA_CH_RX_DEFAULT_DESC_TYPE_SHIFT)
 130 #define DMA_CH_RX_DEFAULT_DESC_EMBED    0
 131 #define DMA_CH_RX_DEFAULT_DESC_HOST     1
 132 #define DMA_CH_RX_DEFAULT_DESC_MONO     2
 133 #define DMA_CH_RX_DEFAULT_RQ_QMGR_SHIFT 12
 134 #define DMA_CH_RX_DEFAULT_RQ_QMGR_MASK  (3 << DMA_CH_RX_DEFAULT_RQ_QMGR_SHIFT)
 135 #define DMA_CH_RX_DEFAULT_RQ_QNUM_SHIFT 0
 136 #define DMA_CH_RX_DEFAULT_RQ_QNUM_MASK  (0xfff << \
 137                                          DMA_CH_RX_DEFAULT_RQ_QNUM_SHIFT)
 138
 139 /* Rx Channel N Host Packet Configuration Register A/B bits */
 140 #define DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(n) (12 + 16 * ((n) & 1))
 141 #define DMA_CH_RX_HOST_FDQ_QMGR_MASK(n)  (3 << DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(n))
 142 #define DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(n) (0 + 16 * ((n) & 1))
 143 #define DMA_CH_RX_HOST_FDQ_QNUM_MASK(n)  (0xfff << \
 144                                           DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(n))
 145
 146 /* Rx Channel N Embedded Packet Configuration Register A bits */
 147 #define DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(n) (6 + 8 * (n))
 148 #define DMA_CH_RX_EMBED_FBP_BMGR_MASK(n)  (3 << \
 149                                            DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(n))
 150 #define DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(n) (0 + 8 * (n))
 151 #define DMA_CH_RX_EMBED_FBP_PNUM_MASK(n)  (0x1f << \
 152                                            DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(n))
 153
 154 /* Rx Channel N Embedded Packet Configuration Register B bits */
 155 #define DMA_CH_RX_EMBED_NUM_SLOT_SHIFT  24
 156 #define DMA_CH_RX_EMBED_NUM_SLOT_MASK   (7 << DMA_CH_RX_EMBED_NUM_SLOT_SHIFT)
 157 #define DMA_CH_RX_EMBED_SOP_SLOT_SHIFT  16
 158 #define DMA_CH_RX_EMBED_SOP_SLOT_MASK   (7 << DMA_CH_RX_EMBED_SOP_SLOT_SHIFT)
 159 #define DMA_CH_RX_EMBED_FDQ_QMGR_SHIFT  12
 160 #define DMA_CH_RX_EMBED_FDQ_QMGR_MASK   (3 << DMA_CH_RX_EMBED_FDQ_QMGR_SHIFT)
 161 #define DMA_CH_RX_EMBED_FDQ_QNUM_SHIFT  0
 162 #define DMA_CH_RX_EMBED_FDQ_QNUM_MASK   (0xfff << \
 163                                          DMA_CH_RX_EMBED_FDQ_QNUM_SHIFT)
 164
 165 /* Rx Channel N Monolithic Packet Configuration Register bits */
 166 #define DMA_CH_RX_MONO_SOP_OFFSET_SHIFT 16
 167 #define DMA_CH_RX_MONO_SOP_OFFSET_MASK  (0xff << \
 168                                          DMA_CH_RX_MONO_SOP_OFFSET_SHIFT)
 169 #define DMA_CH_RX_MONO_FDQ_QMGR_SHIFT   12
 170 #define DMA_CH_RX_MONO_FDQ_QMGR_MASK    (3 << DMA_CH_RX_MONO_FDQ_QMGR_SHIFT)
 171 #define DMA_CH_RX_MONO_FDQ_QNUM_SHIFT   0
 172 #define DMA_CH_RX_MONO_FDQ_QNUM_MASK    (0xfff << DMA_CH_RX_MONO_FDQ_QNUM_SHIFT)
 173
 174 /*
 175  * DMA Scheduler - Control Region
 176  */
 177 #define DMA_SCHED_CTRL_REG              0x00
 178
 179 /* DMA Scheduler Control Register bits */
 180 #define DMA_SCHED_ENABLE_SHIFT          31
 181 #define DMA_SCHED_ENABLE_MASK           (1 << DMA_SCHED_ENABLE_SHIFT)
 182 #define DMA_SCHED_LAST_ENTRY_SHIFT      0
 183 #define DMA_SCHED_LAST_ENTRY_MASK       (0xff << DMA_SCHED_LAST_ENTRY_SHIFT)
 184
 185 /*
 186  * DMA Scheduler - Table Region
 187  */
 188 #define DMA_SCHED_TABLE_WORD_REG(n)     ((n) << 2)
 189
 190 /*
 191  * CPPI 4.1 Host Packet Descriptor
 192  */
 193 struct cppi41_host_pkt_desc {
 194         u32 desc_info;          /* Descriptor type, protocol specific word */
 195                                 /* count, packet length */
 196         u32 tag_info;           /* Source tag (31:16), destination tag (15:0) */
 197         u32 pkt_info;           /* Packet error state, type, protocol flags, */
 198                                 /* return info, descriptor location */
 199         u32 buf_len;            /* Number of valid data bytes in the buffer */
 200         u32 buf_ptr;            /* Pointer to the buffer associated with */
 201                                 /* this descriptor */
 202         u32 next_desc_ptr;      /* Pointer to the next buffer descriptor */
 203         u32 orig_buf_len;       /* Original buffer length */
 204         u32 orig_buf_ptr;       /* Original buffer pointer */
 205         u32 stk_comms_info[2];  /* Network stack private communications info */
 206 };
 207
 208 /*
 209  * CPPI 4.1 Host Buffer Descriptor
 210  */
 211 struct cppi41_host_buf_desc {
 212         u32 reserved[2];
 213         u32 buf_recl_info;      /* Return info, descriptor location */
 214         u32 buf_len;            /* Number of valid data bytes in the buffer */
 215         u32 buf_ptr;            /* Pointer to the buffer associated with */
 216                                 /* this descriptor */
 217         u32 next_desc_ptr;      /* Pointer to the next buffer descriptor */
 218         u32 orig_buf_len;       /* Original buffer length */
 219         u32 orig_buf_ptr;       /* Original buffer pointer */
 220 };
 221
 222 #define CPPI41_DESC_TYPE_SHIFT          27
 223 #define CPPI41_DESC_TYPE_MASK           (0x1f << CPPI41_DESC_TYPE_SHIFT)
 224 #define CPPI41_DESC_TYPE_HOST           16
 225 #define CPPI41_DESC_TYPE_MONOLITHIC     18
 226 #define CPPI41_DESC_TYPE_TEARDOWN       19
 227 #define CPPI41_PROT_VALID_WORD_CNT_SHIFT 22
 228 #define CPPI41_PROT_VALID_WORD_CNT_MASK (0x1f << CPPI41_PROT_WORD_CNT_SHIFT)
 229 #define CPPI41_PKT_LEN_SHIFT            0
 230 #define CPPI41_PKT_LEN_MASK             (0x1fffff << CPPI41_PKT_LEN_SHIFT)
 231
 232 #define CPPI41_PKT_ERROR_SHIFT          31
 233 #define CPPI41_PKT_ERROR_MASK           (1 << CPPI41_PKT_ERROR_SHIFT)
 234 #define CPPI41_PKT_TYPE_SHIFT           26
 235 #define CPPI41_PKT_TYPE_MASK            (0x1f << CPPI41_PKT_TYPE_SHIFT)
 236 #define CPPI41_PKT_TYPE_ATM_AAL5        0
 237 #define CPPI41_PKT_TYPE_ATM_NULL_AAL    1
 238 #define CPPI41_PKT_TYPE_ATM_OAM         2
 239 #define CPPI41_PKT_TYPE_ATM_TRANSPARENT 3
 240 #define CPPI41_PKT_TYPE_EFM             4
 241 #define CPPI41_PKT_TYPE_USB             5
 242 #define CPPI41_PKT_TYPE_GENERIC         6
 243 #define CPPI41_PKT_TYPE_ETHERNET        7
 244 #define CPPI41_RETURN_POLICY_SHIFT      15
 245 #define CPPI41_RETURN_POLICY_MASK       (1 << CPPI41_RETURN_POLICY_SHIFT)
 246 #define CPPI41_RETURN_LINKED            0
 247 #define CPPI41_RETURN_UNLINKED          1
 248 #define CPPI41_ONCHIP_SHIFT             14
 249 #define CPPI41_ONCHIP_MASK              (1 << CPPI41_ONCHIP_SHIFT)
 250 #define CPPI41_RETURN_QMGR_SHIFT        12
 251 #define CPPI41_RETURN_QMGR_MASK         (3 << CPPI41_RETURN_QMGR_SHIFT)
 252 #define CPPI41_RETURN_QNUM_SHIFT        0
 253 #define CPPI41_RETURN_QNUM_MASK         (0xfff << CPPI41_RETURN_QNUM_SHIFT)
 254
 255 #define CPPI41_SRC_TAG_PORT_NUM_SHIFT   27
 256 #define CPPI41_SRC_TAG_PORT_NUM_MASK    (0x1f << CPPI41_SRC_TAG_PORT_NUM_SHIFT)
 257 #define CPPI41_SRC_TAG_CH_NUM_SHIFT     21
 258 #define CPPI41_SRC_TAG_CH_NUM_MASK      (0x3f << CPPI41_SRC_TAG_CH_NUM_SHIFT)
 259 #define CPPI41_SRC_TAG_SUB_CH_NUM_SHIFT 16
 260 #define CPPI41_SRC_TAG_SUB_CH_NUM_MASK  (0x1f << \
 261                                         CPPI41_SRC_TAG_SUB_CH_NUM_SHIFT)
 262 #define CPPI41_DEST_TAG_SHIFT           0
 263 #define CPPI41_DEST_TAG_MASK            (0xffff << CPPI41_DEST_TAG_SHIFT)
 264
 265 /*
 266  * CPPI 4.1 Teardown Descriptor
 267  */
 268 struct cppi41_teardown_desc {
 269         u32 teardown_info;      /* Teardown information */
 270         u32 reserved[7];        /* 28 byte padding */
 271 };
 272
 273 #define CPPI41_TEARDOWN_TX_RX_SHIFT     16
 274 #define CPPI41_TEARDOWN_TX_RX_MASK      (1 << CPPI41_TEARDOWN_TX_RX_SHIFT)
 275 #define CPPI41_TEARDOWN_DMA_NUM_SHIFT   10
 276 #define CPPI41_TEARDOWN_DMA_NUM_MASK    (0x3f << CPPI41_TEARDOWN_DMA_NUM_SHIFT)
 277 #define CPPI41_TEARDOWN_CHAN_NUM_SHIFT  0
 278 #define CPPI41_TEARDOWN_CHAN_NUM_MASK   (0x3f << CPPI41_TEARDOWN_CHAN_NUM_SHIFT)
 279
 280 #define CPPI41_MAX_MEM_RGN              16
 281
 282 /* CPPI 4.1 configuration for AM3517 */
 283 #define CPPI41_NUM_QUEUE_MGR            1       /* 4  max */
 284 #define CPPI41_NUM_DMA_BLOCK            1       /* 64 max */
 285 #define cppi41_num_queue_mgr    CPPI41_NUM_QUEUE_MGR
 286 #define cppi41_num_dma_block    CPPI41_NUM_DMA_BLOCK
 287
 288 /**
 289  * struct cppi41_queue - Queue Tuple
 290  *
 291  * The basic queue tuple in CPPI 4.1 used across all data structures
 292  * where a definition of a queue is required.
 293  */
 294 struct cppi41_queue {
 295         u8  q_mgr;              /* The queue manager number */
 296         u16 q_num;              /* The queue number */
 297 };
 298
 299 /**
 300  * struct cppi41_buf_pool - Buffer Pool Tuple
 301  *
 302  * The basic buffer pool tuple in CPPI 4.1 used across all data structures
 303  * where a definition of a buffer pool is required.
 304  */
 305 struct cppi41_buf_pool {
 306         u8  b_mgr;              /* The buffer manager number */
 307         u16 b_pool;             /* The buffer pool number */
 308 };
 309
 310 /**
 311  * struct cppi41_queue_mgr - Queue Manager information
 312  *
 313  * Contains the information about the queue manager which should be copied from
 314  * the hardware spec as is.
 315  */
 316 struct cppi41_queue_mgr {
 317         void __iomem *q_mgr_rgn_base; /* Base address of the Control region. */
 318         void __iomem *desc_mem_rgn_base; /* Base address of the descriptor */
 319                                 /* memory region. */
 320         void __iomem *q_mgmt_rgn_base; /* Base address of the queues region. */
 321         void __iomem *q_stat_rgn_base; /* Base address of the queue status */
 322                                 /* region. */
 323         u16 num_queue;          /* Number of the queues supported. */
 324         u8  queue_types;        /* Bitmask of the supported queue types. */
 325         u16 base_fdq_num;       /* The base free descriptor queue number. */
 326                                 /* If present, there's always 16 such queues. */
 327         u16 base_fdbq_num;      /* The base free descriptor/buffer queue */
 328                                 /* number.  If present, there's always 16 */
 329                                 /* such queues. */
 330         const u32 *assigned;    /* Pointer to the bitmask of the pre-assigned */
 331                                 /* queues. */
 332 };
 333
 334 /* Queue type flags */
 335 #define CPPI41_FREE_DESC_QUEUE          0x01
 336 #define CPPI41_FREE_DESC_BUF_QUEUE      0x02
 337 #define CPPI41_UNASSIGNED_QUEUE         0x04
 338
 339 /**
 340  * struct cppi41_embed_pkt_cfg - Rx Channel Embedded packet configuration
 341  *
 342  * An instance of this structure forms part of the Rx channel information
 343  * structure.
 344  */
 345 struct cppi41_embed_pkt_cfg {
 346         struct cppi41_queue fd_queue; /* Free Descriptor queue.*/
 347         u8 num_buf_slot;        /* Number of buffer slots in the descriptor */
 348         u8 sop_slot_num;        /* SOP buffer slot number. */
 349         struct cppi41_buf_pool free_buf_pool[4]; /* Free Buffer pool. Element */
 350                                 /* 0 used for the 1st Rx buffer, etc. */
 351 };
 352
 353 /**
 354  * struct cppi41_host_pkt_cfg - Rx Channel Host Packet Configuration
 355  *
 356  * An instance of this structure forms part of the Rx channel information
 357  * structure.
 358  */
 359 struct cppi41_host_pkt_cfg {
 360         struct cppi41_queue fdb_queue[4]; /* Free Desc/Buffer queue. Element */
 361                                 /* 0 used for 1st Rx buffer, etc. */
 362 };
 363
 364 /**
 365  * struct cppi41_mono_pkt_cfg - Rx Channel Monolithic Packet Configuration
 366  *
 367  * An instance of this structure forms part of the Rx channel information
 368  * structure.
 369  */
 370 struct cppi41_mono_pkt_cfg {
 371         struct cppi41_queue fd_queue; /* Free descriptor queue */
 372         u8 sop_offset;          /* Number of bytes to skip before writing */
 373                                 /* payload */
 374 };
 375
 376 enum cppi41_rx_desc_type {
 377         cppi41_rx_embed_desc,
 378         cppi41_rx_host_desc,
 379         cppi41_rx_mono_desc,
 380 };
 381
 382 /**
 383  * struct cppi41_rx_ch_cfg - Rx Channel Configuration
 384  *
 385  * Must be allocated and filled by the caller of cppi41_rx_ch_configure().
 386  *
 387  * The same channel can be configured to receive different descripor type
 388  * packets (not simaltaneously). When the Rx packets on a port need to be sent
 389  * to the SR, the channels default descriptor type is set to Embedded and the
 390  * Rx completion queue is set to the queue which CPU polls for input packets.
 391  * When in SR bypass mode, the same channel's default descriptor type will be
 392  * set to Host and the Rx completion queue set to one of the queues which host
 393  * can get interrupted on (via the Queuing proxy/accumulator). In this example,
 394  * the embedded mode configuration fetches free descriptor from the Free
 395  * descriptor queue (as defined by struct cppi41_embed_pkt_cfg) and host
 396  * mode configuration fetches free descriptors/buffers from the free descriptor/
 397  * buffer queue (as defined by struct cppi41_host_pkt_cfg).
 398  *
 399  * NOTE: There seems to be no separate configuration for teardown completion
 400  * descriptor. The assumption is rxQueue tuple is used for this purpose as well.
 401  */
 402 struct cppi41_rx_ch_cfg {
 403         enum cppi41_rx_desc_type default_desc_type; /* Describes which queue */
 404                                 /* configuration is used for the free */
 405                                 /* descriptors and/or buffers */
 406         u8 sop_offset;          /* Number of bytes to skip in SOP buffer */
 407                                 /* before writing payload */
 408         u8 retry_starved;       /* 0 = Drop packet on descriptor/buffer */
 409                                 /* starvartion, 1 = DMA retries FIFO block */
 410                                 /* transfer at a later time */
 411         struct cppi41_queue rx_queue; /* Rx complete packets queue */
 412         union {
 413                 struct cppi41_host_pkt_cfg host_pkt; /* Host packet */
 414                                 /* configuration. This defines where channel */
 415                                 /* picks free descriptors from. */
 416                 struct cppi41_embed_pkt_cfg embed_pkt; /* Embedded packet */
 417                                 /* configuration. This defines where channel */
 418                                 /* picks free descriptors/buffers from. */
 419                                 /* from. */
 420                 struct cppi41_mono_pkt_cfg mono_pkt; /* Monolithic packet */
 421                                 /* configuration. This defines where channel */
 422                                 /* picks free descriptors from. */
 423         } cfg;                  /* Union of packet configuration structures */
 424                                 /* to be filled in depending on the */
 425                                 /* defDescType field. */
 426 };
 427
 428 /**
 429  * struct cppi41_tx_ch - Tx channel information
 430  *
 431  * NOTE: The queues that feed into the Tx channel are fixed at SoC design time.
 432  */
 433 struct cppi41_tx_ch {
 434         u8 port_num;            /* Port number. */
 435         u8 ch_num;              /* Channel number within port. */
 436         u8 sub_ch_num;          /* Sub-channel number within channel. */
 437         u8 num_tx_queue;        /* Number of queues from which the channel */
 438                                 /* can feed. */
 439         struct cppi41_queue tx_queue[4]; /* List of queues from which the */
 440                                 /* channel can feed. */
 441 };
 442
 443 /**
 444  * struct cppi41_dma_block - CPPI 4.1 DMA configuration
 445  *
 446  * Configuration information for CPPI DMA functionality. Includes the Global
 447  * configuration, Channel configuration, and the Scheduler configuration.
 448  */
 449 struct cppi41_dma_block {
 450         void __iomem *global_ctrl_base; /* Base address of the Global Control */
 451                                 /* registers. */
 452         void __iomem *ch_ctrl_stat_base; /* Base address of the Channel */
 453                                 /* Control/Status registers. */
 454         void __iomem *sched_ctrl_base; /* Base address of the Scheduler */
 455                                 /* Control register. */
 456         void __iomem *sched_table_base; /* Base address of the Scheduler */
 457                                 /* Table registers. */
 458         u8 num_tx_ch;           /* Number of the Tx channels. */
 459         u8 num_rx_ch;           /* Number of the Rx channels. */
 460         const struct cppi41_tx_ch *tx_ch_info;
 461 };
 462
 463 extern struct cppi41_queue_mgr cppi41_queue_mgr[];
 464 extern struct cppi41_dma_block cppi41_dma_block[];
 465
 466 /**
 467  * struct cppi41_dma_ch_obj - CPPI 4.1 DMA Channel object
 468  */
 469 struct cppi41_dma_ch_obj {
 470         void __iomem *base_addr; /* The address of the channel global */
 471                                 /* configuration register */
 472         u32 global_cfg;         /* Tx/Rx global configuration backed-up value */
 473 };
 474
 475 /**
 476  * struct cppi41_queue_obj - CPPI 4.1 queue object
 477  */
 478 struct cppi41_queue_obj {
 479         void __iomem *base_addr; /* The base address of the queue management */
 480                                 /* registers */
 481 };
 482
 483 /**
 484  * cppi41_queue_mgr_init - CPPI 4.1 queue manager initialization.
 485  * @q_mgr:      the queue manager to initialize
 486  * @rgn0_base:  linking RAM region 0 physical address
 487  * @rgn0_size:  linking RAM region 0 size in 32-bit words (0 to 0x3fff)
 488  *
 489  * Returns 0 on success, error otherwise.
 490  */
 491 int cppi41_queue_mgr_init(u8 q_mgr, dma_addr_t rgn0_base, u16 rgn0_size);
 492
 493 /*
 494  * CPPI 4.1 Queue Manager Memory Region Allocation and De-allocation APIs.
 495  */
 496
 497 /**
 498  * cppi41_mem_rgn_alloc - CPPI 4.1 queue manager memory region allocation.
 499  * @q_mgr:      the queue manager whose memory region to allocate
 500  * @rgn_addr:   physical address of the memory region
 501  * @size_order: descriptor size as a power of two (between 5 and 13)
 502  * @num_order:  number of descriptors as a power of two (between 5 and 12)
 503  * @mem_rgn:    pointer to the index of the memory region allocated
 504  *
 505  * This function allocates a memory region within the queue manager
 506  * consisiting of the descriptors of paricular size and number.
 507  *
 508  * Returns 0 on success, error otherwise.
 509  */
 510 int cppi41_mem_rgn_alloc(u8 q_mgr, dma_addr_t rgn_addr, u8 size_order,
 511                          u8 num_order, u8 *mem_rgn);
 512
 513 /**
 514  * cppi41_mem_rgn_free - CPPI 4.1 queue manager memory region de-allocation.
 515  * @q_mgr:      the queue manager whose memory region was allocated
 516  * @mem_rgn:    index of the memory region
 517  *
 518  * This function frees the memory region allocated by cppi41_mem_rgn_alloc().
 519  *
 520  * Returns 0 on success, -EINVAL otherwise.
 521  */
 522 int cppi41_mem_rgn_free(u8 q_mgr, u8 mem_rgn);
 523
 524 /**
 525  * cppi41_dma_block_init - CPPI 4.1 DMA block initialization.
 526  * @dma_num:    number of the DMA block
 527  * @q_mgr:      the queue manager in which to allocate the free teardown
 528  *              descriptor queue
 529  * @num_order:  number of teardown descriptors as a power of two (at least 5)
 530  * @sched_tbl:  the DMA scheduler table
 531  * @tbl_size:   number of entries in the DMA scheduler table
 532  *
 533  * This function frees the memory region allocated by cppi41_mem_rgn_alloc().
 534  *
 535  * Returns 0 on success, error otherwise.
 536  */
 537 int cppi41_dma_block_init(u8 dma_num, u8 q_mgr, u8 num_order,
 538                                  u32 *sched_tbl, u8 tbl_size);
 539
 540 /*
 541  * CPPI 4.1 DMA Channel Management APIs
 542  */
 543
 544 /**
 545  * cppi41_tx_ch_init - initialize CPPI 4.1 transmit channel object
 546  * @tx_ch_obj:  pointer to Tx channel object
 547  * @dma_num:    DMA block to which this channel belongs
 548  * @ch_num:     DMA channel number
 549  *
 550  * Returns 0 if valid Tx channel, -EINVAL otherwise.
 551  */
 552 int cppi41_tx_ch_init(struct cppi41_dma_ch_obj *tx_ch_obj,
 553                       u8 dma_num, u8 ch_num);
 554
 555 /**
 556  * cppi41_rx_ch_init - initialize CPPI 4.1 receive channel object
 557  * @rx_ch_obj:  pointer to Rx channel object
 558  * @dma_num:    DMA block to which this channel belongs
 559  * @ch_num:     DMA channel number
 560  *
 561  * Returns 0 if valid Rx channel, -EINVAL otherwise.
 562  */
 563 int cppi41_rx_ch_init(struct cppi41_dma_ch_obj *rx_ch_obj,
 564                       u8 dma_num, u8 ch_num);
 565
 566 /**
 567  * cppi41_dma_ch_default_queue - set CPPI 4.1 channel default completion queue
 568  * @dma_ch_obj: pointer to DMA channel object
 569  * @q_mgr:      default queue manager
 570  * @q_num:      default queue number
 571  *
 572  * This function configures the specified channel.  The caller is required to
 573  * provide the default queue onto which the teardown descriptors will be queued.
 574  */
 575 void cppi41_dma_ch_default_queue(struct cppi41_dma_ch_obj *dma_ch_obj,
 576                                  u8 q_mgr, u16 q_num);
 577
 578 /**
 579  * cppi41_rx_ch_configure - configure CPPI 4.1 receive channel
 580  * @rx_ch_obj:  pointer to Rx channel object
 581  * @cfg:        pointer to Rx channel configuration
 582  *
 583  * This function configures and opens the specified Rx channel.  The caller
 584  * is required to provide channel configuration information by initializing
 585  * a struct cppi41_rx_ch_cfg.
 586  */
 587 void cppi41_rx_ch_configure(struct cppi41_dma_ch_obj *rx_ch_obj,
 588                             struct cppi41_rx_ch_cfg  *cfg);
 589
 590 /**
 591  * cppi41_dma_ch_enable - enable CPPI 4.1 Tx/Rx DMA channel
 592  * @dma_ch_obj: pointer to DMA channel object
 593  *
 594  * This function enables  a specified Tx channel.  The caller is required to
 595  * provide a reference to a channel object initialized by an earlier call of
 596  * the cppi41_dma_ch_init() function.  After the successful completion of this
 597  * function, the Tx DMA channel will be active and ready for data transmission.
 598  */
 599 void cppi41_dma_ch_enable(struct cppi41_dma_ch_obj *dma_ch_obj);
 600
 601 /**
 602  * cppi41_dma_ch_disable - disable CPPI 4.1 Tx/Rx DMA channel
 603  * @dma_ch_obj: pointer to DMA channel object
 604  *
 605  * This function disables a specific Tx channel.  The caller is required to
 606  * provide a reference to a channel object initialized by an earlier call of
 607  * the cppi41_dma_ch_init() function.  After the successful completion of this
 608  * function, the Tx DMA channel will be deactived.
 609  */
 610 void cppi41_dma_ch_disable(struct cppi41_dma_ch_obj *dma_ch_obj);
 611
 612 /**
 613  * cppi41_dma_ch_teardown - tear down CPPI 4.1 transmit channel
 614  * @dma_ch_obj: pointer DMA channel object
 615  *
 616  * This function triggers the teardown of the given DMA channel.
 617  *
 618  * ATTENTION: Channel disable should not be called before the teardown is
 619  * completed as a disable will stop the DMA scheduling on the channel resulting
 620  * in the teardown complete event not being registered at all.
 621  *
 622  * NOTE: A successful channel teardown event is reported via queueing of a
 623  * teardown descriptor.
 624  *
 625  * This function just sets up for the teardown of the channel and returns. The
 626  * caller must detect the channel teardown event to assume that the channel is
 627  * disabled.
 628  *
 629  * See cppi41_get_teardown_info() for the teardown completion processing.
 630  */
 631 void cppi41_dma_ch_teardown(struct cppi41_dma_ch_obj *dma_ch_obj);
 632
 633 /*
 634  * CPPI 4.1 Queue Allocation and De-allocation APIs.
 635  */
 636
 637 /**
 638  * cppi41_queue_alloc - allocate CPPI 4.1 queue
 639  * @type:       queue type bitmask
 640  * @q_mgr:      queue manager
 641  * @q_num:      pointer to the queue number
 642  *
 643  * Returns 0 if queue allocated, error otherwise.
 644  */
 645 int cppi41_queue_alloc(u8 type, u8 q_mgr, u16 *q_num);
 646
 647 /**
 648  * cppi41_queue_free - de-allocate CPPI 4.1 queue
 649  * @q_mgr:      queue manager
 650  * @q_num:      queue number
 651  *
 652  * Returns 0 on success, -EINVAL otherwise.
 653  */
 654 int cppi41_queue_free(u8 q_mgr, u16 q_num);
 655
 656 /*
 657  *  CPPI 4.1 Queue Management APIs
 658  */
 659
 660 /**
 661  * cppi41_queue_init - initialize CPPI 4.1 queue object
 662  * @queue_obj:  pointer to the queue object
 663  * @q_mgr:      queue manager
 664  * @q_num:      queue number
 665  *
 666  * Returns 0 if valid queue, -EINVAL otherwise.
 667  */
 668 int cppi41_queue_init(struct cppi41_queue_obj *queue_obj, u8 q_mgr, u16 q_num);
 669
 670 /**
 671  * cppi41_queue_push - push to CPPI 4.1 queue
 672  * @queue_obj:  pointer to the queue object
 673  * @desc_addr:  descriptor physical address
 674  * @desc_size:  descriptor size
 675  * @pkt_size:   packet size
 676  *
 677  * This function is called to queue a descriptor onto a queue.
 678  * NOTE: pSize parameter is optional. Pass 0 in case not required.
 679  */
 680 void cppi41_queue_push(const struct cppi41_queue_obj *queue_obj, u32 desc_addr,
 681                        u32 desc_size, u32 pkt_size);
 682
 683 /**
 684  * cppi41_queue_pop - pop from CPPI 4.1 queue
 685  * @queue_obj:  pointer to the queue object
 686  *
 687  * This function is called to pop a single descriptor from the queue.
 688  *
 689  * Returns a packet descriptor's physical address.
 690  */
 691 unsigned long cppi41_queue_pop(const struct cppi41_queue_obj *queue_obj);
 692
 693 /*
 694  * CPPI 4.1 Miscellaneous APIs
 695  */
 696
 697 /**
 698  * cppi41_get_teardown_info - CPPI 4.1 teardown completion processing function
 699  *
 700  * @addr:       physical address of teardown descriptor
 701  * @info:       pointer to the teardown information word
 702  *
 703  * This function is called to complete the teardown processing on a channel
 704  * and provides teardown information from the teardown descriptor passed to it.
 705  * It also recycles the teardown descriptor back to the teardown descriptor
 706  * queue.
 707  *
 708  * Returns 0 if valid descriptor, -EINVAL otherwise.
 709  */
 710 int cppi41_get_teardown_info(unsigned long addr, u32 *info);
 711
 712 /**
 713  * cppi41_exit - delete the instance created via cppi41_init()
 714  */
 715 void cppi41_exit(void);
 716
 717 /**
 718  * cppi41_dma_sched_tbl_init
 719  */
 720 int cppi41_dma_sched_tbl_init(u8 dma_num, u8 q_mgr,
 721                                 u32 *sched_tbl, u8 tbl_size);
 722
 723 /**
 724  * cppi41_free_teardown_queue
 725  */
 726 void cppi41_free_teardown_queue(int dma_num);