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Full support for Ginger Console
[linux-ginger.git] / drivers / usb / musb / musb_core.c
blobd444327216ab38c468a6bc985e89a0bc1d467656
1 /*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 /*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82 /*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101
102 #ifdef CONFIG_ARM
103 #include <mach/hardware.h>
104 #include <mach/memory.h>
105 #include <asm/mach-types.h>
106 #endif
107
108 #include "musb_core.h"
109
110
111 #ifdef CONFIG_ARCH_DAVINCI
112 #include "davinci.h"
113 #endif
114
115
116 #ifdef CONFIG_PM
117 void __iomem *musb_base;
118 unsigned short musb_clock_on = 1;
119 #endif
120
121 unsigned musb_debug;
122 module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR);
123 MODULE_PARM_DESC(debug, "Debug message level. Default = 0");
124
125 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
126 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
127
128 #define MUSB_VERSION "6.0"
129
130 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
131
132 #define MUSB_DRIVER_NAME "musb_hdrc"
133 const char musb_driver_name[] = MUSB_DRIVER_NAME;
134
135 MODULE_DESCRIPTION(DRIVER_INFO);
136 MODULE_AUTHOR(DRIVER_AUTHOR);
137 MODULE_LICENSE("GPL");
138 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
139
140
141 /*-------------------------------------------------------------------------*/
142
143 static inline struct musb *dev_to_musb(struct device *dev)
144 {
145 #ifdef CONFIG_USB_MUSB_HDRC_HCD
146 /* usbcore insists dev->driver_data is a "struct hcd *" */
147 return hcd_to_musb(dev_get_drvdata(dev));
148 #else
149 return dev_get_drvdata(dev);
150 #endif
151 }
152
153 /*-------------------------------------------------------------------------*/
154
155 #if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN)
156
157 /*
158 * Load an endpoint's FIFO
159 */
160 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
161 {
162 void __iomem *fifo = hw_ep->fifo;
163
164 prefetch((u8 *)src);
165
166 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
167 'T', hw_ep->epnum, fifo, len, src);
168
169 /* we can't assume unaligned reads work */
170 if (likely((0x01 & (unsigned long) src) == 0)) {
171 u16 index = 0;
172
173 /* best case is 32bit-aligned source address */
174 if ((0x02 & (unsigned long) src) == 0) {
175 if (len >= 4) {
176 writesl(fifo, src + index, len >> 2);
177 index += len & ~0x03;
178 }
179 if (len & 0x02) {
180 musb_writew(fifo, 0, *(u16 *)&src[index]);
181 index += 2;
182 }
183 } else {
184 if (len >= 2) {
185 writesw(fifo, src + index, len >> 1);
186 index += len & ~0x01;
187 }
188 }
189 if (len & 0x01)
190 musb_writeb(fifo, 0, src[index]);
191 } else {
192 /* byte aligned */
193 writesb(fifo, src, len);
194 }
195 }
196
197 static inline void musb_fifo_read_unaligned(void __iomem *fifo,
198 void __iomem *buf, u16 len)
199 {
200 u32 val;
201 int i;
202
203 if (len > 4) {
204 for (i = 0; i < (len >> 2); i++) {
205 val = musb_readl(fifo, 0);
206 memcpy(buf, &val, 4);
207 buf += 4;
208 }
209 len %= 4;
210 }
211 if (len > 0) {
212 /* Read the rest 1 - 3 bytes from FIFO */
213 val = musb_readl(fifo, 0);
214 memcpy(buf, &val, len);
215 }
216 }
217
218 /*
219 * Unload an endpoint's FIFO
220 */
221 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
222 {
223 void __iomem *fifo = hw_ep->fifo;
224
225 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
226 'R', hw_ep->epnum, fifo, len, dst);
227
228 if (cpu_is_omap3517()) {
229 /* Bytewise or wordwise data read from FIFO is corrupted
230 * if AM3517EVM is configured as gadget */
231 musb_fifo_read_unaligned(fifo, dst, len);
232 return;
233 } else if (likely((0x01 & (unsigned long) dst) == 0)) {
234 /* we can't assume unaligned writes work */
235 u16 index = 0;
236
237 /* best case is 32bit-aligned destination address */
238 if ((0x02 & (unsigned long) dst) == 0) {
239 if (len >= 4) {
240 readsl(fifo, dst, len >> 2);
241 index = len & ~0x03;
242 }
243 if (len & 0x02) {
244 *(u16 *)&dst[index] = musb_readw(fifo, 0);
245 index += 2;
246 }
247 } else {
248 if (len >= 2) {
249 readsw(fifo, dst, len >> 1);
250 index = len & ~0x01;
251 }
252 }
253 if (len & 0x01)
254 dst[index] = musb_readb(fifo, 0);
255 } else {
256 /* byte aligned */
257 readsb(fifo, dst, len);
258 }
259 }
260
261 #endif /* normal PIO */
262
263
264 /*-------------------------------------------------------------------------*/
265
266 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
267 static const u8 musb_test_packet[53] = {
268 /* implicit SYNC then DATA0 to start */
269
270 /* JKJKJKJK x9 */
271 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
272 /* JJKKJJKK x8 */
273 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
274 /* JJJJKKKK x8 */
275 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
276 /* JJJJJJJKKKKKKK x8 */
277 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
278 /* JJJJJJJK x8 */
279 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
280 /* JKKKKKKK x10, JK */
281 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
282
283 /* implicit CRC16 then EOP to end */
284 };
285
286 void musb_load_testpacket(struct musb *musb)
287 {
288 void __iomem *regs = musb->endpoints[0].regs;
289
290 musb_ep_select(musb->mregs, 0);
291 musb_write_fifo(musb->control_ep,
292 sizeof(musb_test_packet), musb_test_packet);
293 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
294 }
295
296 /*-------------------------------------------------------------------------*/
297
298 const char *otg_state_string(struct musb *musb)
299 {
300 switch (musb->xceiv->state) {
301 case OTG_STATE_A_IDLE: return "a_idle";
302 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
303 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
304 case OTG_STATE_A_HOST: return "a_host";
305 case OTG_STATE_A_SUSPEND: return "a_suspend";
306 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
307 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
308 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
309 case OTG_STATE_B_IDLE: return "b_idle";
310 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
311 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
312 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
313 case OTG_STATE_B_HOST: return "b_host";
314 default: return "UNDEFINED";
315 }
316 }
317
318 #ifdef CONFIG_USB_MUSB_OTG
319
320 /*
321 * See also USB_OTG_1-3.pdf 6.6.5 Timers
322 * REVISIT: Are the other timers done in the hardware?
323 */
324 #define TB_ASE0_BRST 100 /* Min 3.125 ms */
325
326 /*
327 * Handles OTG hnp timeouts, such as b_ase0_brst
328 */
329 void musb_otg_timer_func(unsigned long data)
330 {
331 struct musb *musb = (struct musb *)data;
332 unsigned long flags;
333
334 spin_lock_irqsave(&musb->lock, flags);
335 switch (musb->xceiv->state) {
336 case OTG_STATE_B_WAIT_ACON:
337 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
338 musb_g_disconnect(musb);
339 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
340 musb->is_active = 0;
341 break;
342 case OTG_STATE_A_WAIT_BCON:
343 DBG(1, "HNP: a_wait_bcon timeout; back to a_host\n");
344 musb_hnp_stop(musb);
345 break;
346 default:
347 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
348 }
349 musb->ignore_disconnect = 0;
350 spin_unlock_irqrestore(&musb->lock, flags);
351 }
352
353 static DEFINE_TIMER(musb_otg_timer, musb_otg_timer_func, 0, 0);
354
355 /*
356 * Stops the B-device HNP state. Caller must take care of locking.
357 */
358 void musb_hnp_stop(struct musb *musb)
359 {
360 struct usb_hcd *hcd = musb_to_hcd(musb);
361 void __iomem *mbase = musb->mregs;
362 u8 reg;
363
364 switch (musb->xceiv->state) {
365 case OTG_STATE_A_PERIPHERAL:
366 case OTG_STATE_A_WAIT_VFALL:
367 case OTG_STATE_A_WAIT_BCON:
368 DBG(1, "HNP: Switching back to A-host\n");
369 musb_g_disconnect(musb);
370 musb->xceiv->state = OTG_STATE_A_IDLE;
371 MUSB_HST_MODE(musb);
372 musb->is_active = 0;
373 break;
374 case OTG_STATE_B_HOST:
375 DBG(1, "HNP: Disabling HR\n");
376 hcd->self.is_b_host = 0;
377 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
378 MUSB_DEV_MODE(musb);
379 reg = musb_readb(mbase, MUSB_POWER);
380 reg |= MUSB_POWER_SUSPENDM;
381 musb_writeb(mbase, MUSB_POWER, reg);
382 /* REVISIT: Start SESSION_REQUEST here? */
383 break;
384 default:
385 DBG(1, "HNP: Stopping in unknown state %s\n",
386 otg_state_string(musb));
387 }
388
389 /*
390 * When returning to A state after HNP, avoid hub_port_rebounce(),
391 * which cause occasional OPT A "Did not receive reset after connect"
392 * errors.
393 */
394 musb->port1_status &=
395 ~(1 << USB_PORT_FEAT_C_CONNECTION);
396 }
397
398 #endif
399
400 /*
401 * Interrupt Service Routine to record USB "global" interrupts.
402 * Since these do not happen often and signify things of
403 * paramount importance, it seems OK to check them individually;
404 * the order of the tests is specified in the manual
405 *
406 * @param musb instance pointer
407 * @param int_usb register contents
408 * @param devctl
409 * @param power
410 */
411
412 #define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \
413 | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \
414 | MUSB_INTR_RESET)
415
416 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
417 u8 devctl, u8 power)
418 {
419 irqreturn_t handled = IRQ_NONE;
420 void __iomem *mbase = musb->mregs;
421
422 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
423 int_usb);
424
425 /* in host mode, the peripheral may issue remote wakeup.
426 * in peripheral mode, the host may resume the link.
427 * spurious RESUME irqs happen too, paired with SUSPEND.
428 */
429 if (int_usb & MUSB_INTR_RESUME) {
430 handled = IRQ_HANDLED;
431 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
432
433 if (devctl & MUSB_DEVCTL_HM) {
434 #ifdef CONFIG_USB_MUSB_HDRC_HCD
435 switch (musb->xceiv->state) {
436 case OTG_STATE_A_SUSPEND:
437 /* remote wakeup? later, GetPortStatus
438 * will stop RESUME signaling
439 */
440
441 if (power & MUSB_POWER_SUSPENDM) {
442 /* spurious */
443 musb->int_usb &= ~MUSB_INTR_SUSPEND;
444 DBG(2, "Spurious SUSPENDM\n");
445 break;
446 }
447
448 power &= ~MUSB_POWER_SUSPENDM;
449 musb_writeb(mbase, MUSB_POWER,
450 power | MUSB_POWER_RESUME);
451
452 musb->port1_status |=
453 (USB_PORT_STAT_C_SUSPEND << 16)
454 | MUSB_PORT_STAT_RESUME;
455 musb->rh_timer = jiffies
456 + msecs_to_jiffies(20);
457
458 musb->xceiv->state = OTG_STATE_A_HOST;
459 musb->is_active = 1;
460 usb_hcd_resume_root_hub(musb_to_hcd(musb));
461 break;
462 case OTG_STATE_B_WAIT_ACON:
463 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
464 musb->is_active = 1;
465 MUSB_DEV_MODE(musb);
466 break;
467 default:
468 WARNING("bogus %s RESUME (%s)\n",
469 "host",
470 otg_state_string(musb));
471 }
472 #endif
473 } else {
474 switch (musb->xceiv->state) {
475 #ifdef CONFIG_USB_MUSB_HDRC_HCD
476 case OTG_STATE_A_SUSPEND:
477 /* possibly DISCONNECT is upcoming */
478 musb->xceiv->state = OTG_STATE_A_HOST;
479 usb_hcd_resume_root_hub(musb_to_hcd(musb));
480 break;
481 #endif
482 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
483 case OTG_STATE_B_WAIT_ACON:
484 case OTG_STATE_B_PERIPHERAL:
485 /* disconnect while suspended? we may
486 * not get a disconnect irq...
487 */
488 if ((devctl & MUSB_DEVCTL_VBUS)
489 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
490 ) {
491 musb->int_usb |= MUSB_INTR_DISCONNECT;
492 musb->int_usb &= ~MUSB_INTR_SUSPEND;
493 break;
494 }
495 musb_g_resume(musb);
496 break;
497 case OTG_STATE_B_IDLE:
498 musb->int_usb &= ~MUSB_INTR_SUSPEND;
499 break;
500 #endif
501 default:
502 WARNING("bogus %s RESUME (%s)\n",
503 "peripheral",
504 otg_state_string(musb));
505 }
506 }
507 }
508
509 #ifdef CONFIG_USB_MUSB_HDRC_HCD
510 /* see manual for the order of the tests */
511 if (int_usb & MUSB_INTR_SESSREQ) {
512 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
513
514 /* IRQ arrives from ID pin sense or (later, if VBUS power
515 * is removed) SRP. responses are time critical:
516 * - turn on VBUS (with silicon-specific mechanism)
517 * - go through A_WAIT_VRISE
518 * - ... to A_WAIT_BCON.
519 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
520 */
521 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
522 musb->ep0_stage = MUSB_EP0_START;
523 musb->xceiv->state = OTG_STATE_A_IDLE;
524 MUSB_HST_MODE(musb);
525 musb_set_vbus(musb, 1);
526
527 handled = IRQ_HANDLED;
528 }
529
530 if (int_usb & MUSB_INTR_VBUSERROR) {
531 int ignore = 0;
532
533 /* During connection as an A-Device, we may see a short
534 * current spikes causing voltage drop, because of cable
535 * and peripheral capacitance combined with vbus draw.
536 * (So: less common with truly self-powered devices, where
537 * vbus doesn't act like a power supply.)
538 *
539 * Such spikes are short; usually less than ~500 usec, max
540 * of ~2 msec. That is, they're not sustained overcurrent
541 * errors, though they're reported using VBUSERROR irqs.
542 *
543 * Workarounds: (a) hardware: use self powered devices.
544 * (b) software: ignore non-repeated VBUS errors.
545 *
546 * REVISIT: do delays from lots of DEBUG_KERNEL checks
547 * make trouble here, keeping VBUS < 4.4V ?
548 */
549 switch (musb->xceiv->state) {
550 case OTG_STATE_A_HOST:
551 /* recovery is dicey once we've gotten past the
552 * initial stages of enumeration, but if VBUS
553 * stayed ok at the other end of the link, and
554 * another reset is due (at least for high speed,
555 * to redo the chirp etc), it might work OK...
556 */
557 case OTG_STATE_A_WAIT_BCON:
558 case OTG_STATE_A_WAIT_VRISE:
559 if (musb->vbuserr_retry) {
560 musb->vbuserr_retry--;
561 ignore = 1;
562 devctl |= MUSB_DEVCTL_SESSION;
563 musb_writeb(mbase, MUSB_DEVCTL, devctl);
564 } else {
565 musb->port1_status |=
566 (1 << USB_PORT_FEAT_OVER_CURRENT)
567 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
568 }
569 break;
570 default:
571 break;
572 }
573
574 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
575 otg_state_string(musb),
576 devctl,
577 ({ char *s;
578 switch (devctl & MUSB_DEVCTL_VBUS) {
579 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
580 s = "<SessEnd"; break;
581 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
582 s = "<AValid"; break;
583 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
584 s = "<VBusValid"; break;
585 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
586 default:
587 s = "VALID"; break;
588 }; s; }),
589 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
590 musb->port1_status);
591
592 /* go through A_WAIT_VFALL then start a new session */
593 if (!ignore)
594 musb_set_vbus(musb, 0);
595 handled = IRQ_HANDLED;
596 }
597
598 if (int_usb & MUSB_INTR_CONNECT) {
599 struct usb_hcd *hcd = musb_to_hcd(musb);
600
601 handled = IRQ_HANDLED;
602 musb->is_active = 1;
603 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
604
605 musb->ep0_stage = MUSB_EP0_START;
606
607 #ifdef CONFIG_USB_MUSB_OTG
608 /* flush endpoints when transitioning from Device Mode */
609 if (is_peripheral_active(musb)) {
610 /* REVISIT HNP; just force disconnect */
611 }
612 musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
613 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
614 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
615 #endif
616 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
617 |USB_PORT_STAT_HIGH_SPEED
618 |USB_PORT_STAT_ENABLE
619 );
620 musb->port1_status |= USB_PORT_STAT_CONNECTION
621 |(USB_PORT_STAT_C_CONNECTION << 16);
622
623 /* high vs full speed is just a guess until after reset */
624 if (devctl & MUSB_DEVCTL_LSDEV)
625 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
626
627 if (hcd->status_urb)
628 usb_hcd_poll_rh_status(hcd);
629 else
630 usb_hcd_resume_root_hub(hcd);
631
632 MUSB_HST_MODE(musb);
633
634 /* indicate new connection to OTG machine */
635 switch (musb->xceiv->state) {
636 case OTG_STATE_B_PERIPHERAL:
637 if (int_usb & MUSB_INTR_SUSPEND) {
638 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
639 musb->xceiv->state = OTG_STATE_B_HOST;
640 hcd->self.is_b_host = 1;
641 int_usb &= ~MUSB_INTR_SUSPEND;
642 } else
643 DBG(1, "CONNECT as b_peripheral???\n");
644 break;
645 case OTG_STATE_B_WAIT_ACON:
646 DBG(1, "HNP: Waiting to switch to b_host state\n");
647 musb->xceiv->state = OTG_STATE_B_HOST;
648 hcd->self.is_b_host = 1;
649 break;
650 default:
651 if ((devctl & MUSB_DEVCTL_VBUS)
652 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
653 musb->xceiv->state = OTG_STATE_A_HOST;
654 hcd->self.is_b_host = 0;
655 }
656 break;
657 }
658 DBG(1, "CONNECT (%s) devctl %02x\n",
659 otg_state_string(musb), devctl);
660 }
661 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
662
663 /* mentor saves a bit: bus reset and babble share the same irq.
664 * only host sees babble; only peripheral sees bus reset.
665 */
666 if (int_usb & MUSB_INTR_RESET) {
667 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
668 /*
669 * Looks like non-HS BABBLE can be ignored, but
670 * HS BABBLE is an error condition. For HS the solution
671 * is to avoid babble in the first place and fix what
672 * caused BABBLE. When HS BABBLE happens we can only
673 * stop the session.
674 */
675 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
676 DBG(1, "BABBLE devctl: %02x\n", devctl);
677 else {
678 ERR("Stopping host session -- babble\n");
679 musb_writeb(mbase, MUSB_DEVCTL, 0);
680 }
681 } else if (is_peripheral_capable()) {
682 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
683 switch (musb->xceiv->state) {
684 #ifdef CONFIG_USB_OTG
685 case OTG_STATE_A_SUSPEND:
686 /* We need to ignore disconnect on suspend
687 * otherwise tusb 2.0 won't reconnect after a
688 * power cycle, which breaks otg compliance.
689 */
690 musb->ignore_disconnect = 1;
691 musb_g_reset(musb);
692 /* FALLTHROUGH */
693 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
694 DBG(1, "HNP: Setting timer as %s\n",
695 otg_state_string(musb));
696 musb_otg_timer.data = (unsigned long)musb;
697 mod_timer(&musb_otg_timer, jiffies
698 + msecs_to_jiffies(100));
699 break;
700 case OTG_STATE_A_PERIPHERAL:
701 musb_hnp_stop(musb);
702 break;
703 case OTG_STATE_B_WAIT_ACON:
704 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
705 otg_state_string(musb));
706 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
707 musb_g_reset(musb);
708 break;
709 #endif
710 case OTG_STATE_B_IDLE:
711 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
712 /* FALLTHROUGH */
713 case OTG_STATE_B_PERIPHERAL:
714 musb_g_reset(musb);
715 break;
716 default:
717 DBG(1, "Unhandled BUS RESET as %s\n",
718 otg_state_string(musb));
719 }
720 }
721
722 handled = IRQ_HANDLED;
723 }
724 schedule_work(&musb->irq_work);
725
726 return handled;
727 }
728
729 /*
730 * Interrupt Service Routine to record USB "global" interrupts.
731 * Since these do not happen often and signify things of
732 * paramount importance, it seems OK to check them individually;
733 * the order of the tests is specified in the manual
734 *
735 * @param musb instance pointer
736 * @param int_usb register contents
737 * @param devctl
738 * @param power
739 */
740 static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
741 u8 devctl, u8 power)
742 {
743 irqreturn_t handled = IRQ_NONE;
744
745 #if 0
746 /* REVISIT ... this would be for multiplexing periodic endpoints, or
747 * supporting transfer phasing to prevent exceeding ISO bandwidth
748 * limits of a given frame or microframe.
749 *
750 * It's not needed for peripheral side, which dedicates endpoints;
751 * though it _might_ use SOF irqs for other purposes.
752 *
753 * And it's not currently needed for host side, which also dedicates
754 * endpoints, relies on TX/RX interval registers, and isn't claimed
755 * to support ISO transfers yet.
756 */
757 if (int_usb & MUSB_INTR_SOF) {
758 void __iomem *mbase = musb->mregs;
759 struct musb_hw_ep *ep;
760 u8 epnum;
761 u16 frame;
762
763 DBG(6, "START_OF_FRAME\n");
764 handled = IRQ_HANDLED;
765
766 /* start any periodic Tx transfers waiting for current frame */
767 frame = musb_readw(mbase, MUSB_FRAME);
768 ep = musb->endpoints;
769 for (epnum = 1; (epnum < musb->nr_endpoints)
770 && (musb->epmask >= (1 << epnum));
771 epnum++, ep++) {
772 /*
773 * FIXME handle framecounter wraps (12 bits)
774 * eliminate duplicated StartUrb logic
775 */
776 if (ep->dwWaitFrame >= frame) {
777 ep->dwWaitFrame = 0;
778 pr_debug("SOF --> periodic TX%s on %d\n",
779 ep->tx_channel ? " DMA" : "",
780 epnum);
781 if (!ep->tx_channel)
782 musb_h_tx_start(musb, epnum);
783 else
784 cppi_hostdma_start(musb, epnum);
785 }
786 } /* end of for loop */
787 }
788 #endif
789
790 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
791 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
792 otg_state_string(musb),
793 MUSB_MODE(musb), devctl);
794 handled = IRQ_HANDLED;
795
796 switch (musb->xceiv->state) {
797 #ifdef CONFIG_USB_MUSB_HDRC_HCD
798 case OTG_STATE_A_HOST:
799 case OTG_STATE_A_SUSPEND:
800 usb_hcd_resume_root_hub(musb_to_hcd(musb));
801 musb_root_disconnect(musb);
802 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
803 musb_platform_try_idle(musb, jiffies
804 + msecs_to_jiffies(musb->a_wait_bcon));
805 break;
806 #endif /* HOST */
807 #ifdef CONFIG_USB_MUSB_OTG
808 case OTG_STATE_B_HOST:
809 musb_hnp_stop(musb);
810 break;
811 case OTG_STATE_A_PERIPHERAL:
812 musb_hnp_stop(musb);
813 musb_root_disconnect(musb);
814 /* FALLTHROUGH */
815 case OTG_STATE_B_WAIT_ACON:
816 /* FALLTHROUGH */
817 #endif /* OTG */
818 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
819 case OTG_STATE_B_PERIPHERAL:
820 case OTG_STATE_B_IDLE:
821 printk(KERN_INFO "musb %s gadget disconnected.\n",
822 musb->gadget_driver
823 ? musb->gadget_driver->driver.name
824 : "");
825 musb_g_disconnect(musb);
826 break;
827 #endif /* GADGET */
828 default:
829 WARNING("unhandled DISCONNECT transition (%s)\n",
830 otg_state_string(musb));
831 break;
832 }
833
834 schedule_work(&musb->irq_work);
835 }
836
837 if (int_usb & MUSB_INTR_SUSPEND) {
838 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
839 otg_state_string(musb), devctl, power);
840 handled = IRQ_HANDLED;
841
842 switch (musb->xceiv->state) {
843 #ifdef CONFIG_USB_MUSB_OTG
844 case OTG_STATE_A_PERIPHERAL:
845 /*
846 * We cannot stop HNP here, devctl BDEVICE might be
847 * still set.
848 */
849 break;
850 #endif
851 case OTG_STATE_B_PERIPHERAL:
852 musb_g_suspend(musb);
853 musb->is_active = is_otg_enabled(musb)
854 && musb->xceiv->gadget->b_hnp_enable;
855 if (musb->is_active) {
856 #ifdef CONFIG_USB_MUSB_OTG
857 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
858 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
859 musb_otg_timer.data = (unsigned long)musb;
860 mod_timer(&musb_otg_timer, jiffies
861 + msecs_to_jiffies(TB_ASE0_BRST));
862 #endif
863 }
864 break;
865 case OTG_STATE_A_WAIT_BCON:
866 if (musb->a_wait_bcon != 0)
867 musb_platform_try_idle(musb, jiffies
868 + msecs_to_jiffies(musb->a_wait_bcon));
869 break;
870 case OTG_STATE_A_HOST:
871 musb->xceiv->state = OTG_STATE_A_SUSPEND;
872 musb->is_active = is_otg_enabled(musb)
873 && musb->xceiv->host->b_hnp_enable;
874 break;
875 case OTG_STATE_B_HOST:
876 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
877 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
878 break;
879 default:
880 /* "should not happen" */
881 musb->is_active = 0;
882 break;
883 }
884 schedule_work(&musb->irq_work);
885 }
886
887
888 return handled;
889 }
890
891 /*-------------------------------------------------------------------------*/
892
893 /*
894 * Program the HDRC to start (enable interrupts, dma, etc.).
895 */
896 void musb_start(struct musb *musb)
897 {
898 void __iomem *regs = musb->mregs;
899 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
900
901 DBG(2, "<== devctl %02x\n", devctl);
902
903 /* Set INT enable registers, enable interrupts */
904 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
905 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
906 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
907
908 musb_writeb(regs, MUSB_TESTMODE, 0);
909
910 /* put into basic highspeed mode and start session */
911 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
912 | MUSB_POWER_SOFTCONN
913 | MUSB_POWER_HSENAB
914 /* ENSUSPEND wedges tusb */
915 /* | MUSB_POWER_ENSUSPEND */
916 );
917
918 musb->is_active = 0;
919 devctl = musb_readb(regs, MUSB_DEVCTL);
920 devctl &= ~MUSB_DEVCTL_SESSION;
921
922 if (is_otg_enabled(musb)) {
923 /* session started after:
924 * (a) ID-grounded irq, host mode;
925 * (b) vbus present/connect IRQ, peripheral mode;
926 * (c) peripheral initiates, using SRP
927 */
928 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
929 musb->is_active = 1;
930 else if (!cpu_is_omap3517())
931 devctl |= MUSB_DEVCTL_SESSION;
932
933 } else if (is_host_enabled(musb)) {
934 /* assume ID pin is hard-wired to ground */
935 devctl |= MUSB_DEVCTL_SESSION;
936
937 } else /* peripheral is enabled */ {
938 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
939 musb->is_active = 1;
940 }
941 musb_platform_enable(musb);
942 musb_writeb(regs, MUSB_DEVCTL, devctl);
943 }
944
945
946 static void musb_generic_disable(struct musb *musb)
947 {
948 void __iomem *mbase = musb->mregs;
949 u16 temp;
950
951 /* disable interrupts */
952 musb_writeb(mbase, MUSB_INTRUSBE, 0);
953 musb_writew(mbase, MUSB_INTRTXE, 0);
954 musb_writew(mbase, MUSB_INTRRXE, 0);
955
956 /* off */
957 musb_writeb(mbase, MUSB_DEVCTL, 0);
958
959 /* flush pending interrupts */
960 temp = musb_readb(mbase, MUSB_INTRUSB);
961 temp = musb_readw(mbase, MUSB_INTRTX);
962 temp = musb_readw(mbase, MUSB_INTRRX);
963
964 }
965
966 /*
967 * Make the HDRC stop (disable interrupts, etc.);
968 * reversible by musb_start
969 * called on gadget driver unregister
970 * with controller locked, irqs blocked
971 * acts as a NOP unless some role activated the hardware
972 */
973 void musb_stop(struct musb *musb)
974 {
975 /* stop IRQs, timers, ... */
976 musb_platform_disable(musb);
977 musb_generic_disable(musb);
978 DBG(3, "HDRC disabled\n");
979
980 /* FIXME
981 * - mark host and/or peripheral drivers unusable/inactive
982 * - disable DMA (and enable it in HdrcStart)
983 * - make sure we can musb_start() after musb_stop(); with
984 * OTG mode, gadget driver module rmmod/modprobe cycles that
985 * - ...
986 */
987 musb_platform_try_idle(musb, 0);
988 }
989
990 static void musb_shutdown(struct platform_device *pdev)
991 {
992 struct musb *musb = dev_to_musb(&pdev->dev);
993 unsigned long flags;
994
995 spin_lock_irqsave(&musb->lock, flags);
996 musb_platform_disable(musb);
997 musb_generic_disable(musb);
998 if (musb->clock) {
999 clk_put(musb->clock);
1000 musb->clock = NULL;
1001 }
1002 spin_unlock_irqrestore(&musb->lock, flags);
1003
1004 /* FIXME power down */
1005 }
1006
1007
1008 /*-------------------------------------------------------------------------*/
1009
1010 /*
1011 * The silicon either has hard-wired endpoint configurations, or else
1012 * "dynamic fifo" sizing. The driver has support for both, though at this
1013 * writing only the dynamic sizing is very well tested. Since we switched
1014 * away from compile-time hardware parameters, we can no longer rely on
1015 * dead code elimination to leave only the relevant one in the object file.
1016 *
1017 * We don't currently use dynamic fifo setup capability to do anything
1018 * more than selecting one of a bunch of predefined configurations.
1019 */
1020 #if defined(CONFIG_USB_TUSB6010) || \
1021 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX) || \
1022 defined(CONFIG_MACH_OMAP3517EVM)
1023 static ushort __initdata fifo_mode = 4;
1024 #else
1025 static ushort __initdata fifo_mode = 2;
1026 #endif
1027
1028 /* "modprobe ... fifo_mode=1" etc */
1029 module_param(fifo_mode, ushort, 0);
1030 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1031
1032
1033 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
1034 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
1035
1036 struct fifo_cfg {
1037 u8 hw_ep_num;
1038 enum fifo_style style;
1039 enum buf_mode mode;
1040 u16 maxpacket;
1041 };
1042
1043 /*
1044 * tables defining fifo_mode values. define more if you like.
1045 * for host side, make sure both halves of ep1 are set up.
1046 */
1047
1048 /* mode 0 - fits in 2KB */
1049 static struct fifo_cfg __initdata mode_0_cfg[] = {
1050 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1051 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1052 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1053 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1054 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1055 };
1056
1057 /* mode 1 - fits in 4KB */
1058 static struct fifo_cfg __initdata mode_1_cfg[] = {
1059 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1060 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1061 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1062 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1063 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1064 };
1065
1066 /* mode 2 - fits in 4KB */
1067 static struct fifo_cfg __initdata mode_2_cfg[] = {
1068 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1069 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1070 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1071 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1072 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1073 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1074 };
1075
1076 /* mode 3 - fits in 4KB */
1077 static struct fifo_cfg __initdata mode_3_cfg[] = {
1078 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1079 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1080 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1081 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1082 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1083 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1084 };
1085
1086 /* mode 4 - fits in 16KB */
1087 static struct fifo_cfg __initdata mode_4_cfg[] = {
1088 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1089 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1090 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1091 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1092 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1093 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1094 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1095 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1096 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1097 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1098 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1099 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1100 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1101 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1102 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1103 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1104 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1105 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1106 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1107 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1108 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1109 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1110 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1111 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1112 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1113 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1114 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1115 };
1116
1117
1118 /*
1119 * configure a fifo; for non-shared endpoints, this may be called
1120 * once for a tx fifo and once for an rx fifo.
1121 *
1122 * returns negative errno or offset for next fifo.
1123 */
1124 static int __init
1125 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1126 const struct fifo_cfg *cfg, u16 offset)
1127 {
1128 void __iomem *mbase = musb->mregs;
1129 int size = 0;
1130 u16 maxpacket = cfg->maxpacket;
1131 u16 c_off = offset >> 3;
1132 u8 c_size;
1133
1134 /* expect hw_ep has already been zero-initialized */
1135
1136 size = ffs(max(maxpacket, (u16) 8)) - 1;
1137 maxpacket = 1 << size;
1138
1139 c_size = size - 3;
1140 if (cfg->mode == BUF_DOUBLE) {
1141 if ((offset + (maxpacket << 1)) >
1142 (1 << (musb->config->ram_bits + 2)))
1143 return -EMSGSIZE;
1144 c_size |= MUSB_FIFOSZ_DPB;
1145 } else {
1146 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1147 return -EMSGSIZE;
1148 }
1149
1150 /* configure the FIFO */
1151 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1152
1153 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1154 /* EP0 reserved endpoint for control, bidirectional;
1155 * EP1 reserved for bulk, two unidirection halves.
1156 */
1157 if (hw_ep->epnum == 1)
1158 musb->bulk_ep = hw_ep;
1159 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1160 #endif
1161 switch (cfg->style) {
1162 case FIFO_TX:
1163 musb_write_txfifosz(mbase, c_size);
1164 musb_write_txfifoadd(mbase, c_off);
1165 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1166 hw_ep->max_packet_sz_tx = maxpacket;
1167 break;
1168 case FIFO_RX:
1169 musb_write_rxfifosz(mbase, c_size);
1170 musb_write_rxfifoadd(mbase, c_off);
1171 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1172 hw_ep->max_packet_sz_rx = maxpacket;
1173 break;
1174 case FIFO_RXTX:
1175 musb_write_txfifosz(mbase, c_size);
1176 musb_write_txfifoadd(mbase, c_off);
1177 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1178 hw_ep->max_packet_sz_rx = maxpacket;
1179
1180 musb_write_rxfifosz(mbase, c_size);
1181 musb_write_rxfifoadd(mbase, c_off);
1182 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1183 hw_ep->max_packet_sz_tx = maxpacket;
1184
1185 hw_ep->is_shared_fifo = true;
1186 break;
1187 }
1188
1189 /* NOTE rx and tx endpoint irqs aren't managed separately,
1190 * which happens to be ok
1191 */
1192 musb->epmask |= (1 << hw_ep->epnum);
1193
1194 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1195 }
1196
1197 static struct fifo_cfg __initdata ep0_cfg = {
1198 .style = FIFO_RXTX, .maxpacket = 64,
1199 };
1200
1201 static int __init ep_config_from_table(struct musb *musb)
1202 {
1203 const struct fifo_cfg *cfg;
1204 unsigned i, n;
1205 int offset;
1206 struct musb_hw_ep *hw_ep = musb->endpoints;
1207
1208 switch (fifo_mode) {
1209 default:
1210 fifo_mode = 0;
1211 /* FALLTHROUGH */
1212 case 0:
1213 cfg = mode_0_cfg;
1214 n = ARRAY_SIZE(mode_0_cfg);
1215 break;
1216 case 1:
1217 cfg = mode_1_cfg;
1218 n = ARRAY_SIZE(mode_1_cfg);
1219 break;
1220 case 2:
1221 cfg = mode_2_cfg;
1222 n = ARRAY_SIZE(mode_2_cfg);
1223 break;
1224 case 3:
1225 cfg = mode_3_cfg;
1226 n = ARRAY_SIZE(mode_3_cfg);
1227 break;
1228 case 4:
1229 cfg = mode_4_cfg;
1230 n = ARRAY_SIZE(mode_4_cfg);
1231 break;
1232 }
1233
1234 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1235 musb_driver_name, fifo_mode);
1236
1237
1238 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1239 /* assert(offset > 0) */
1240
1241 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1242 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1243 */
1244
1245 for (i = 0; i < n; i++) {
1246 u8 epn = cfg->hw_ep_num;
1247
1248 if (epn >= musb->config->num_eps) {
1249 pr_debug("%s: invalid ep %d\n",
1250 musb_driver_name, epn);
1251 return -EINVAL;
1252 }
1253 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1254 if (offset < 0) {
1255 pr_debug("%s: mem overrun, ep %d\n",
1256 musb_driver_name, epn);
1257 return -EINVAL;
1258 }
1259 epn++;
1260 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1261 }
1262
1263 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1264 musb_driver_name,
1265 n + 1, musb->config->num_eps * 2 - 1,
1266 offset, (1 << (musb->config->ram_bits + 2)));
1267
1268 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1269 if (!musb->bulk_ep) {
1270 pr_debug("%s: missing bulk\n", musb_driver_name);
1271 return -EINVAL;
1272 }
1273 #endif
1274
1275 return 0;
1276 }
1277
1278
1279 /*
1280 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1281 * @param musb the controller
1282 */
1283 static int __init ep_config_from_hw(struct musb *musb)
1284 {
1285 u8 epnum = 0;
1286 struct musb_hw_ep *hw_ep;
1287 void *mbase = musb->mregs;
1288 int ret = 0;
1289
1290 DBG(2, "<== static silicon ep config\n");
1291
1292 /* FIXME pick up ep0 maxpacket size */
1293
1294 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1295 musb_ep_select(mbase, epnum);
1296 hw_ep = musb->endpoints + epnum;
1297
1298 ret = musb_read_fifosize(musb, hw_ep, epnum);
1299 if (ret < 0)
1300 break;
1301
1302 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1303
1304 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1305 /* pick an RX/TX endpoint for bulk */
1306 if (hw_ep->max_packet_sz_tx < 512
1307 || hw_ep->max_packet_sz_rx < 512)
1308 continue;
1309
1310 /* REVISIT: this algorithm is lazy, we should at least
1311 * try to pick a double buffered endpoint.
1312 */
1313 if (musb->bulk_ep)
1314 continue;
1315 musb->bulk_ep = hw_ep;
1316 #endif
1317 }
1318
1319 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1320 if (!musb->bulk_ep) {
1321 pr_debug("%s: missing bulk\n", musb_driver_name);
1322 return -EINVAL;
1323 }
1324 #endif
1325
1326 return 0;
1327 }
1328
1329 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1330
1331 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1332 * configure endpoints, or take their config from silicon
1333 */
1334 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1335 {
1336 #ifdef MUSB_AHB_ID
1337 u32 data;
1338 #endif
1339 u8 reg;
1340 char *type;
1341 u16 hwvers, rev_major, rev_minor;
1342 char aInfo[78], aRevision[32], aDate[12];
1343 void __iomem *mbase = musb->mregs;
1344 int status = 0;
1345 int i;
1346
1347 /* log core options (read using indexed model) */
1348 reg = musb_read_configdata(mbase);
1349
1350 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1351 if (reg & MUSB_CONFIGDATA_DYNFIFO)
1352 strcat(aInfo, ", dyn FIFOs");
1353 if (reg & MUSB_CONFIGDATA_MPRXE) {
1354 strcat(aInfo, ", bulk combine");
1355 #ifdef C_MP_RX
1356 musb->bulk_combine = true;
1357 #else
1358 strcat(aInfo, " (X)"); /* no driver support */
1359 #endif
1360 }
1361 if (reg & MUSB_CONFIGDATA_MPTXE) {
1362 strcat(aInfo, ", bulk split");
1363 #ifdef C_MP_TX
1364 musb->bulk_split = true;
1365 #else
1366 strcat(aInfo, " (X)"); /* no driver support */
1367 #endif
1368 }
1369 if (reg & MUSB_CONFIGDATA_HBRXE) {
1370 strcat(aInfo, ", HB-ISO Rx");
1371 musb->hb_iso_rx = true;
1372 }
1373 if (reg & MUSB_CONFIGDATA_HBTXE) {
1374 strcat(aInfo, ", HB-ISO Tx");
1375 musb->hb_iso_tx = true;
1376 }
1377 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1378 strcat(aInfo, ", SoftConn");
1379
1380 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1381 musb_driver_name, reg, aInfo);
1382
1383 #ifdef MUSB_AHB_ID
1384 data = musb_readl(mbase, 0x404);
1385 sprintf(aDate, "%04d-%02x-%02x", (data & 0xffff),
1386 (data >> 16) & 0xff, (data >> 24) & 0xff);
1387 /* FIXME ID2 and ID3 are unused */
1388 data = musb_readl(mbase, 0x408);
1389 printk(KERN_DEBUG "ID2=%lx\n", (long unsigned)data);
1390 data = musb_readl(mbase, 0x40c);
1391 printk(KERN_DEBUG "ID3=%lx\n", (long unsigned)data);
1392 reg = musb_readb(mbase, 0x400);
1393 musb_type = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1394 #else
1395 aDate[0] = 0;
1396 #endif
1397 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1398 musb->is_multipoint = 1;
1399 type = "M";
1400 } else {
1401 musb->is_multipoint = 0;
1402 type = "";
1403 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1404 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1405 printk(KERN_ERR
1406 "%s: kernel must blacklist external hubs\n",
1407 musb_driver_name);
1408 #endif
1409 #endif
1410 }
1411
1412 /* log release info */
1413 hwvers = musb_read_hwvers(mbase);
1414 rev_major = (hwvers >> 10) & 0x1f;
1415 rev_minor = hwvers & 0x3ff;
1416 snprintf(aRevision, 32, "%d.%d%s", rev_major,
1417 rev_minor, (hwvers & 0x8000) ? "RC" : "");
1418 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1419 musb_driver_name, type, aRevision, aDate);
1420
1421 /* configure ep0 */
1422 musb_configure_ep0(musb);
1423
1424 /* discover endpoint configuration */
1425 musb->nr_endpoints = 1;
1426 musb->epmask = 1;
1427
1428 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1429 if (musb->config->dyn_fifo)
1430 status = ep_config_from_table(musb);
1431 else {
1432 ERR("reconfigure software for Dynamic FIFOs\n");
1433 status = -ENODEV;
1434 }
1435 } else {
1436 if (!musb->config->dyn_fifo)
1437 status = ep_config_from_hw(musb);
1438 else {
1439 ERR("reconfigure software for static FIFOs\n");
1440 return -ENODEV;
1441 }
1442 }
1443
1444 if (status < 0)
1445 return status;
1446
1447 /* finish init, and print endpoint config */
1448 for (i = 0; i < musb->nr_endpoints; i++) {
1449 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1450
1451 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1452 #ifdef CONFIG_USB_TUSB6010
1453 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1454 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1455 hw_ep->fifo_sync_va =
1456 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1457
1458 if (i == 0)
1459 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1460 else
1461 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1462 #endif
1463
1464 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1465 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1466 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1467 hw_ep->rx_reinit = 1;
1468 hw_ep->tx_reinit = 1;
1469 #endif
1470
1471 if (hw_ep->max_packet_sz_tx) {
1472 DBG(1,
1473 "%s: hw_ep %d%s, %smax %d\n",
1474 musb_driver_name, i,
1475 hw_ep->is_shared_fifo ? "shared" : "tx",
1476 hw_ep->tx_double_buffered
1477 ? "doublebuffer, " : "",
1478 hw_ep->max_packet_sz_tx);
1479 }
1480 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1481 DBG(1,
1482 "%s: hw_ep %d%s, %smax %d\n",
1483 musb_driver_name, i,
1484 "rx",
1485 hw_ep->rx_double_buffered
1486 ? "doublebuffer, " : "",
1487 hw_ep->max_packet_sz_rx);
1488 }
1489 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1490 DBG(1, "hw_ep %d not configured\n", i);
1491 }
1492
1493 return 0;
1494 }
1495
1496 /*-------------------------------------------------------------------------*/
1497
1498 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1499
1500 static irqreturn_t generic_interrupt(int irq, void *__hci)
1501 {
1502 unsigned long flags;
1503 irqreturn_t retval = IRQ_NONE;
1504 struct musb *musb = __hci;
1505
1506 spin_lock_irqsave(&musb->lock, flags);
1507
1508 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1509 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1510 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1511
1512 if (musb->int_usb || musb->int_tx || musb->int_rx)
1513 retval = musb_interrupt(musb);
1514
1515 spin_unlock_irqrestore(&musb->lock, flags);
1516
1517 return retval;
1518 }
1519
1520 #else
1521 #define generic_interrupt NULL
1522 #endif
1523
1524 /*
1525 * handle all the irqs defined by the HDRC core. for now we expect: other
1526 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1527 * will be assigned, and the irq will already have been acked.
1528 *
1529 * called in irq context with spinlock held, irqs blocked
1530 */
1531 irqreturn_t musb_interrupt(struct musb *musb)
1532 {
1533 irqreturn_t retval = IRQ_NONE;
1534 u8 devctl, power;
1535 int ep_num;
1536 u32 reg;
1537
1538 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1539 power = musb_readb(musb->mregs, MUSB_POWER);
1540
1541 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1542 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1543 musb->int_usb, musb->int_tx, musb->int_rx);
1544
1545 /* the core can interrupt us for multiple reasons; docs have
1546 * a generic interrupt flowchart to follow
1547 */
1548 if (musb->int_usb & STAGE0_MASK)
1549 retval |= musb_stage0_irq(musb, musb->int_usb,
1550 devctl, power);
1551
1552 /* "stage 1" is handling endpoint irqs */
1553
1554 /* handle endpoint 0 first */
1555 if (musb->int_tx & 1) {
1556 if (devctl & MUSB_DEVCTL_HM)
1557 retval |= musb_h_ep0_irq(musb);
1558 else
1559 retval |= musb_g_ep0_irq(musb);
1560 }
1561
1562 /* RX on endpoints 1-15 */
1563 reg = musb->int_rx >> 1;
1564 ep_num = 1;
1565 while (reg) {
1566 if (reg & 1) {
1567 /* musb_ep_select(musb->mregs, ep_num); */
1568 /* REVISIT just retval = ep->rx_irq(...) */
1569 retval = IRQ_HANDLED;
1570 if (devctl & MUSB_DEVCTL_HM) {
1571 if (is_host_capable())
1572 musb_host_rx(musb, ep_num);
1573 } else {
1574 if (is_peripheral_capable())
1575 musb_g_rx(musb, ep_num);
1576 }
1577 }
1578
1579 reg >>= 1;
1580 ep_num++;
1581 }
1582
1583 /* TX on endpoints 1-15 */
1584 reg = musb->int_tx >> 1;
1585 ep_num = 1;
1586 while (reg) {
1587 if (reg & 1) {
1588 /* musb_ep_select(musb->mregs, ep_num); */
1589 /* REVISIT just retval |= ep->tx_irq(...) */
1590 retval = IRQ_HANDLED;
1591 if (devctl & MUSB_DEVCTL_HM) {
1592 if (is_host_capable())
1593 musb_host_tx(musb, ep_num);
1594 } else {
1595 if (is_peripheral_capable())
1596 musb_g_tx(musb, ep_num);
1597 }
1598 }
1599 reg >>= 1;
1600 ep_num++;
1601 }
1602
1603 /* finish handling "global" interrupts after handling fifos */
1604 if (musb->int_usb)
1605 retval |= musb_stage2_irq(musb,
1606 musb->int_usb, devctl, power);
1607
1608 return retval;
1609 }
1610
1611
1612 #ifndef CONFIG_MUSB_PIO_ONLY
1613 static int __initdata use_dma = 1;
1614
1615 /* "modprobe ... use_dma=0" etc */
1616 module_param(use_dma, bool, 0);
1617 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1618
1619 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1620 {
1621 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1622
1623 /* called with controller lock already held */
1624
1625 if (!epnum) {
1626 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1627 if (!is_cppi_enabled() && !is_cppi41_enabled()) {
1628 /* endpoint 0 */
1629 if (devctl & MUSB_DEVCTL_HM)
1630 musb_h_ep0_irq(musb);
1631 else
1632 musb_g_ep0_irq(musb);
1633 }
1634 #endif
1635 } else {
1636 /* endpoints 1..15 */
1637 if (transmit) {
1638 if (devctl & MUSB_DEVCTL_HM) {
1639 if (is_host_capable())
1640 musb_host_tx(musb, epnum);
1641 } else {
1642 if (is_peripheral_capable())
1643 musb_g_tx(musb, epnum);
1644 }
1645 } else {
1646 /* receive */
1647 if (devctl & MUSB_DEVCTL_HM) {
1648 if (is_host_capable())
1649 musb_host_rx(musb, epnum);
1650 } else {
1651 if (is_peripheral_capable())
1652 musb_g_rx(musb, epnum);
1653 }
1654 }
1655 }
1656 }
1657
1658 #else
1659 #define use_dma 0
1660 #endif
1661
1662 /*-------------------------------------------------------------------------*/
1663
1664 #ifdef CONFIG_SYSFS
1665
1666 static ssize_t
1667 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1668 {
1669 struct musb *musb = dev_to_musb(dev);
1670 unsigned long flags;
1671 int ret = -EINVAL;
1672
1673 spin_lock_irqsave(&musb->lock, flags);
1674 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1675 spin_unlock_irqrestore(&musb->lock, flags);
1676
1677 return ret;
1678 }
1679
1680 static ssize_t
1681 musb_mode_store(struct device *dev, struct device_attribute *attr,
1682 const char *buf, size_t n)
1683 {
1684 struct musb *musb = dev_to_musb(dev);
1685 unsigned long flags;
1686 int status;
1687
1688 spin_lock_irqsave(&musb->lock, flags);
1689 if (sysfs_streq(buf, "host"))
1690 status = musb_platform_set_mode(musb, MUSB_HOST);
1691 else if (sysfs_streq(buf, "peripheral"))
1692 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1693 else if (sysfs_streq(buf, "otg"))
1694 status = musb_platform_set_mode(musb, MUSB_OTG);
1695 else
1696 status = -EINVAL;
1697 spin_unlock_irqrestore(&musb->lock, flags);
1698
1699 return (status == 0) ? n : status;
1700 }
1701 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1702
1703 static ssize_t
1704 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1705 const char *buf, size_t n)
1706 {
1707 struct musb *musb = dev_to_musb(dev);
1708 unsigned long flags;
1709 unsigned long val;
1710
1711 if (sscanf(buf, "%lu", &val) < 1) {
1712 printk(KERN_ERR "Invalid VBUS timeout ms value\n");
1713 return -EINVAL;
1714 }
1715
1716 spin_lock_irqsave(&musb->lock, flags);
1717 musb->a_wait_bcon = val;
1718 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1719 musb->is_active = 0;
1720 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1721 spin_unlock_irqrestore(&musb->lock, flags);
1722
1723 return n;
1724 }
1725
1726 static ssize_t
1727 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1728 {
1729 struct musb *musb = dev_to_musb(dev);
1730 unsigned long flags;
1731 unsigned long val;
1732 int vbus;
1733
1734 spin_lock_irqsave(&musb->lock, flags);
1735 val = musb->a_wait_bcon;
1736 vbus = musb_platform_get_vbus_status(musb);
1737 spin_unlock_irqrestore(&musb->lock, flags);
1738
1739 return sprintf(buf, "Vbus %s, timeout %lu\n",
1740 vbus ? "on" : "off", val);
1741 }
1742 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1743
1744 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1745
1746 /* Gadget drivers can't know that a host is connected so they might want
1747 * to start SRP, but users can. This allows userspace to trigger SRP.
1748 */
1749 static ssize_t
1750 musb_srp_store(struct device *dev, struct device_attribute *attr,
1751 const char *buf, size_t n)
1752 {
1753 struct musb *musb = dev_to_musb(dev);
1754 unsigned short srp;
1755
1756 if (sscanf(buf, "%hu", &srp) != 1
1757 || (srp != 1)) {
1758 printk(KERN_ERR "SRP: Value must be 1\n");
1759 return -EINVAL;
1760 }
1761
1762 if (srp == 1)
1763 musb_g_wakeup(musb);
1764
1765 return n;
1766 }
1767 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1768
1769 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1770
1771 #endif /* sysfs */
1772
1773 /* Only used to provide driver mode change events */
1774 static void musb_irq_work(struct work_struct *data)
1775 {
1776 struct musb *musb = container_of(data, struct musb, irq_work);
1777 static int old_state;
1778
1779 if (musb->xceiv->state != old_state) {
1780 old_state = musb->xceiv->state;
1781 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1782 }
1783 }
1784
1785 /* --------------------------------------------------------------------------
1786 * Init support
1787 */
1788
1789 static struct musb *__init
1790 allocate_instance(struct device *dev,
1791 struct musb_hdrc_config *config, void __iomem *mbase)
1792 {
1793 struct musb *musb;
1794 struct musb_hw_ep *ep;
1795 int epnum;
1796 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1797 struct usb_hcd *hcd;
1798
1799 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1800 if (!hcd)
1801 return NULL;
1802 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1803
1804 musb = hcd_to_musb(hcd);
1805 INIT_LIST_HEAD(&musb->control);
1806 INIT_LIST_HEAD(&musb->in_bulk);
1807 INIT_LIST_HEAD(&musb->out_bulk);
1808
1809 hcd->uses_new_polling = 1;
1810
1811 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1812 #else
1813 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1814 if (!musb)
1815 return NULL;
1816 dev_set_drvdata(dev, musb);
1817
1818 #endif
1819
1820 musb->mregs = mbase;
1821 musb->ctrl_base = mbase;
1822 musb->nIrq = -ENODEV;
1823 musb->config = config;
1824 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1825 for (epnum = 0, ep = musb->endpoints;
1826 epnum < musb->config->num_eps;
1827 epnum++, ep++) {
1828 ep->musb = musb;
1829 ep->epnum = epnum;
1830 }
1831
1832 musb->controller = dev;
1833 return musb;
1834 }
1835
1836 static void musb_free(struct musb *musb)
1837 {
1838 /* this has multiple entry modes. it handles fault cleanup after
1839 * probe(), where things may be partially set up, as well as rmmod
1840 * cleanup after everything's been de-activated.
1841 */
1842
1843 #ifdef CONFIG_SYSFS
1844 device_remove_file(musb->controller, &dev_attr_mode);
1845 device_remove_file(musb->controller, &dev_attr_vbus);
1846 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1847 device_remove_file(musb->controller, &dev_attr_srp);
1848 #endif
1849 #endif
1850
1851 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1852 musb_gadget_cleanup(musb);
1853 #endif
1854
1855 if (musb->nIrq >= 0) {
1856 if (musb->irq_wake)
1857 disable_irq_wake(musb->nIrq);
1858 free_irq(musb->nIrq, musb);
1859 }
1860 if (is_dma_capable() && musb->dma_controller) {
1861 struct dma_controller *c = musb->dma_controller;
1862
1863 (void) c->stop(c);
1864 dma_controller_destroy(c);
1865 }
1866
1867 #ifdef CONFIG_USB_MUSB_OTG
1868 put_device(musb->xceiv->dev);
1869 #endif
1870
1871 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1872 musb_platform_exit(musb);
1873 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1874
1875 if (musb->clock) {
1876 clk_disable(musb->clock);
1877 clk_put(musb->clock);
1878 }
1879
1880 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1881 usb_put_hcd(musb_to_hcd(musb));
1882 #else
1883 kfree(musb);
1884 #endif
1885 }
1886
1887 /*
1888 * Perform generic per-controller initialization.
1889 *
1890 * @pDevice: the controller (already clocked, etc)
1891 * @nIrq: irq
1892 * @mregs: virtual address of controller registers,
1893 * not yet corrected for platform-specific offsets
1894 */
1895 static int __init
1896 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1897 {
1898 int status;
1899 struct musb *musb;
1900 struct musb_hdrc_platform_data *plat = dev->platform_data;
1901
1902 /* The driver might handle more features than the board; OK.
1903 * Fail when the board needs a feature that's not enabled.
1904 */
1905 if (!plat) {
1906 dev_dbg(dev, "no platform_data?\n");
1907 return -ENODEV;
1908 }
1909 switch (plat->mode) {
1910 case MUSB_HOST:
1911 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1912 break;
1913 #else
1914 goto bad_config;
1915 #endif
1916 case MUSB_PERIPHERAL:
1917 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1918 break;
1919 #else
1920 goto bad_config;
1921 #endif
1922 case MUSB_OTG:
1923 #ifdef CONFIG_USB_MUSB_OTG
1924 break;
1925 #else
1926 bad_config:
1927 #endif
1928 default:
1929 dev_err(dev, "incompatible Kconfig role setting\n");
1930 return -EINVAL;
1931 }
1932
1933 /* allocate */
1934 musb = allocate_instance(dev, plat->config, ctrl);
1935 if (!musb)
1936 return -ENOMEM;
1937
1938 spin_lock_init(&musb->lock);
1939 musb->board_mode = plat->mode;
1940 musb->board_set_power = plat->set_power;
1941 musb->set_clock = plat->set_clock;
1942 musb->min_power = plat->min_power;
1943
1944 /* Clock usage is chip-specific ... functional clock (DaVinci,
1945 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
1946 * code does is make sure a clock handle is available; platform
1947 * code manages it during start/stop and suspend/resume.
1948 */
1949 if (plat->clock) {
1950 musb->clock = clk_get(dev, plat->clock);
1951 if (IS_ERR(musb->clock)) {
1952 status = PTR_ERR(musb->clock);
1953 musb->clock = NULL;
1954 goto fail;
1955 }
1956 }
1957
1958 /* The musb_platform_init() call:
1959 * - adjusts musb->mregs and musb->isr if needed,
1960 * - may initialize an integrated tranceiver
1961 * - initializes musb->xceiv, usually by otg_get_transceiver()
1962 * - activates clocks.
1963 * - stops powering VBUS
1964 * - assigns musb->board_set_vbus if host mode is enabled
1965 *
1966 * There are various transciever configurations. Blackfin,
1967 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1968 * external/discrete ones in various flavors (twl4030 family,
1969 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1970 */
1971 musb->isr = generic_interrupt;
1972 status = musb_platform_init(musb);
1973
1974 if (status < 0)
1975 goto fail;
1976 if (!musb->isr) {
1977 status = -ENODEV;
1978 goto fail2;
1979 }
1980
1981 #ifdef CONFIG_PM
1982 musb_base = musb->mregs;
1983 #endif
1984 #ifndef CONFIG_MUSB_PIO_ONLY
1985 if (use_dma && dev->dma_mask) {
1986 struct dma_controller *c;
1987
1988 c = dma_controller_create(musb, musb->mregs);
1989 musb->dma_controller = c;
1990 if (c)
1991 (void) c->start(c);
1992 }
1993 #endif
1994 /* ideally this would be abstracted in platform setup */
1995 if (!is_dma_capable() || !musb->dma_controller)
1996 dev->dma_mask = NULL;
1997
1998 /* be sure interrupts are disabled before connecting ISR */
1999 musb_platform_disable(musb);
2000 musb_generic_disable(musb);
2001
2002 /* setup musb parts of the core (especially endpoints) */
2003 status = musb_core_init(plat->config->multipoint
2004 ? MUSB_CONTROLLER_MHDRC
2005 : MUSB_CONTROLLER_HDRC, musb);
2006 if (status < 0)
2007 goto fail2;
2008
2009 /* Init IRQ workqueue before request_irq */
2010 INIT_WORK(&musb->irq_work, musb_irq_work);
2011
2012 /* attach to the IRQ */
2013 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2014 dev_err(dev, "request_irq %d failed!\n", nIrq);
2015 status = -ENODEV;
2016 goto fail2;
2017 }
2018 musb->nIrq = nIrq;
2019 /* FIXME this handles wakeup irqs wrong */
2020 if (enable_irq_wake(nIrq) == 0) {
2021 musb->irq_wake = 1;
2022 device_init_wakeup(dev, 1);
2023 } else {
2024 musb->irq_wake = 0;
2025 }
2026
2027 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
2028 musb_driver_name,
2029 ({char *s;
2030 switch (musb->board_mode) {
2031 case MUSB_HOST: s = "Host"; break;
2032 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2033 default: s = "OTG"; break;
2034 }; s; }),
2035 ctrl,
2036 (is_dma_capable() && musb->dma_controller)
2037 ? "DMA" : "PIO",
2038 musb->nIrq);
2039
2040 /* host side needs more setup */
2041 if (is_host_enabled(musb)) {
2042 struct usb_hcd *hcd = musb_to_hcd(musb);
2043
2044 otg_set_host(musb->xceiv, &hcd->self);
2045
2046 if (is_otg_enabled(musb))
2047 hcd->self.otg_port = 1;
2048 musb->xceiv->host = &hcd->self;
2049 hcd->power_budget = 2 * (plat->power ? : 250);
2050 }
2051
2052 /* For the host-only role, we can activate right away.
2053 * (We expect the ID pin to be forcibly grounded!!)
2054 * Otherwise, wait till the gadget driver hooks up.
2055 */
2056 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2057 MUSB_HST_MODE(musb);
2058 musb->xceiv->default_a = 1;
2059 musb->xceiv->state = OTG_STATE_A_IDLE;
2060
2061 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2062
2063 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2064 "HOST", status,
2065 musb_readb(musb->mregs, MUSB_DEVCTL),
2066 (musb_readb(musb->mregs, MUSB_DEVCTL)
2067 & MUSB_DEVCTL_BDEVICE
2068 ? 'B' : 'A'));
2069
2070 } else /* peripheral is enabled */ {
2071 MUSB_DEV_MODE(musb);
2072 musb->xceiv->default_a = 0;
2073 musb->xceiv->state = OTG_STATE_B_IDLE;
2074
2075 status = musb_gadget_setup(musb);
2076
2077 DBG(1, "%s mode, status %d, dev%02x\n",
2078 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2079 status,
2080 musb_readb(musb->mregs, MUSB_DEVCTL));
2081
2082 }
2083
2084 #ifdef CONFIG_SYSFS
2085 status = device_create_file(dev, &dev_attr_mode);
2086 status = device_create_file(dev, &dev_attr_vbus);
2087 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2088 status = device_create_file(dev, &dev_attr_srp);
2089 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2090 status = 0;
2091 #endif
2092 if (status)
2093 goto fail2;
2094 if (status == 0)
2095 musb_debug_create("driver/musb_hdrc", musb);
2096 return 0;
2097
2098 fail2:
2099 #ifdef CONFIG_SYSFS
2100 device_remove_file(musb->controller, &dev_attr_mode);
2101 device_remove_file(musb->controller, &dev_attr_vbus);
2102 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2103 device_remove_file(musb->controller, &dev_attr_srp);
2104 #endif
2105 #endif
2106 musb_platform_exit(musb);
2107 fail:
2108 dev_err(musb->controller,
2109 "musb_init_controller failed with status %d\n", status);
2110
2111 if (musb->clock)
2112 clk_put(musb->clock);
2113 device_init_wakeup(dev, 0);
2114 musb_free(musb);
2115
2116 return status;
2117
2118 }
2119
2120 /*-------------------------------------------------------------------------*/
2121
2122 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2123 * bridge to a platform device; this driver then suffices.
2124 */
2125
2126 #ifndef CONFIG_MUSB_PIO_ONLY
2127 static u64 *orig_dma_mask;
2128 #endif
2129
2130 static int __init musb_probe(struct platform_device *pdev)
2131 {
2132 struct device *dev = &pdev->dev;
2133 int irq = platform_get_irq(pdev, 0);
2134 struct resource *iomem;
2135 void __iomem *base;
2136
2137 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2138 if (!iomem || irq == 0)
2139 return -ENODEV;
2140
2141 base = ioremap(iomem->start, iomem->end - iomem->start + 1);
2142 if (!base) {
2143 dev_err(dev, "ioremap failed\n");
2144 return -ENOMEM;
2145 }
2146
2147 #ifndef CONFIG_MUSB_PIO_ONLY
2148 /* clobbered by use_dma=n */
2149 orig_dma_mask = dev->dma_mask;
2150 #endif
2151 return musb_init_controller(dev, irq, base);
2152 }
2153
2154 static int __devexit musb_remove(struct platform_device *pdev)
2155 {
2156 struct musb *musb = dev_to_musb(&pdev->dev);
2157 void __iomem *ctrl_base = musb->ctrl_base;
2158
2159 /* this gets called on rmmod.
2160 * - Host mode: host may still be active
2161 * - Peripheral mode: peripheral is deactivated (or never-activated)
2162 * - OTG mode: both roles are deactivated (or never-activated)
2163 */
2164 musb_shutdown(pdev);
2165 musb_debug_delete("driver/musb_hdrc", musb);
2166 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2167 if (musb->board_mode == MUSB_HOST)
2168 usb_remove_hcd(musb_to_hcd(musb));
2169 #endif
2170 musb_free(musb);
2171 iounmap(ctrl_base);
2172 device_init_wakeup(&pdev->dev, 0);
2173 #ifndef CONFIG_MUSB_PIO_ONLY
2174 pdev->dev.dma_mask = orig_dma_mask;
2175 #endif
2176 return 0;
2177 }
2178
2179 #ifdef CONFIG_PM
2180
2181 static struct musb_context_registers musb_context;
2182
2183 void musb_save_context(void)
2184 {
2185 int i;
2186
2187 if (!musb_clock_on)
2188 return;
2189
2190 musb_context.faddr = musb_readb(musb_base, MUSB_FADDR);
2191 musb_context.power = musb_readb(musb_base, MUSB_POWER);
2192 musb_context.intrtx = musb_readw(musb_base, MUSB_INTRTX);
2193 musb_context.intrrx = musb_readw(musb_base, MUSB_INTRRX);
2194 musb_context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2195 musb_context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2196 musb_context.intrusb = musb_readb(musb_base, MUSB_INTRUSB);
2197 musb_context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2198 musb_context.frame = musb_readw(musb_base, MUSB_FRAME);
2199 musb_context.index = musb_readb(musb_base, MUSB_INDEX);
2200 musb_context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2201 musb_context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2202
2203 for (i = 0; i < MUSB_C_NUM_EPS; ++i) {
2204 musb_writeb(musb_base, MUSB_INDEX, i);
2205 musb_context.index_regs[i].txmaxp =
2206 musb_readw(musb_base, 0x10 + MUSB_TXMAXP);
2207 musb_context.index_regs[i].txcsr =
2208 musb_readw(musb_base, 0x10 + MUSB_TXCSR);
2209 musb_context.index_regs[i].rxmaxp =
2210 musb_readw(musb_base, 0x10 + MUSB_RXMAXP);
2211 musb_context.index_regs[i].rxcsr =
2212 musb_readw(musb_base, 0x10 + MUSB_RXCSR);
2213 musb_context.index_regs[i].rxcount =
2214 musb_readw(musb_base, 0x10 + MUSB_RXCOUNT);
2215 musb_context.index_regs[i].txtype =
2216 musb_readb(musb_base, 0x10 + MUSB_TXTYPE);
2217 musb_context.index_regs[i].txinterval =
2218 musb_readb(musb_base, 0x10 + MUSB_TXINTERVAL);
2219 musb_context.index_regs[i].rxtype =
2220 musb_readb(musb_base, 0x10 + MUSB_RXTYPE);
2221 musb_context.index_regs[i].rxinterval =
2222 musb_readb(musb_base, 0x10 + MUSB_RXINTERVAL);
2223
2224 musb_context.index_regs[i].txfifoadd =
2225 musb_read_txfifoadd(musb_base);
2226 musb_context.index_regs[i].rxfifoadd =
2227 musb_read_rxfifoadd(musb_base);
2228 musb_context.index_regs[i].txfifosz =
2229 musb_read_txfifosz(musb_base);
2230 musb_context.index_regs[i].rxfifosz =
2231 musb_read_rxfifosz(musb_base);
2232
2233 musb_context.index_regs[i].txfunaddr =
2234 musb_read_txfunaddr(musb_base, i);
2235 musb_context.index_regs[i].txhubaddr =
2236 musb_read_txhubaddr(musb_base, i);
2237 musb_context.index_regs[i].txhubport =
2238 musb_read_txhubport(musb_base, i);
2239
2240 musb_context.index_regs[i].rxfunaddr =
2241 musb_read_rxfunaddr(musb_base, i);
2242 musb_context.index_regs[i].rxhubaddr =
2243 musb_read_rxhubaddr(musb_base, i);
2244 musb_context.index_regs[i].rxhubport =
2245 musb_read_rxhubport(musb_base, i);
2246 }
2247
2248 musb_writeb(musb_base, MUSB_INDEX, musb_context.index);
2249
2250 musb_platform_save_context(&musb_context);
2251 }
2252
2253 void musb_restore_context(void)
2254 {
2255 int i;
2256 void __iomem *ep_target_regs;
2257
2258 if (!musb_clock_on)
2259 return;
2260
2261 musb_platform_restore_context(&musb_context);
2262
2263 musb_writeb(musb_base, MUSB_FADDR, musb_context.faddr);
2264 musb_writeb(musb_base, MUSB_POWER, musb_context.power);
2265 musb_writew(musb_base, MUSB_INTRTX, musb_context.intrtx);
2266 musb_writew(musb_base, MUSB_INTRRX, musb_context.intrrx);
2267 musb_writew(musb_base, MUSB_INTRTXE, musb_context.intrtxe);
2268 musb_writew(musb_base, MUSB_INTRRXE, musb_context.intrrxe);
2269 musb_writeb(musb_base, MUSB_INTRUSB, musb_context.intrusb);
2270 musb_writeb(musb_base, MUSB_INTRUSBE, musb_context.intrusbe);
2271 musb_writew(musb_base, MUSB_FRAME, musb_context.frame);
2272 musb_writeb(musb_base, MUSB_TESTMODE, musb_context.testmode);
2273 musb_writeb(musb_base, MUSB_DEVCTL, musb_context.devctl);
2274
2275
2276 for (i = 0; i < MUSB_C_NUM_EPS; ++i) {
2277 musb_writeb(musb_base, MUSB_INDEX, i);
2278 musb_writew(musb_base, 0x10 + MUSB_TXMAXP,
2279 musb_context.index_regs[i].txmaxp);
2280 musb_writew(musb_base, 0x10 + MUSB_TXCSR,
2281 musb_context.index_regs[i].txcsr);
2282 musb_writew(musb_base, 0x10 + MUSB_RXMAXP,
2283 musb_context.index_regs[i].rxmaxp);
2284 musb_writew(musb_base, 0x10 + MUSB_RXCSR,
2285 musb_context.index_regs[i].rxcsr);
2286 musb_writew(musb_base, 0x10 + MUSB_RXCOUNT,
2287 musb_context.index_regs[i].rxcount);
2288 musb_writeb(musb_base, 0x10 + MUSB_TXTYPE,
2289 musb_context.index_regs[i].txtype);
2290 musb_writeb(musb_base, 0x10 + MUSB_TXINTERVAL,
2291 musb_context.index_regs[i].txinterval);
2292 musb_writeb(musb_base, 0x10 + MUSB_RXTYPE,
2293 musb_context.index_regs[i].rxtype);
2294 musb_writeb(musb_base, 0x10 + MUSB_RXINTERVAL,
2295 musb_context.index_regs[i].rxinterval);
2296
2297 musb_write_txfifosz(musb_base,
2298 musb_context.index_regs[i].txfifosz);
2299 musb_write_rxfifosz(musb_base,
2300 musb_context.index_regs[i].rxfifosz);
2301 musb_write_txfifoadd(musb_base,
2302 musb_context.index_regs[i].txfifoadd);
2303 musb_write_rxfifoadd(musb_base,
2304 musb_context.index_regs[i].rxfifoadd);
2305
2306 musb_write_txfunaddr(musb_base, i,
2307 musb_context.index_regs[i].txfunaddr);
2308 musb_write_txhubaddr(musb_base, i,
2309 musb_context.index_regs[i].txhubaddr);
2310 musb_write_txhubport(musb_base, i,
2311 musb_context.index_regs[i].txhubport);
2312
2313 ep_target_regs = musb_read_target_reg_base(i, musb_base);
2314
2315 musb_write_rxfunaddr(ep_target_regs,
2316 musb_context.index_regs[i].rxfunaddr);
2317 musb_write_rxhubaddr(ep_target_regs,
2318 musb_context.index_regs[i].rxhubaddr);
2319 musb_write_rxhubport(ep_target_regs,
2320 musb_context.index_regs[i].rxhubport);
2321 }
2322
2323 musb_writeb(musb_base, MUSB_INDEX, musb_context.index);
2324 }
2325
2326 static int musb_suspend(struct device *dev)
2327 {
2328 struct platform_device *pdev = to_platform_device(dev);
2329 unsigned long flags;
2330 struct musb *musb = dev_to_musb(&pdev->dev);
2331 u8 reg;
2332
2333 if (!musb->clock)
2334 return 0;
2335
2336 if (!musb_clock_on)
2337 return 0;
2338
2339 spin_lock_irqsave(&musb->lock, flags);
2340
2341 musb_save_context();
2342
2343 if (is_peripheral_active(musb)) {
2344 /* System is entering into suspend where gadget would not be
2345 * able to respond to host and thus it will be in an unknown
2346 * state for host.Re-enumemation of gadget is required after
2347 * resume to make the gadget functional thus doing a force
2348 * disconnect.
2349 */
2350 reg = musb_readb(musb->mregs, MUSB_POWER);
2351 reg &= ~MUSB_POWER_SOFTCONN;
2352 musb_writeb(musb->mregs, MUSB_POWER, reg);
2353
2354 } else if (is_host_active(musb)) {
2355 /* we know all the children are suspended; sometimes
2356 * they will even be wakeup-enabled.
2357 */
2358 }
2359
2360 if (musb->set_clock)
2361 musb->set_clock(musb->clock, 0);
2362 else
2363 clk_disable(musb->clock);
2364
2365 musb_clock_on = 0;
2366
2367 spin_unlock_irqrestore(&musb->lock, flags);
2368 return 0;
2369 }
2370
2371 static int musb_resume_noirq(struct device *dev)
2372 {
2373 struct platform_device *pdev = to_platform_device(dev);
2374 struct musb *musb = dev_to_musb(&pdev->dev);
2375
2376 if (!musb->clock)
2377 return 0;
2378
2379 if (musb_clock_on)
2380 return 0;
2381
2382 if (musb->set_clock)
2383 musb->set_clock(musb->clock, 1);
2384 else
2385 clk_enable(musb->clock);
2386
2387 musb_clock_on = 1;
2388
2389 musb_restore_context();
2390
2391 /* for static cmos like DaVinci, register values were preserved
2392 * unless for some reason the whole soc powered down or the USB
2393 * module got reset through the PSC (vs just being disabled).
2394 */
2395 return 0;
2396 }
2397
2398 static struct dev_pm_ops musb_dev_pm_ops = {
2399 .suspend = musb_suspend,
2400 .resume_noirq = musb_resume_noirq,
2401 };
2402
2403 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2404 #else
2405 #define MUSB_DEV_PM_OPS NULL
2406 #endif
2407
2408 static struct platform_driver musb_driver = {
2409 .driver = {
2410 .name = (char *)musb_driver_name,
2411 .bus = &platform_bus_type,
2412 .owner = THIS_MODULE,
2413 .pm = MUSB_DEV_PM_OPS,
2414 },
2415 .remove = __devexit_p(musb_remove),
2416 .shutdown = musb_shutdown,
2417 };
2418
2419 /*-------------------------------------------------------------------------*/
2420
2421 static int __init musb_init(void)
2422 {
2423 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2424 if (usb_disabled())
2425 return 0;
2426 #endif
2427
2428 pr_info("%s: version " MUSB_VERSION ", "
2429 #ifdef CONFIG_MUSB_PIO_ONLY
2430 "pio"
2431 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2432 "cppi-dma"
2433 #elif defined(CONFIG_USB_TI_CPPI41_DMA)
2434 "cppi4.1-dma"
2435 #elif defined(CONFIG_USB_INVENTRA_DMA)
2436 "musb-dma"
2437 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2438 "tusb-omap-dma"
2439 #else
2440 "?dma?"
2441 #endif
2442 ", "
2443 #ifdef CONFIG_USB_MUSB_OTG
2444 "otg (peripheral+host)"
2445 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2446 "peripheral"
2447 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2448 "host"
2449 #endif
2450 ", debug=%d\n",
2451 musb_driver_name, musb_debug);
2452 return platform_driver_probe(&musb_driver, musb_probe);
2453 }
2454
2455 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2456 * and before usb gadget and host-side drivers start to register
2457 */
2458 fs_initcall(musb_init);
2459
2460 static void __exit musb_cleanup(void)
2461 {
2462 platform_driver_unregister(&musb_driver);
2463 }
2464 module_exit(musb_cleanup);
Linux for Ginger Game Console