drivers/usb/musb/musbhsdma.c

   1 /*
   2  * MUSB OTG driver - support for Mentor's DMA controller
   3  *
   4  * Copyright 2005 Mentor Graphics Corporation
   5  * Copyright (C) 2005-2007 by Texas Instruments
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * version 2 as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  19  * 02110-1301 USA
  20  *
  21  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  22  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  24  * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  27  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  28  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  */
  33 #include <linux/device.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/platform_device.h>
  36 #include "musb_core.h"
  37 #include "musbhsdma.h"
  38 #include <plat/dma.h>
  39
  40 static int dma_controller_start(struct dma_controller *c)
  41 {
  42         /* nothing to do */
  43         return 0;
  44 }
  45
  46 static void musb_sysdma_completion(int lch, u16 ch_status, void *data)
  47 {
  48         u32 addr;
  49         unsigned long flags;
  50
  51         struct dma_channel *channel;
  52
  53         struct musb_dma_channel *musb_channel =
  54                                         (struct musb_dma_channel *) data;
  55         struct musb_dma_controller *controller = musb_channel->controller;
  56         struct musb *musb = controller->private_data;
  57         channel = &musb_channel->channel;
  58
  59         DBG(2, "lch = 0x%d, ch_status = 0x%x\n", lch, ch_status);
  60         spin_lock_irqsave(&musb->lock, flags);
  61
  62         addr = (u32) omap_get_dma_dst_pos(musb_channel->sysdma_channel);
  63         if (musb_channel->len == 0)
  64                 channel->actual_len = 0;
  65         else
  66                 channel->actual_len = addr - musb_channel->start_addr;
  67
  68         DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n",
  69                 channel, musb_channel->start_addr, addr,
  70                 channel->actual_len, musb_channel->len,
  71                 (channel->actual_len < musb_channel->len) ?
  72                 "=> reconfig 0 " : " => complete");
  73
  74         channel->status = MUSB_DMA_STATUS_FREE;
  75         musb_dma_completion(musb, musb_channel->epnum, musb_channel->transmit);
  76
  77         spin_unlock_irqrestore(&musb->lock, flags);
  78         return;
  79 }
  80
  81 static void dma_channel_release(struct dma_channel *channel);
  82
  83 static int dma_controller_stop(struct dma_controller *c)
  84 {
  85         struct musb_dma_controller *controller = container_of(c,
  86                         struct musb_dma_controller, controller);
  87         struct musb *musb = controller->private_data;
  88         struct dma_channel *channel;
  89         u8 bit;
  90
  91         if (controller->used_channels != 0) {
  92                 dev_err(musb->controller,
  93                         "Stopping DMA controller while channel active\n");
  94
  95                 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
  96                         if (controller->used_channels & (1 << bit)) {
  97                                 channel = &controller->channel[bit].channel;
  98                                 dma_channel_release(channel);
  99
 100                                 if (!controller->used_channels)
 101                                         break;
 102                         }
 103                 }
 104         }
 105
 106         return 0;
 107 }
 108
 109 static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
 110                                 struct musb_hw_ep *hw_ep, u8 transmit)
 111 {
 112         struct musb_dma_controller *controller = container_of(c,
 113                         struct musb_dma_controller, controller);
 114         struct musb_dma_channel *musb_channel = NULL;
 115         struct dma_channel *channel = NULL;
 116         u8 bit;
 117
 118         for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
 119                 if (!(controller->used_channels & (1 << bit))) {
 120                         controller->used_channels |= (1 << bit);
 121                         musb_channel = &(controller->channel[bit]);
 122                         musb_channel->controller = controller;
 123                         musb_channel->idx = bit;
 124                         musb_channel->epnum = hw_ep->epnum;
 125                         musb_channel->transmit = transmit;
 126                         channel = &(musb_channel->channel);
 127                         channel->private_data = musb_channel;
 128                         channel->status = MUSB_DMA_STATUS_FREE;
 129                         channel->max_len = 0x10000;
 130                         /* Tx => mode 1; Rx => mode 0 */
 131                         channel->desired_mode = transmit;
 132                         channel->actual_len = 0;
 133                         musb_channel->sysdma_channel = -1;
 134
 135                         if (!transmit && use_system_dma()) {
 136                                 int ret;
 137                                 ret = omap_request_dma(OMAP24XX_DMA_NO_DEVICE,
 138                                         "MUSB SysDMA", musb_sysdma_completion,
 139                                         (void *) musb_channel,
 140                                         &(musb_channel->sysdma_channel));
 141
 142                                 if (ret) {
 143                                         printk(KERN_ERR "request_dma failed:"
 144                                                         " %d\n", ret);
 145                                         controller->used_channels &=
 146                                                                 ~(1 << bit);
 147                                         channel->status =
 148                                                         MUSB_DMA_STATUS_UNKNOWN;
 149                                         musb_channel->sysdma_channel = -1;
 150                                         channel = NULL;
 151                                 }
 152                         }
 153                         break;
 154                 }
 155         }
 156
 157         return channel;
 158 }
 159
 160 static void dma_channel_release(struct dma_channel *channel)
 161 {
 162         struct musb_dma_channel *musb_channel = channel->private_data;
 163
 164         channel->actual_len = 0;
 165         musb_channel->start_addr = 0;
 166         musb_channel->len = 0;
 167
 168         musb_channel->controller->used_channels &=
 169                 ~(1 << musb_channel->idx);
 170
 171         channel->status = MUSB_DMA_STATUS_UNKNOWN;
 172
 173         if (musb_channel->sysdma_channel != -1) {
 174                 omap_stop_dma(musb_channel->sysdma_channel);
 175                 omap_free_dma(musb_channel->sysdma_channel);
 176                 musb_channel->sysdma_channel = -1;
 177         }
 178 }
 179
 180 static void configure_channel(struct dma_channel *channel,
 181                                 u16 packet_sz, u8 mode,
 182                                 dma_addr_t dma_addr, u32 len)
 183 {
 184         struct musb_dma_channel *musb_channel = channel->private_data;
 185         struct musb_dma_controller *controller = musb_channel->controller;
 186         void __iomem *mbase = controller->base;
 187         u8 bchannel = musb_channel->idx;
 188         u16 csr = 0;
 189
 190         DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
 191                         channel, packet_sz, dma_addr, len, mode);
 192         if (musb_channel->sysdma_channel != -1) {
 193                 /* System DMA */
 194                 /* RX: set src = FIFO */
 195                 omap_set_dma_transfer_params(musb_channel->sysdma_channel,
 196                                         OMAP_DMA_DATA_TYPE_S8,
 197                                         len ? len : 1, 1, /* One frame */
 198                                         OMAP_DMA_SYNC_ELEMENT,
 199                                         OMAP24XX_DMA_NO_DEVICE,
 200                                         0); /* Src Sync */
 201
 202                 omap_set_dma_src_params(musb_channel->sysdma_channel, 0,
 203                                         OMAP_DMA_AMODE_CONSTANT,
 204                                         MUSB_FIFO_ADDRESS(musb_channel->epnum),
 205                                         0, 0);
 206
 207                 omap_set_dma_dest_params(musb_channel->sysdma_channel, 0,
 208                                         OMAP_DMA_AMODE_POST_INC, dma_addr,
 209                                         0, 0);
 210
 211                 omap_set_dma_dest_data_pack(musb_channel->sysdma_channel, 1);
 212                 omap_set_dma_dest_burst_mode(musb_channel->sysdma_channel,
 213                                         OMAP_DMA_DATA_BURST_16);
 214
 215                 omap_start_dma(musb_channel->sysdma_channel);
 216
 217         } else { /* Mentor DMA */
 218
 219         if (mode) {
 220                 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
 221                 BUG_ON(len < packet_sz);
 222
 223                 if (packet_sz >= 64) {
 224                         csr |= MUSB_HSDMA_BURSTMODE_INCR16
 225                                         << MUSB_HSDMA_BURSTMODE_SHIFT;
 226                 } else if (packet_sz >= 32) {
 227                         csr |= MUSB_HSDMA_BURSTMODE_INCR8
 228                                         << MUSB_HSDMA_BURSTMODE_SHIFT;
 229                 } else if (packet_sz >= 16) {
 230                         csr |= MUSB_HSDMA_BURSTMODE_INCR4
 231                                         << MUSB_HSDMA_BURSTMODE_SHIFT;
 232                 }
 233         }
 234
 235         csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
 236                 | (1 << MUSB_HSDMA_ENABLE_SHIFT)
 237                 | (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
 238                 | (musb_channel->transmit
 239                                 ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
 240                                 : 0);
 241
 242         /* address/count */
 243         musb_write_hsdma_addr(mbase, bchannel, dma_addr);
 244         musb_write_hsdma_count(mbase, bchannel, len);
 245
 246         /* control (this should start things) */
 247         musb_writew(mbase,
 248                 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
 249                 csr);
 250         }
 251 }
 252
 253 static int dma_channel_program(struct dma_channel *channel,
 254                                 u16 packet_sz, u8 mode,
 255                                 dma_addr_t dma_addr, u32 len)
 256 {
 257         struct musb_dma_channel *musb_channel = channel->private_data;
 258
 259         DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
 260                 musb_channel->epnum,
 261                 musb_channel->transmit ? "Tx" : "Rx",
 262                 packet_sz, dma_addr, len, mode);
 263
 264         BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
 265                 channel->status == MUSB_DMA_STATUS_BUSY);
 266
 267         channel->actual_len = 0;
 268         musb_channel->start_addr = dma_addr;
 269         musb_channel->len = len;
 270         musb_channel->max_packet_sz = packet_sz;
 271         channel->status = MUSB_DMA_STATUS_BUSY;
 272
 273         if ((mode == 1) && (len >= packet_sz))
 274                 configure_channel(channel, packet_sz, 1, dma_addr, len);
 275         else
 276                 configure_channel(channel, packet_sz, 0, dma_addr, len);
 277
 278         return true;
 279 }
 280
 281 static int dma_channel_abort(struct dma_channel *channel)
 282 {
 283         struct musb_dma_channel *musb_channel = channel->private_data;
 284         void __iomem *mbase = musb_channel->controller->base;
 285
 286         u8 bchannel = musb_channel->idx;
 287         int offset;
 288         u16 csr;
 289
 290         if (channel->status == MUSB_DMA_STATUS_BUSY) {
 291                 if (musb_channel->transmit) {
 292                         offset = MUSB_EP_OFFSET(musb_channel->epnum,
 293                                                 MUSB_TXCSR);
 294
 295                         /*
 296                          * The programming guide says that we must clear
 297                          * the DMAENAB bit before the DMAMODE bit...
 298                          */
 299                         csr = musb_readw(mbase, offset);
 300                         csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
 301                         musb_writew(mbase, offset, csr);
 302                         csr &= ~MUSB_TXCSR_DMAMODE;
 303                         musb_writew(mbase, offset, csr);
 304                 } else {
 305                         if (musb_channel->sysdma_channel != -1)
 306                                 omap_stop_dma(musb_channel->sysdma_channel);
 307
 308                         offset = MUSB_EP_OFFSET(musb_channel->epnum,
 309                                                 MUSB_RXCSR);
 310
 311                         csr = musb_readw(mbase, offset);
 312                         csr &= ~(MUSB_RXCSR_AUTOCLEAR |
 313                                  MUSB_RXCSR_DMAENAB |
 314                                  MUSB_RXCSR_DMAMODE);
 315                         musb_writew(mbase, offset, csr);
 316                 }
 317
 318                 musb_writew(mbase,
 319                         MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
 320                         0);
 321                 musb_write_hsdma_addr(mbase, bchannel, 0);
 322                 musb_write_hsdma_count(mbase, bchannel, 0);
 323                 channel->status = MUSB_DMA_STATUS_FREE;
 324         }
 325
 326         return 0;
 327 }
 328
 329 static irqreturn_t dma_controller_irq(int irq, void *private_data)
 330 {
 331         struct musb_dma_controller *controller = private_data;
 332         struct musb *musb = controller->private_data;
 333         struct musb_dma_channel *musb_channel;
 334         struct dma_channel *channel;
 335
 336         void __iomem *mbase = controller->base;
 337
 338         irqreturn_t retval = IRQ_NONE;
 339
 340         unsigned long flags;
 341
 342         u8 bchannel;
 343         u8 int_hsdma;
 344
 345         u32 addr;
 346         u16 csr;
 347
 348         spin_lock_irqsave(&musb->lock, flags);
 349
 350         int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
 351         if (!int_hsdma)
 352                 goto done;
 353
 354         for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
 355                 if (int_hsdma & (1 << bchannel)) {
 356                         musb_channel = (struct musb_dma_channel *)
 357                                         &(controller->channel[bchannel]);
 358                         channel = &musb_channel->channel;
 359
 360                         csr = musb_readw(mbase,
 361                                         MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
 362                                                         MUSB_HSDMA_CONTROL));
 363
 364                         if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
 365                                 musb_channel->channel.status =
 366                                         MUSB_DMA_STATUS_BUS_ABORT;
 367                         } else {
 368                                 u8 devctl;
 369
 370                                 addr = musb_read_hsdma_addr(mbase,
 371                                                 bchannel);
 372                                 channel->actual_len = addr
 373                                         - musb_channel->start_addr;
 374
 375                                 DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n",
 376                                         channel, musb_channel->start_addr,
 377                                         addr, channel->actual_len,
 378                                         musb_channel->len,
 379                                         (channel->actual_len
 380                                                 < musb_channel->len) ?
 381                                         "=> reconfig 0" : "=> complete");
 382
 383                                 devctl = musb_readb(mbase, MUSB_DEVCTL);
 384
 385                                 channel->status = MUSB_DMA_STATUS_FREE;
 386
 387                                 /* completed */
 388                                 if ((devctl & MUSB_DEVCTL_HM)
 389                                         && (musb_channel->transmit)
 390                                         && ((channel->desired_mode == 0)
 391                                             || (channel->actual_len &
 392                                             (musb_channel->max_packet_sz - 1)))
 393                                     ) {
 394                                         u8  epnum  = musb_channel->epnum;
 395                                         int offset = MUSB_EP_OFFSET(epnum,
 396                                                                     MUSB_TXCSR);
 397                                         u16 txcsr;
 398
 399                                         /*
 400                                          * The programming guide says that we
 401                                          * must clear DMAENAB before DMAMODE.
 402                                          */
 403                                         musb_ep_select(mbase, epnum);
 404                                         txcsr = musb_readw(mbase, offset);
 405                                         txcsr &= ~(MUSB_TXCSR_DMAENAB
 406                                                         | MUSB_TXCSR_AUTOSET);
 407                                         musb_writew(mbase, offset, txcsr);
 408                                         /* Send out the packet */
 409                                         txcsr &= ~MUSB_TXCSR_DMAMODE;
 410                                         txcsr |=  MUSB_TXCSR_TXPKTRDY;
 411                                         musb_writew(mbase, offset, txcsr);
 412                                 }
 413                                 musb_dma_completion(musb, musb_channel->epnum,
 414                                                     musb_channel->transmit);
 415                         }
 416                 }
 417         }
 418
 419 #ifdef CONFIG_BLACKFIN
 420         /* Clear DMA interrup flags */
 421         musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
 422 #endif
 423
 424         retval = IRQ_HANDLED;
 425 done:
 426         spin_unlock_irqrestore(&musb->lock, flags);
 427         return retval;
 428 }
 429
 430 void dma_controller_destroy(struct dma_controller *c)
 431 {
 432         struct musb_dma_controller *controller = container_of(c,
 433                         struct musb_dma_controller, controller);
 434
 435         if (!controller)
 436                 return;
 437
 438         if (controller->irq)
 439                 free_irq(controller->irq, c);
 440
 441         kfree(controller);
 442 }
 443
 444 struct dma_controller *__init
 445 dma_controller_create(struct musb *musb, void __iomem *base)
 446 {
 447         struct musb_dma_controller *controller;
 448         struct device *dev = musb->controller;
 449         struct platform_device *pdev = to_platform_device(dev);
 450         int irq = platform_get_irq(pdev, 1);
 451
 452         if (irq == 0) {
 453                 dev_err(dev, "No DMA interrupt line!\n");
 454                 return NULL;
 455         }
 456
 457         controller = kzalloc(sizeof(*controller), GFP_KERNEL);
 458         if (!controller)
 459                 return NULL;
 460
 461         controller->channel_count = MUSB_HSDMA_CHANNELS;
 462         controller->private_data = musb;
 463         controller->base = base;
 464
 465         controller->controller.start = dma_controller_start;
 466         controller->controller.stop = dma_controller_stop;
 467         controller->controller.channel_alloc = dma_channel_allocate;
 468         controller->controller.channel_release = dma_channel_release;
 469         controller->controller.channel_program = dma_channel_program;
 470         controller->controller.channel_abort = dma_channel_abort;
 471
 472         if (request_irq(irq, dma_controller_irq, IRQF_DISABLED,
 473                         dev_name(musb->controller), &controller->controller)) {
 474                 dev_err(dev, "request_irq %d failed!\n", irq);
 475                 dma_controller_destroy(&controller->controller);
 476
 477                 return NULL;
 478         }
 479
 480         controller->irq = irq;
 481
 482         return &controller->controller;
 483 }