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Full support for Ginger Console
[linux-ginger.git] / drivers / video / omap2 / dss / dsi.c
blobce93a22c191ae0c10361ca3ee98d995fc9015416
1 /*
2 * linux/drivers/video/omap2/dss/dsi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #define DSS_SUBSYS_NAME "DSI"
21
22 #include <linux/kernel.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/seq_file.h>
31 #include <linux/platform_device.h>
32 #include <linux/regulator/consumer.h>
33 #include <linux/kthread.h>
34 #include <linux/wait.h>
35
36 #include <plat/display.h>
37 #include <plat/clock.h>
38
39 #include "dss.h"
40
41 /*#define VERBOSE_IRQ*/
42 #define DSI_CATCH_MISSING_TE
43
44 #define DSI_BASE 0x4804FC00
45
46 struct dsi_reg { u16 idx; };
47
48 #define DSI_REG(idx) ((const struct dsi_reg) { idx })
49
50 #define DSI_SZ_REGS SZ_1K
51 /* DSI Protocol Engine */
52
53 #define DSI_REVISION DSI_REG(0x0000)
54 #define DSI_SYSCONFIG DSI_REG(0x0010)
55 #define DSI_SYSSTATUS DSI_REG(0x0014)
56 #define DSI_IRQSTATUS DSI_REG(0x0018)
57 #define DSI_IRQENABLE DSI_REG(0x001C)
58 #define DSI_CTRL DSI_REG(0x0040)
59 #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
60 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
61 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
62 #define DSI_CLK_CTRL DSI_REG(0x0054)
63 #define DSI_TIMING1 DSI_REG(0x0058)
64 #define DSI_TIMING2 DSI_REG(0x005C)
65 #define DSI_VM_TIMING1 DSI_REG(0x0060)
66 #define DSI_VM_TIMING2 DSI_REG(0x0064)
67 #define DSI_VM_TIMING3 DSI_REG(0x0068)
68 #define DSI_CLK_TIMING DSI_REG(0x006C)
69 #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
70 #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
71 #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
72 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
73 #define DSI_VM_TIMING4 DSI_REG(0x0080)
74 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
75 #define DSI_VM_TIMING5 DSI_REG(0x0088)
76 #define DSI_VM_TIMING6 DSI_REG(0x008C)
77 #define DSI_VM_TIMING7 DSI_REG(0x0090)
78 #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
79 #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
80 #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
81 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
82 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
83 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
84 #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
85 #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
86
87 /* DSIPHY_SCP */
88
89 #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
90 #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
91 #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
92 #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
93
94 /* DSI_PLL_CTRL_SCP */
95
96 #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
97 #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
98 #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
99 #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
100 #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
101
102 #define REG_GET(idx, start, end) \
103 FLD_GET(dsi_read_reg(idx), start, end)
104
105 #define REG_FLD_MOD(idx, val, start, end) \
106 dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
107
108 /* Global interrupts */
109 #define DSI_IRQ_VC0 (1 << 0)
110 #define DSI_IRQ_VC1 (1 << 1)
111 #define DSI_IRQ_VC2 (1 << 2)
112 #define DSI_IRQ_VC3 (1 << 3)
113 #define DSI_IRQ_WAKEUP (1 << 4)
114 #define DSI_IRQ_RESYNC (1 << 5)
115 #define DSI_IRQ_PLL_LOCK (1 << 7)
116 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
117 #define DSI_IRQ_PLL_RECALL (1 << 9)
118 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
119 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
120 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
121 #define DSI_IRQ_TE_TRIGGER (1 << 16)
122 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
123 #define DSI_IRQ_SYNC_LOST (1 << 18)
124 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
125 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
126 #define DSI_IRQ_ERROR_MASK \
127 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
128 DSI_IRQ_TA_TIMEOUT)
129 #define DSI_IRQ_CHANNEL_MASK 0xf
130
131 /* Virtual channel interrupts */
132 #define DSI_VC_IRQ_CS (1 << 0)
133 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
134 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
135 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
136 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
137 #define DSI_VC_IRQ_BTA (1 << 5)
138 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
139 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
140 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
141 #define DSI_VC_IRQ_ERROR_MASK \
142 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
143 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
144 DSI_VC_IRQ_FIFO_TX_UDF)
145
146 /* ComplexIO interrupts */
147 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
148 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
149 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
150 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
151 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
152 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
153 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
154 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
155 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
156 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
157 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
158 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
159 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
160 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
161 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
162 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
163 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
164 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
165 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
166 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
167
168 #define DSI_DT_DCS_SHORT_WRITE_0 0x05
169 #define DSI_DT_DCS_SHORT_WRITE_1 0x15
170 #define DSI_DT_DCS_READ 0x06
171 #define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37
172 #define DSI_DT_NULL_PACKET 0x09
173 #define DSI_DT_DCS_LONG_WRITE 0x39
174
175 #define DSI_DT_RX_ACK_WITH_ERR 0x02
176 #define DSI_DT_RX_DCS_LONG_READ 0x1c
177 #define DSI_DT_RX_SHORT_READ_1 0x21
178 #define DSI_DT_RX_SHORT_READ_2 0x22
179
180 #define FINT_MAX 2100000
181 #define FINT_MIN 750000
182 #define REGN_MAX (1 << 7)
183 #define REGM_MAX ((1 << 11) - 1)
184 #define REGM3_MAX (1 << 4)
185 #define REGM4_MAX (1 << 4)
186 #define LP_DIV_MAX ((1 << 13) - 1)
187
188 enum fifo_size {
189 DSI_FIFO_SIZE_0 = 0,
190 DSI_FIFO_SIZE_32 = 1,
191 DSI_FIFO_SIZE_64 = 2,
192 DSI_FIFO_SIZE_96 = 3,
193 DSI_FIFO_SIZE_128 = 4,
194 };
195
196 enum dsi_vc_mode {
197 DSI_VC_MODE_L4 = 0,
198 DSI_VC_MODE_VP,
199 };
200
201 struct dsi_update_region {
202 bool dirty;
203 u16 x, y, w, h;
204 struct omap_dss_device *device;
205 };
206
207 static struct
208 {
209 void __iomem *base;
210
211 struct dsi_clock_info current_cinfo;
212
213 struct regulator *vdds_dsi_reg;
214
215 struct {
216 enum dsi_vc_mode mode;
217 struct omap_dss_device *dssdev;
218 enum fifo_size fifo_size;
219 int dest_per; /* destination peripheral 0-3 */
220 } vc[4];
221
222 struct mutex lock;
223 struct mutex bus_lock;
224
225 unsigned pll_locked;
226
227 struct completion bta_completion;
228
229 struct task_struct *thread;
230 wait_queue_head_t waitqueue;
231
232 spinlock_t update_lock;
233 bool framedone_received;
234 struct dsi_update_region update_region;
235 struct dsi_update_region active_update_region;
236 struct completion update_completion;
237
238 enum omap_dss_update_mode user_update_mode;
239 enum omap_dss_update_mode update_mode;
240 bool te_enabled;
241 bool use_ext_te;
242
243 #ifdef DSI_CATCH_MISSING_TE
244 struct timer_list te_timer;
245 #endif
246
247 unsigned long cache_req_pck;
248 unsigned long cache_clk_freq;
249 struct dsi_clock_info cache_cinfo;
250
251 u32 errors;
252 spinlock_t errors_lock;
253 #ifdef DEBUG
254 ktime_t perf_setup_time;
255 ktime_t perf_start_time;
256 ktime_t perf_start_time_auto;
257 int perf_measure_frames;
258 #endif
259 int debug_read;
260 int debug_write;
261 } dsi;
262
263 #ifdef DEBUG
264 static unsigned int dsi_perf;
265 module_param_named(dsi_perf, dsi_perf, bool, 0644);
266 #endif
267
268 static inline void dsi_write_reg(const struct dsi_reg idx, u32 val)
269 {
270 __raw_writel(val, dsi.base + idx.idx);
271 }
272
273 static inline u32 dsi_read_reg(const struct dsi_reg idx)
274 {
275 return __raw_readl(dsi.base + idx.idx);
276 }
277
278
279 void dsi_save_context(void)
280 {
281 }
282
283 void dsi_restore_context(void)
284 {
285 }
286
287 void dsi_bus_lock(void)
288 {
289 mutex_lock(&dsi.bus_lock);
290 }
291 EXPORT_SYMBOL(dsi_bus_lock);
292
293 void dsi_bus_unlock(void)
294 {
295 mutex_unlock(&dsi.bus_lock);
296 }
297 EXPORT_SYMBOL(dsi_bus_unlock);
298
299 static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
300 int value)
301 {
302 int t = 100000;
303
304 while (REG_GET(idx, bitnum, bitnum) != value) {
305 if (--t == 0)
306 return !value;
307 }
308
309 return value;
310 }
311
312 #ifdef DEBUG
313 static void dsi_perf_mark_setup(void)
314 {
315 dsi.perf_setup_time = ktime_get();
316 }
317
318 static void dsi_perf_mark_start(void)
319 {
320 dsi.perf_start_time = ktime_get();
321 }
322
323 static void dsi_perf_mark_start_auto(void)
324 {
325 dsi.perf_measure_frames = 0;
326 dsi.perf_start_time_auto = ktime_get();
327 }
328
329 static void dsi_perf_show(const char *name)
330 {
331 ktime_t t, setup_time, trans_time;
332 u32 total_bytes;
333 u32 setup_us, trans_us, total_us;
334
335 if (!dsi_perf)
336 return;
337
338 if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED)
339 return;
340
341 t = ktime_get();
342
343 setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time);
344 setup_us = (u32)ktime_to_us(setup_time);
345 if (setup_us == 0)
346 setup_us = 1;
347
348 trans_time = ktime_sub(t, dsi.perf_start_time);
349 trans_us = (u32)ktime_to_us(trans_time);
350 if (trans_us == 0)
351 trans_us = 1;
352
353 total_us = setup_us + trans_us;
354
355 total_bytes = dsi.active_update_region.w *
356 dsi.active_update_region.h *
357 dsi.active_update_region.device->ctrl.pixel_size / 8;
358
359 if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) {
360 static u32 s_total_trans_us, s_total_setup_us;
361 static u32 s_min_trans_us = 0xffffffff, s_min_setup_us;
362 static u32 s_max_trans_us, s_max_setup_us;
363 const int numframes = 100;
364 ktime_t total_time_auto;
365 u32 total_time_auto_us;
366
367 dsi.perf_measure_frames++;
368
369 if (setup_us < s_min_setup_us)
370 s_min_setup_us = setup_us;
371
372 if (setup_us > s_max_setup_us)
373 s_max_setup_us = setup_us;
374
375 s_total_setup_us += setup_us;
376
377 if (trans_us < s_min_trans_us)
378 s_min_trans_us = trans_us;
379
380 if (trans_us > s_max_trans_us)
381 s_max_trans_us = trans_us;
382
383 s_total_trans_us += trans_us;
384
385 if (dsi.perf_measure_frames < numframes)
386 return;
387
388 total_time_auto = ktime_sub(t, dsi.perf_start_time_auto);
389 total_time_auto_us = (u32)ktime_to_us(total_time_auto);
390
391 printk(KERN_INFO "DSI(%s): %u fps, setup %u/%u/%u, "
392 "trans %u/%u/%u\n",
393 name,
394 1000 * 1000 * numframes / total_time_auto_us,
395 s_min_setup_us,
396 s_max_setup_us,
397 s_total_setup_us / numframes,
398 s_min_trans_us,
399 s_max_trans_us,
400 s_total_trans_us / numframes);
401
402 s_total_setup_us = 0;
403 s_min_setup_us = 0xffffffff;
404 s_max_setup_us = 0;
405 s_total_trans_us = 0;
406 s_min_trans_us = 0xffffffff;
407 s_max_trans_us = 0;
408 dsi_perf_mark_start_auto();
409 } else {
410 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
411 "%u bytes, %u kbytes/sec\n",
412 name,
413 setup_us,
414 trans_us,
415 total_us,
416 1000*1000 / total_us,
417 total_bytes,
418 total_bytes * 1000 / total_us);
419 }
420 }
421 #else
422 #define dsi_perf_mark_setup()
423 #define dsi_perf_mark_start()
424 #define dsi_perf_mark_start_auto()
425 #define dsi_perf_show(x)
426 #endif
427
428 static void print_irq_status(u32 status)
429 {
430 #ifndef VERBOSE_IRQ
431 if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
432 return;
433 #endif
434 printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
435
436 #define PIS(x) \
437 if (status & DSI_IRQ_##x) \
438 printk(#x " ");
439 #ifdef VERBOSE_IRQ
440 PIS(VC0);
441 PIS(VC1);
442 PIS(VC2);
443 PIS(VC3);
444 #endif
445 PIS(WAKEUP);
446 PIS(RESYNC);
447 PIS(PLL_LOCK);
448 PIS(PLL_UNLOCK);
449 PIS(PLL_RECALL);
450 PIS(COMPLEXIO_ERR);
451 PIS(HS_TX_TIMEOUT);
452 PIS(LP_RX_TIMEOUT);
453 PIS(TE_TRIGGER);
454 PIS(ACK_TRIGGER);
455 PIS(SYNC_LOST);
456 PIS(LDO_POWER_GOOD);
457 PIS(TA_TIMEOUT);
458 #undef PIS
459
460 printk("\n");
461 }
462
463 static void print_irq_status_vc(int channel, u32 status)
464 {
465 #ifndef VERBOSE_IRQ
466 if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
467 return;
468 #endif
469 printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
470
471 #define PIS(x) \
472 if (status & DSI_VC_IRQ_##x) \
473 printk(#x " ");
474 PIS(CS);
475 PIS(ECC_CORR);
476 #ifdef VERBOSE_IRQ
477 PIS(PACKET_SENT);
478 #endif
479 PIS(FIFO_TX_OVF);
480 PIS(FIFO_RX_OVF);
481 PIS(BTA);
482 PIS(ECC_NO_CORR);
483 PIS(FIFO_TX_UDF);
484 PIS(PP_BUSY_CHANGE);
485 #undef PIS
486 printk("\n");
487 }
488
489 static void print_irq_status_cio(u32 status)
490 {
491 printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
492
493 #define PIS(x) \
494 if (status & DSI_CIO_IRQ_##x) \
495 printk(#x " ");
496 PIS(ERRSYNCESC1);
497 PIS(ERRSYNCESC2);
498 PIS(ERRSYNCESC3);
499 PIS(ERRESC1);
500 PIS(ERRESC2);
501 PIS(ERRESC3);
502 PIS(ERRCONTROL1);
503 PIS(ERRCONTROL2);
504 PIS(ERRCONTROL3);
505 PIS(STATEULPS1);
506 PIS(STATEULPS2);
507 PIS(STATEULPS3);
508 PIS(ERRCONTENTIONLP0_1);
509 PIS(ERRCONTENTIONLP1_1);
510 PIS(ERRCONTENTIONLP0_2);
511 PIS(ERRCONTENTIONLP1_2);
512 PIS(ERRCONTENTIONLP0_3);
513 PIS(ERRCONTENTIONLP1_3);
514 PIS(ULPSACTIVENOT_ALL0);
515 PIS(ULPSACTIVENOT_ALL1);
516 #undef PIS
517
518 printk("\n");
519 }
520
521 static int debug_irq;
522
523 /* called from dss */
524 void dsi_irq_handler(void)
525 {
526 u32 irqstatus, vcstatus, ciostatus;
527 int i;
528
529 irqstatus = dsi_read_reg(DSI_IRQSTATUS);
530
531 if (irqstatus & DSI_IRQ_ERROR_MASK) {
532 DSSERR("DSI error, irqstatus %x\n", irqstatus);
533 print_irq_status(irqstatus);
534 spin_lock(&dsi.errors_lock);
535 dsi.errors |= irqstatus & DSI_IRQ_ERROR_MASK;
536 spin_unlock(&dsi.errors_lock);
537 } else if (debug_irq) {
538 print_irq_status(irqstatus);
539 }
540
541 #ifdef DSI_CATCH_MISSING_TE
542 if (irqstatus & DSI_IRQ_TE_TRIGGER)
543 del_timer(&dsi.te_timer);
544 #endif
545
546 for (i = 0; i < 4; ++i) {
547 if ((irqstatus & (1<<i)) == 0)
548 continue;
549
550 vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i));
551
552 if (vcstatus & DSI_VC_IRQ_BTA)
553 complete(&dsi.bta_completion);
554
555 if (vcstatus & DSI_VC_IRQ_ERROR_MASK) {
556 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
557 i, vcstatus);
558 print_irq_status_vc(i, vcstatus);
559 } else if (debug_irq) {
560 print_irq_status_vc(i, vcstatus);
561 }
562
563 dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus);
564 /* flush posted write */
565 dsi_read_reg(DSI_VC_IRQSTATUS(i));
566 }
567
568 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
569 ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
570
571 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
572 /* flush posted write */
573 dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
574
575 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
576 print_irq_status_cio(ciostatus);
577 }
578
579 dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
580 /* flush posted write */
581 dsi_read_reg(DSI_IRQSTATUS);
582 }
583
584
585 static void _dsi_initialize_irq(void)
586 {
587 u32 l;
588 int i;
589
590 /* disable all interrupts */
591 dsi_write_reg(DSI_IRQENABLE, 0);
592 for (i = 0; i < 4; ++i)
593 dsi_write_reg(DSI_VC_IRQENABLE(i), 0);
594 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0);
595
596 /* clear interrupt status */
597 l = dsi_read_reg(DSI_IRQSTATUS);
598 dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK);
599
600 for (i = 0; i < 4; ++i) {
601 l = dsi_read_reg(DSI_VC_IRQSTATUS(i));
602 dsi_write_reg(DSI_VC_IRQSTATUS(i), l);
603 }
604
605 l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
606 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l);
607
608 /* enable error irqs */
609 l = DSI_IRQ_ERROR_MASK;
610 #ifdef DSI_CATCH_MISSING_TE
611 l |= DSI_IRQ_TE_TRIGGER;
612 #endif
613 dsi_write_reg(DSI_IRQENABLE, l);
614
615 l = DSI_VC_IRQ_ERROR_MASK;
616 for (i = 0; i < 4; ++i)
617 dsi_write_reg(DSI_VC_IRQENABLE(i), l);
618
619 /* XXX zonda responds incorrectly, causing control error:
620 Exit from LP-ESC mode to LP11 uses wrong transition states on the
621 data lines LP0 and LN0. */
622 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE,
623 -1 & (~DSI_CIO_IRQ_ERRCONTROL2));
624 }
625
626 static u32 dsi_get_errors(void)
627 {
628 unsigned long flags;
629 u32 e;
630 spin_lock_irqsave(&dsi.errors_lock, flags);
631 e = dsi.errors;
632 dsi.errors = 0;
633 spin_unlock_irqrestore(&dsi.errors_lock, flags);
634 return e;
635 }
636
637 static void dsi_vc_enable_bta_irq(int channel)
638 {
639 u32 l;
640
641 dsi_write_reg(DSI_VC_IRQSTATUS(channel), DSI_VC_IRQ_BTA);
642
643 l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
644 l |= DSI_VC_IRQ_BTA;
645 dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
646 }
647
648 static void dsi_vc_disable_bta_irq(int channel)
649 {
650 u32 l;
651
652 l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
653 l &= ~DSI_VC_IRQ_BTA;
654 dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
655 }
656
657 /* DSI func clock. this could also be DSI2_PLL_FCLK */
658 static inline void enable_clocks(bool enable)
659 {
660 if (enable)
661 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
662 else
663 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
664 }
665
666 /* source clock for DSI PLL. this could also be PCLKFREE */
667 static inline void dsi_enable_pll_clock(bool enable)
668 {
669 if (enable)
670 dss_clk_enable(DSS_CLK_FCK2);
671 else
672 dss_clk_disable(DSS_CLK_FCK2);
673
674 if (enable && dsi.pll_locked) {
675 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
676 DSSERR("cannot lock PLL when enabling clocks\n");
677 }
678 }
679
680 #ifdef DEBUG
681 static void _dsi_print_reset_status(void)
682 {
683 u32 l;
684
685 if (!dss_debug)
686 return;
687
688 /* A dummy read using the SCP interface to any DSIPHY register is
689 * required after DSIPHY reset to complete the reset of the DSI complex
690 * I/O. */
691 l = dsi_read_reg(DSI_DSIPHY_CFG5);
692
693 printk(KERN_DEBUG "DSI resets: ");
694
695 l = dsi_read_reg(DSI_PLL_STATUS);
696 printk("PLL (%d) ", FLD_GET(l, 0, 0));
697
698 l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
699 printk("CIO (%d) ", FLD_GET(l, 29, 29));
700
701 l = dsi_read_reg(DSI_DSIPHY_CFG5);
702 printk("PHY (%x, %d, %d, %d)\n",
703 FLD_GET(l, 28, 26),
704 FLD_GET(l, 29, 29),
705 FLD_GET(l, 30, 30),
706 FLD_GET(l, 31, 31));
707 }
708 #else
709 #define _dsi_print_reset_status()
710 #endif
711
712 static inline int dsi_if_enable(bool enable)
713 {
714 DSSDBG("dsi_if_enable(%d)\n", enable);
715
716 enable = enable ? 1 : 0;
717 REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
718
719 if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
720 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
721 return -EIO;
722 }
723
724 return 0;
725 }
726
727 unsigned long dsi_get_dsi1_pll_rate(void)
728 {
729 return dsi.current_cinfo.dsi1_pll_fclk;
730 }
731
732 static unsigned long dsi_get_dsi2_pll_rate(void)
733 {
734 return dsi.current_cinfo.dsi2_pll_fclk;
735 }
736
737 static unsigned long dsi_get_txbyteclkhs(void)
738 {
739 return dsi.current_cinfo.clkin4ddr / 16;
740 }
741
742 static unsigned long dsi_fclk_rate(void)
743 {
744 unsigned long r;
745
746 if (dss_get_dsi_clk_source() == 0) {
747 /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
748 r = dss_clk_get_rate(DSS_CLK_FCK1);
749 } else {
750 /* DSI FCLK source is DSI2_PLL_FCLK */
751 r = dsi_get_dsi2_pll_rate();
752 }
753
754 return r;
755 }
756
757 static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
758 {
759 unsigned long dsi_fclk;
760 unsigned lp_clk_div;
761 unsigned long lp_clk;
762
763 lp_clk_div = dssdev->phy.dsi.div.lp_clk_div;
764
765 if (lp_clk_div == 0 || lp_clk_div > LP_DIV_MAX)
766 return -EINVAL;
767
768 dsi_fclk = dsi_fclk_rate();
769
770 lp_clk = dsi_fclk / 2 / lp_clk_div;
771
772 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
773 dsi.current_cinfo.lp_clk = lp_clk;
774 dsi.current_cinfo.lp_clk_div = lp_clk_div;
775
776 REG_FLD_MOD(DSI_CLK_CTRL, lp_clk_div, 12, 0); /* LP_CLK_DIVISOR */
777
778 REG_FLD_MOD(DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0,
779 21, 21); /* LP_RX_SYNCHRO_ENABLE */
780
781 return 0;
782 }
783
784
785 enum dsi_pll_power_state {
786 DSI_PLL_POWER_OFF = 0x0,
787 DSI_PLL_POWER_ON_HSCLK = 0x1,
788 DSI_PLL_POWER_ON_ALL = 0x2,
789 DSI_PLL_POWER_ON_DIV = 0x3,
790 };
791
792 static int dsi_pll_power(enum dsi_pll_power_state state)
793 {
794 int t = 0;
795
796 REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */
797
798 /* PLL_PWR_STATUS */
799 while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
800 udelay(1);
801 if (t++ > 1000) {
802 DSSERR("Failed to set DSI PLL power mode to %d\n",
803 state);
804 return -ENODEV;
805 }
806 }
807
808 return 0;
809 }
810
811 /* calculate clock rates using dividers in cinfo */
812 static int dsi_calc_clock_rates(struct dsi_clock_info *cinfo)
813 {
814 if (cinfo->regn == 0 || cinfo->regn > REGN_MAX)
815 return -EINVAL;
816
817 if (cinfo->regm == 0 || cinfo->regm > REGM_MAX)
818 return -EINVAL;
819
820 if (cinfo->regm3 > REGM3_MAX)
821 return -EINVAL;
822
823 if (cinfo->regm4 > REGM4_MAX)
824 return -EINVAL;
825
826 if (cinfo->use_dss2_fck) {
827 cinfo->clkin = dss_clk_get_rate(DSS_CLK_FCK2);
828 /* XXX it is unclear if highfreq should be used
829 * with DSS2_FCK source also */
830 cinfo->highfreq = 0;
831 } else {
832 cinfo->clkin = dispc_pclk_rate();
833
834 if (cinfo->clkin < 32000000)
835 cinfo->highfreq = 0;
836 else
837 cinfo->highfreq = 1;
838 }
839
840 cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
841
842 if (cinfo->fint > FINT_MAX || cinfo->fint < FINT_MIN)
843 return -EINVAL;
844
845 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
846
847 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
848 return -EINVAL;
849
850 if (cinfo->regm3 > 0)
851 cinfo->dsi1_pll_fclk = cinfo->clkin4ddr / cinfo->regm3;
852 else
853 cinfo->dsi1_pll_fclk = 0;
854
855 if (cinfo->regm4 > 0)
856 cinfo->dsi2_pll_fclk = cinfo->clkin4ddr / cinfo->regm4;
857 else
858 cinfo->dsi2_pll_fclk = 0;
859
860 return 0;
861 }
862
863 int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
864 struct dsi_clock_info *dsi_cinfo,
865 struct dispc_clock_info *dispc_cinfo)
866 {
867 struct dsi_clock_info cur, best;
868 struct dispc_clock_info best_dispc;
869 int min_fck_per_pck;
870 int match = 0;
871 unsigned long dss_clk_fck2;
872
873 dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_FCK2);
874
875 if (req_pck == dsi.cache_req_pck &&
876 dsi.cache_cinfo.clkin == dss_clk_fck2) {
877 DSSDBG("DSI clock info found from cache\n");
878 *dsi_cinfo = dsi.cache_cinfo;
879 return 0;
880 }
881
882 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
883
884 if (min_fck_per_pck &&
885 req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
886 DSSERR("Requested pixel clock not possible with the current "
887 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
888 "the constraint off.\n");
889 min_fck_per_pck = 0;
890 }
891
892 DSSDBG("dsi_pll_calc\n");
893
894 retry:
895 memset(&best, 0, sizeof(best));
896 memset(&best_dispc, 0, sizeof(best_dispc));
897
898 memset(&cur, 0, sizeof(cur));
899 cur.clkin = dss_clk_fck2;
900 cur.use_dss2_fck = 1;
901 cur.highfreq = 0;
902
903 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
904 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
905 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
906 for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
907 if (cur.highfreq == 0)
908 cur.fint = cur.clkin / cur.regn;
909 else
910 cur.fint = cur.clkin / (2 * cur.regn);
911
912 if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
913 continue;
914
915 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
916 for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
917 unsigned long a, b;
918
919 a = 2 * cur.regm * (cur.clkin/1000);
920 b = cur.regn * (cur.highfreq + 1);
921 cur.clkin4ddr = a / b * 1000;
922
923 if (cur.clkin4ddr > 1800 * 1000 * 1000)
924 break;
925
926 /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */
927 for (cur.regm3 = 1; cur.regm3 < REGM3_MAX;
928 ++cur.regm3) {
929 struct dispc_clock_info cur_dispc;
930 cur.dsi1_pll_fclk = cur.clkin4ddr / cur.regm3;
931
932 /* this will narrow down the search a bit,
933 * but still give pixclocks below what was
934 * requested */
935 if (cur.dsi1_pll_fclk < req_pck)
936 break;
937
938 if (cur.dsi1_pll_fclk > DISPC_MAX_FCK)
939 continue;
940
941 if (min_fck_per_pck &&
942 cur.dsi1_pll_fclk <
943 req_pck * min_fck_per_pck)
944 continue;
945
946 match = 1;
947
948 dispc_find_clk_divs(is_tft, req_pck,
949 cur.dsi1_pll_fclk,
950 &cur_dispc);
951
952 if (abs(cur_dispc.pck - req_pck) <
953 abs(best_dispc.pck - req_pck)) {
954 best = cur;
955 best_dispc = cur_dispc;
956
957 if (cur_dispc.pck == req_pck)
958 goto found;
959 }
960 }
961 }
962 }
963 found:
964 if (!match) {
965 if (min_fck_per_pck) {
966 DSSERR("Could not find suitable clock settings.\n"
967 "Turning FCK/PCK constraint off and"
968 "trying again.\n");
969 min_fck_per_pck = 0;
970 goto retry;
971 }
972
973 DSSERR("Could not find suitable clock settings.\n");
974
975 return -EINVAL;
976 }
977
978 /* DSI2_PLL_FCLK (regm4) is not used */
979 best.regm4 = 0;
980 best.dsi2_pll_fclk = 0;
981
982 if (dsi_cinfo)
983 *dsi_cinfo = best;
984 if (dispc_cinfo)
985 *dispc_cinfo = best_dispc;
986
987 dsi.cache_req_pck = req_pck;
988 dsi.cache_clk_freq = 0;
989 dsi.cache_cinfo = best;
990
991 return 0;
992 }
993
994 int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
995 {
996 int r = 0;
997 u32 l;
998 int f;
999
1000 DSSDBGF();
1001
1002 dsi.current_cinfo.fint = cinfo->fint;
1003 dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1004 dsi.current_cinfo.dsi1_pll_fclk = cinfo->dsi1_pll_fclk;
1005 dsi.current_cinfo.dsi2_pll_fclk = cinfo->dsi2_pll_fclk;
1006
1007 dsi.current_cinfo.regn = cinfo->regn;
1008 dsi.current_cinfo.regm = cinfo->regm;
1009 dsi.current_cinfo.regm3 = cinfo->regm3;
1010 dsi.current_cinfo.regm4 = cinfo->regm4;
1011
1012 DSSDBG("DSI Fint %ld\n", cinfo->fint);
1013
1014 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
1015 cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree",
1016 cinfo->clkin,
1017 cinfo->highfreq);
1018
1019 /* DSIPHY == CLKIN4DDR */
1020 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
1021 cinfo->regm,
1022 cinfo->regn,
1023 cinfo->clkin,
1024 cinfo->highfreq + 1,
1025 cinfo->clkin4ddr);
1026
1027 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1028 cinfo->clkin4ddr / 1000 / 1000 / 2);
1029
1030 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1031
1032 DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
1033 cinfo->regm3, cinfo->dsi1_pll_fclk);
1034 DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
1035 cinfo->regm4, cinfo->dsi2_pll_fclk);
1036
1037 REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
1038
1039 l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
1040 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1041 l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */
1042 l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */
1043 l = FLD_MOD(l, cinfo->regm3 > 0 ? cinfo->regm3 - 1 : 0,
1044 22, 19); /* DSI_CLOCK_DIV */
1045 l = FLD_MOD(l, cinfo->regm4 > 0 ? cinfo->regm4 - 1 : 0,
1046 26, 23); /* DSIPROTO_CLOCK_DIV */
1047 dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
1048
1049 BUG_ON(cinfo->fint < 750000 || cinfo->fint > 2100000);
1050 if (cinfo->fint < 1000000)
1051 f = 0x3;
1052 else if (cinfo->fint < 1250000)
1053 f = 0x4;
1054 else if (cinfo->fint < 1500000)
1055 f = 0x5;
1056 else if (cinfo->fint < 1750000)
1057 f = 0x6;
1058 else
1059 f = 0x7;
1060
1061 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1062 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1063 l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1,
1064 11, 11); /* DSI_PLL_CLKSEL */
1065 l = FLD_MOD(l, cinfo->highfreq,
1066 12, 12); /* DSI_PLL_HIGHFREQ */
1067 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1068 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1069 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1070 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1071
1072 REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1073
1074 if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
1075 DSSERR("dsi pll go bit not going down.\n");
1076 r = -EIO;
1077 goto err;
1078 }
1079
1080 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
1081 DSSERR("cannot lock PLL\n");
1082 r = -EIO;
1083 goto err;
1084 }
1085
1086 dsi.pll_locked = 1;
1087
1088 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1089 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1090 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1091 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1092 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1093 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1094 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1095 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1096 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1097 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1098 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1099 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1100 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1101 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1102 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1103 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1104
1105 DSSDBG("PLL config done\n");
1106 err:
1107 return r;
1108 }
1109
1110 int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
1111 bool enable_hsdiv)
1112 {
1113 int r = 0;
1114 enum dsi_pll_power_state pwstate;
1115
1116 DSSDBG("PLL init\n");
1117
1118 enable_clocks(1);
1119 dsi_enable_pll_clock(1);
1120
1121 r = regulator_enable(dsi.vdds_dsi_reg);
1122 if (r)
1123 goto err0;
1124
1125 /* XXX PLL does not come out of reset without this... */
1126 dispc_pck_free_enable(1);
1127
1128 if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
1129 DSSERR("PLL not coming out of reset.\n");
1130 r = -ENODEV;
1131 goto err1;
1132 }
1133
1134 /* XXX ... but if left on, we get problems when planes do not
1135 * fill the whole display. No idea about this */
1136 dispc_pck_free_enable(0);
1137
1138 if (enable_hsclk && enable_hsdiv)
1139 pwstate = DSI_PLL_POWER_ON_ALL;
1140 else if (enable_hsclk)
1141 pwstate = DSI_PLL_POWER_ON_HSCLK;
1142 else if (enable_hsdiv)
1143 pwstate = DSI_PLL_POWER_ON_DIV;
1144 else
1145 pwstate = DSI_PLL_POWER_OFF;
1146
1147 r = dsi_pll_power(pwstate);
1148
1149 if (r)
1150 goto err1;
1151
1152 DSSDBG("PLL init done\n");
1153
1154 return 0;
1155 err1:
1156 regulator_disable(dsi.vdds_dsi_reg);
1157 err0:
1158 enable_clocks(0);
1159 dsi_enable_pll_clock(0);
1160 return r;
1161 }
1162
1163 void dsi_pll_uninit(void)
1164 {
1165 enable_clocks(0);
1166 dsi_enable_pll_clock(0);
1167
1168 dsi.pll_locked = 0;
1169 dsi_pll_power(DSI_PLL_POWER_OFF);
1170 regulator_disable(dsi.vdds_dsi_reg);
1171 DSSDBG("PLL uninit done\n");
1172 }
1173
1174 void dsi_dump_clocks(struct seq_file *s)
1175 {
1176 int clksel;
1177 struct dsi_clock_info *cinfo = &dsi.current_cinfo;
1178
1179 enable_clocks(1);
1180
1181 clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);
1182
1183 seq_printf(s, "- DSI PLL -\n");
1184
1185 seq_printf(s, "dsi pll source = %s\n",
1186 clksel == 0 ?
1187 "dss2_alwon_fclk" : "pclkfree");
1188
1189 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1190
1191 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1192 cinfo->clkin4ddr, cinfo->regm);
1193
1194 seq_printf(s, "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n",
1195 cinfo->dsi1_pll_fclk,
1196 cinfo->regm3,
1197 dss_get_dispc_clk_source() == 0 ? "off" : "on");
1198
1199 seq_printf(s, "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n",
1200 cinfo->dsi2_pll_fclk,
1201 cinfo->regm4,
1202 dss_get_dsi_clk_source() == 0 ? "off" : "on");
1203
1204 seq_printf(s, "- DSI -\n");
1205
1206 seq_printf(s, "dsi fclk source = %s\n",
1207 dss_get_dsi_clk_source() == 0 ?
1208 "dss1_alwon_fclk" : "dsi2_pll_fclk");
1209
1210 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate());
1211
1212 seq_printf(s, "DDR_CLK\t\t%lu\n",
1213 cinfo->clkin4ddr / 4);
1214
1215 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs());
1216
1217 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1218
1219 seq_printf(s, "VP_CLK\t\t%lu\n"
1220 "VP_PCLK\t\t%lu\n",
1221 dispc_lclk_rate(),
1222 dispc_pclk_rate());
1223
1224 enable_clocks(0);
1225 }
1226
1227 void dsi_dump_regs(struct seq_file *s)
1228 {
1229 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
1230
1231 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
1232
1233 DUMPREG(DSI_REVISION);
1234 DUMPREG(DSI_SYSCONFIG);
1235 DUMPREG(DSI_SYSSTATUS);
1236 DUMPREG(DSI_IRQSTATUS);
1237 DUMPREG(DSI_IRQENABLE);
1238 DUMPREG(DSI_CTRL);
1239 DUMPREG(DSI_COMPLEXIO_CFG1);
1240 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1241 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1242 DUMPREG(DSI_CLK_CTRL);
1243 DUMPREG(DSI_TIMING1);
1244 DUMPREG(DSI_TIMING2);
1245 DUMPREG(DSI_VM_TIMING1);
1246 DUMPREG(DSI_VM_TIMING2);
1247 DUMPREG(DSI_VM_TIMING3);
1248 DUMPREG(DSI_CLK_TIMING);
1249 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1250 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1251 DUMPREG(DSI_COMPLEXIO_CFG2);
1252 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1253 DUMPREG(DSI_VM_TIMING4);
1254 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1255 DUMPREG(DSI_VM_TIMING5);
1256 DUMPREG(DSI_VM_TIMING6);
1257 DUMPREG(DSI_VM_TIMING7);
1258 DUMPREG(DSI_STOPCLK_TIMING);
1259
1260 DUMPREG(DSI_VC_CTRL(0));
1261 DUMPREG(DSI_VC_TE(0));
1262 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1263 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1264 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1265 DUMPREG(DSI_VC_IRQSTATUS(0));
1266 DUMPREG(DSI_VC_IRQENABLE(0));
1267
1268 DUMPREG(DSI_VC_CTRL(1));
1269 DUMPREG(DSI_VC_TE(1));
1270 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1271 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1272 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1273 DUMPREG(DSI_VC_IRQSTATUS(1));
1274 DUMPREG(DSI_VC_IRQENABLE(1));
1275
1276 DUMPREG(DSI_VC_CTRL(2));
1277 DUMPREG(DSI_VC_TE(2));
1278 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1279 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1280 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1281 DUMPREG(DSI_VC_IRQSTATUS(2));
1282 DUMPREG(DSI_VC_IRQENABLE(2));
1283
1284 DUMPREG(DSI_VC_CTRL(3));
1285 DUMPREG(DSI_VC_TE(3));
1286 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1287 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1288 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1289 DUMPREG(DSI_VC_IRQSTATUS(3));
1290 DUMPREG(DSI_VC_IRQENABLE(3));
1291
1292 DUMPREG(DSI_DSIPHY_CFG0);
1293 DUMPREG(DSI_DSIPHY_CFG1);
1294 DUMPREG(DSI_DSIPHY_CFG2);
1295 DUMPREG(DSI_DSIPHY_CFG5);
1296
1297 DUMPREG(DSI_PLL_CONTROL);
1298 DUMPREG(DSI_PLL_STATUS);
1299 DUMPREG(DSI_PLL_GO);
1300 DUMPREG(DSI_PLL_CONFIGURATION1);
1301 DUMPREG(DSI_PLL_CONFIGURATION2);
1302
1303 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
1304 #undef DUMPREG
1305 }
1306
1307 enum dsi_complexio_power_state {
1308 DSI_COMPLEXIO_POWER_OFF = 0x0,
1309 DSI_COMPLEXIO_POWER_ON = 0x1,
1310 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1311 };
1312
1313 static int dsi_complexio_power(enum dsi_complexio_power_state state)
1314 {
1315 int t = 0;
1316
1317 /* PWR_CMD */
1318 REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
1319
1320 /* PWR_STATUS */
1321 while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
1322 udelay(1);
1323 if (t++ > 1000) {
1324 DSSERR("failed to set complexio power state to "
1325 "%d\n", state);
1326 return -ENODEV;
1327 }
1328 }
1329
1330 return 0;
1331 }
1332
1333 static void dsi_complexio_config(struct omap_dss_device *dssdev)
1334 {
1335 u32 r;
1336
1337 int clk_lane = dssdev->phy.dsi.clk_lane;
1338 int data1_lane = dssdev->phy.dsi.data1_lane;
1339 int data2_lane = dssdev->phy.dsi.data2_lane;
1340 int clk_pol = dssdev->phy.dsi.clk_pol;
1341 int data1_pol = dssdev->phy.dsi.data1_pol;
1342 int data2_pol = dssdev->phy.dsi.data2_pol;
1343
1344 r = dsi_read_reg(DSI_COMPLEXIO_CFG1);
1345 r = FLD_MOD(r, clk_lane, 2, 0);
1346 r = FLD_MOD(r, clk_pol, 3, 3);
1347 r = FLD_MOD(r, data1_lane, 6, 4);
1348 r = FLD_MOD(r, data1_pol, 7, 7);
1349 r = FLD_MOD(r, data2_lane, 10, 8);
1350 r = FLD_MOD(r, data2_pol, 11, 11);
1351 dsi_write_reg(DSI_COMPLEXIO_CFG1, r);
1352
1353 /* The configuration of the DSI complex I/O (number of data lanes,
1354 position, differential order) should not be changed while
1355 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
1356 the hardware to take into account a new configuration of the complex
1357 I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
1358 follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
1359 then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
1360 DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
1361 DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
1362 DSI complex I/O configuration is unknown. */
1363
1364 /*
1365 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1366 REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
1367 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
1368 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1369 */
1370 }
1371
1372 static inline unsigned ns2ddr(unsigned ns)
1373 {
1374 /* convert time in ns to ddr ticks, rounding up */
1375 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1376 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1377 }
1378
1379 static inline unsigned ddr2ns(unsigned ddr)
1380 {
1381 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1382 return ddr * 1000 * 1000 / (ddr_clk / 1000);
1383 }
1384
1385 static void dsi_complexio_timings(void)
1386 {
1387 u32 r;
1388 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1389 u32 tlpx_half, tclk_trail, tclk_zero;
1390 u32 tclk_prepare;
1391
1392 /* calculate timings */
1393
1394 /* 1 * DDR_CLK = 2 * UI */
1395
1396 /* min 40ns + 4*UI max 85ns + 6*UI */
1397 ths_prepare = ns2ddr(70) + 2;
1398
1399 /* min 145ns + 10*UI */
1400 ths_prepare_ths_zero = ns2ddr(175) + 2;
1401
1402 /* min max(8*UI, 60ns+4*UI) */
1403 ths_trail = ns2ddr(60) + 5;
1404
1405 /* min 100ns */
1406 ths_exit = ns2ddr(145);
1407
1408 /* tlpx min 50n */
1409 tlpx_half = ns2ddr(25);
1410
1411 /* min 60ns */
1412 tclk_trail = ns2ddr(60) + 2;
1413
1414 /* min 38ns, max 95ns */
1415 tclk_prepare = ns2ddr(65);
1416
1417 /* min tclk-prepare + tclk-zero = 300ns */
1418 tclk_zero = ns2ddr(260);
1419
1420 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1421 ths_prepare, ddr2ns(ths_prepare),
1422 ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero));
1423 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1424 ths_trail, ddr2ns(ths_trail),
1425 ths_exit, ddr2ns(ths_exit));
1426
1427 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1428 "tclk_zero %u (%uns)\n",
1429 tlpx_half, ddr2ns(tlpx_half),
1430 tclk_trail, ddr2ns(tclk_trail),
1431 tclk_zero, ddr2ns(tclk_zero));
1432 DSSDBG("tclk_prepare %u (%uns)\n",
1433 tclk_prepare, ddr2ns(tclk_prepare));
1434
1435 /* program timings */
1436
1437 r = dsi_read_reg(DSI_DSIPHY_CFG0);
1438 r = FLD_MOD(r, ths_prepare, 31, 24);
1439 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1440 r = FLD_MOD(r, ths_trail, 15, 8);
1441 r = FLD_MOD(r, ths_exit, 7, 0);
1442 dsi_write_reg(DSI_DSIPHY_CFG0, r);
1443
1444 r = dsi_read_reg(DSI_DSIPHY_CFG1);
1445 r = FLD_MOD(r, tlpx_half, 22, 16);
1446 r = FLD_MOD(r, tclk_trail, 15, 8);
1447 r = FLD_MOD(r, tclk_zero, 7, 0);
1448 dsi_write_reg(DSI_DSIPHY_CFG1, r);
1449
1450 r = dsi_read_reg(DSI_DSIPHY_CFG2);
1451 r = FLD_MOD(r, tclk_prepare, 7, 0);
1452 dsi_write_reg(DSI_DSIPHY_CFG2, r);
1453 }
1454
1455
1456 static int dsi_complexio_init(struct omap_dss_device *dssdev)
1457 {
1458 int r = 0;
1459
1460 DSSDBG("dsi_complexio_init\n");
1461
1462 /* CIO_CLK_ICG, enable L3 clk to CIO */
1463 REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
1464
1465 /* A dummy read using the SCP interface to any DSIPHY register is
1466 * required after DSIPHY reset to complete the reset of the DSI complex
1467 * I/O. */
1468 dsi_read_reg(DSI_DSIPHY_CFG5);
1469
1470 if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) {
1471 DSSERR("ComplexIO PHY not coming out of reset.\n");
1472 r = -ENODEV;
1473 goto err;
1474 }
1475
1476 dsi_complexio_config(dssdev);
1477
1478 r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON);
1479
1480 if (r)
1481 goto err;
1482
1483 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
1484 DSSERR("ComplexIO not coming out of reset.\n");
1485 r = -ENODEV;
1486 goto err;
1487 }
1488
1489 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
1490 DSSERR("ComplexIO LDO power down.\n");
1491 r = -ENODEV;
1492 goto err;
1493 }
1494
1495 dsi_complexio_timings();
1496
1497 /*
1498 The configuration of the DSI complex I/O (number of data lanes,
1499 position, differential order) should not be changed while
1500 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
1501 hardware to recognize a new configuration of the complex I/O (done
1502 in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
1503 this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
1504 reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
1505 LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
1506 bit to 1. If the sequence is not followed, the DSi complex I/O
1507 configuration is undetermined.
1508 */
1509 dsi_if_enable(1);
1510 dsi_if_enable(0);
1511 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
1512 dsi_if_enable(1);
1513 dsi_if_enable(0);
1514
1515 DSSDBG("CIO init done\n");
1516 err:
1517 return r;
1518 }
1519
1520 static void dsi_complexio_uninit(void)
1521 {
1522 dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF);
1523 }
1524
1525 static int _dsi_wait_reset(void)
1526 {
1527 int i = 0;
1528
1529 while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) {
1530 if (i++ > 5) {
1531 DSSERR("soft reset failed\n");
1532 return -ENODEV;
1533 }
1534 udelay(1);
1535 }
1536
1537 return 0;
1538 }
1539
1540 static int _dsi_reset(void)
1541 {
1542 /* Soft reset */
1543 REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
1544 return _dsi_wait_reset();
1545 }
1546
1547 static void dsi_reset_tx_fifo(int channel)
1548 {
1549 u32 mask;
1550 u32 l;
1551
1552 /* set fifosize of the channel to 0, then return the old size */
1553 l = dsi_read_reg(DSI_TX_FIFO_VC_SIZE);
1554
1555 mask = FLD_MASK((8 * channel) + 7, (8 * channel) + 4);
1556 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l & ~mask);
1557
1558 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l);
1559 }
1560
1561 static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
1562 enum fifo_size size3, enum fifo_size size4)
1563 {
1564 u32 r = 0;
1565 int add = 0;
1566 int i;
1567
1568 dsi.vc[0].fifo_size = size1;
1569 dsi.vc[1].fifo_size = size2;
1570 dsi.vc[2].fifo_size = size3;
1571 dsi.vc[3].fifo_size = size4;
1572
1573 for (i = 0; i < 4; i++) {
1574 u8 v;
1575 int size = dsi.vc[i].fifo_size;
1576
1577 if (add + size > 4) {
1578 DSSERR("Illegal FIFO configuration\n");
1579 BUG();
1580 }
1581
1582 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
1583 r |= v << (8 * i);
1584 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
1585 add += size;
1586 }
1587
1588 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r);
1589 }
1590
1591 static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
1592 enum fifo_size size3, enum fifo_size size4)
1593 {
1594 u32 r = 0;
1595 int add = 0;
1596 int i;
1597
1598 dsi.vc[0].fifo_size = size1;
1599 dsi.vc[1].fifo_size = size2;
1600 dsi.vc[2].fifo_size = size3;
1601 dsi.vc[3].fifo_size = size4;
1602
1603 for (i = 0; i < 4; i++) {
1604 u8 v;
1605 int size = dsi.vc[i].fifo_size;
1606
1607 if (add + size > 4) {
1608 DSSERR("Illegal FIFO configuration\n");
1609 BUG();
1610 }
1611
1612 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
1613 r |= v << (8 * i);
1614 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
1615 add += size;
1616 }
1617
1618 dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
1619 }
1620
1621 static int dsi_force_tx_stop_mode_io(void)
1622 {
1623 u32 r;
1624
1625 r = dsi_read_reg(DSI_TIMING1);
1626 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
1627 dsi_write_reg(DSI_TIMING1, r);
1628
1629 if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
1630 DSSERR("TX_STOP bit not going down\n");
1631 return -EIO;
1632 }
1633
1634 return 0;
1635 }
1636
1637 static void dsi_vc_print_status(int channel)
1638 {
1639 u32 r;
1640
1641 r = dsi_read_reg(DSI_VC_CTRL(channel));
1642 DSSDBG("vc %d: TX_FIFO_NOT_EMPTY %d, BTA_EN %d, VC_BUSY %d, "
1643 "TX_FIFO_FULL %d, RX_FIFO_NOT_EMPTY %d, ",
1644 channel,
1645 FLD_GET(r, 5, 5),
1646 FLD_GET(r, 6, 6),
1647 FLD_GET(r, 15, 15),
1648 FLD_GET(r, 16, 16),
1649 FLD_GET(r, 20, 20));
1650
1651 r = dsi_read_reg(DSI_TX_FIFO_VC_EMPTINESS);
1652 DSSDBG("EMPTINESS %d\n", (r >> (8 * channel)) & 0xff);
1653 }
1654
1655 static int dsi_vc_enable(int channel, bool enable)
1656 {
1657 if (dsi.update_mode != OMAP_DSS_UPDATE_AUTO)
1658 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
1659 channel, enable);
1660
1661 enable = enable ? 1 : 0;
1662
1663 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
1664
1665 if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
1666 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
1667 return -EIO;
1668 }
1669
1670 return 0;
1671 }
1672
1673 static void dsi_vc_initial_config(int channel)
1674 {
1675 u32 r;
1676
1677 DSSDBGF("%d", channel);
1678
1679 r = dsi_read_reg(DSI_VC_CTRL(channel));
1680
1681 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
1682 DSSERR("VC(%d) busy when trying to configure it!\n",
1683 channel);
1684
1685 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
1686 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
1687 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
1688 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
1689 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
1690 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
1691 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
1692
1693 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
1694 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
1695
1696 dsi_write_reg(DSI_VC_CTRL(channel), r);
1697
1698 dsi.vc[channel].mode = DSI_VC_MODE_L4;
1699 }
1700
1701 static void dsi_vc_config_l4(int channel)
1702 {
1703 if (dsi.vc[channel].mode == DSI_VC_MODE_L4)
1704 return;
1705
1706 DSSDBGF("%d", channel);
1707
1708 dsi_vc_enable(channel, 0);
1709
1710 if (REG_GET(DSI_VC_CTRL(channel), 15, 15)) /* VC_BUSY */
1711 DSSERR("vc(%d) busy when trying to config for L4\n", channel);
1712
1713 REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */
1714
1715 dsi_vc_enable(channel, 1);
1716
1717 dsi.vc[channel].mode = DSI_VC_MODE_L4;
1718 }
1719
1720 static void dsi_vc_config_vp(int channel)
1721 {
1722 if (dsi.vc[channel].mode == DSI_VC_MODE_VP)
1723 return;
1724
1725 DSSDBGF("%d", channel);
1726
1727 dsi_vc_enable(channel, 0);
1728
1729 if (REG_GET(DSI_VC_CTRL(channel), 15, 15)) /* VC_BUSY */
1730 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
1731
1732 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */
1733
1734 dsi_vc_enable(channel, 1);
1735
1736 dsi.vc[channel].mode = DSI_VC_MODE_VP;
1737 }
1738
1739
1740 static void dsi_vc_enable_hs(int channel, bool enable)
1741 {
1742 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
1743
1744 dsi_vc_enable(channel, 0);
1745 dsi_if_enable(0);
1746
1747 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
1748
1749 dsi_vc_enable(channel, 1);
1750 dsi_if_enable(1);
1751
1752 dsi_force_tx_stop_mode_io();
1753 }
1754
1755 static void dsi_vc_flush_long_data(int channel)
1756 {
1757 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
1758 u32 val;
1759 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
1760 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
1761 (val >> 0) & 0xff,
1762 (val >> 8) & 0xff,
1763 (val >> 16) & 0xff,
1764 (val >> 24) & 0xff);
1765 }
1766 }
1767
1768 static void dsi_show_rx_ack_with_err(u16 err)
1769 {
1770 DSSERR("\tACK with ERROR (%#x):\n", err);
1771 if (err & (1 << 0))
1772 DSSERR("\t\tSoT Error\n");
1773 if (err & (1 << 1))
1774 DSSERR("\t\tSoT Sync Error\n");
1775 if (err & (1 << 2))
1776 DSSERR("\t\tEoT Sync Error\n");
1777 if (err & (1 << 3))
1778 DSSERR("\t\tEscape Mode Entry Command Error\n");
1779 if (err & (1 << 4))
1780 DSSERR("\t\tLP Transmit Sync Error\n");
1781 if (err & (1 << 5))
1782 DSSERR("\t\tHS Receive Timeout Error\n");
1783 if (err & (1 << 6))
1784 DSSERR("\t\tFalse Control Error\n");
1785 if (err & (1 << 7))
1786 DSSERR("\t\t(reserved7)\n");
1787 if (err & (1 << 8))
1788 DSSERR("\t\tECC Error, single-bit (corrected)\n");
1789 if (err & (1 << 9))
1790 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
1791 if (err & (1 << 10))
1792 DSSERR("\t\tChecksum Error\n");
1793 if (err & (1 << 11))
1794 DSSERR("\t\tData type not recognized\n");
1795 if (err & (1 << 12))
1796 DSSERR("\t\tInvalid VC ID\n");
1797 if (err & (1 << 13))
1798 DSSERR("\t\tInvalid Transmission Length\n");
1799 if (err & (1 << 14))
1800 DSSERR("\t\t(reserved14)\n");
1801 if (err & (1 << 15))
1802 DSSERR("\t\tDSI Protocol Violation\n");
1803 }
1804
1805 static u16 dsi_vc_flush_receive_data(int channel)
1806 {
1807 /* RX_FIFO_NOT_EMPTY */
1808 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
1809 u32 val;
1810 u8 dt;
1811 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
1812 DSSDBG("\trawval %#08x\n", val);
1813 dt = FLD_GET(val, 5, 0);
1814 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
1815 u16 err = FLD_GET(val, 23, 8);
1816 dsi_show_rx_ack_with_err(err);
1817 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
1818 DSSDBG("\tDCS short response, 1 byte: %#x\n",
1819 FLD_GET(val, 23, 8));
1820 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
1821 DSSDBG("\tDCS short response, 2 byte: %#x\n",
1822 FLD_GET(val, 23, 8));
1823 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
1824 DSSDBG("\tDCS long response, len %d\n",
1825 FLD_GET(val, 23, 8));
1826 dsi_vc_flush_long_data(channel);
1827 } else {
1828 DSSERR("\tunknown datatype 0x%02x\n", dt);
1829 }
1830 }
1831 return 0;
1832 }
1833
1834 static int dsi_vc_send_bta(int channel)
1835 {
1836 if (dsi.update_mode != OMAP_DSS_UPDATE_AUTO &&
1837 (dsi.debug_write || dsi.debug_read))
1838 DSSDBG("dsi_vc_send_bta %d\n", channel);
1839
1840 WARN_ON(!mutex_is_locked(&dsi.bus_lock));
1841
1842 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
1843 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
1844 dsi_vc_flush_receive_data(channel);
1845 }
1846
1847 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
1848
1849 return 0;
1850 }
1851
1852 int dsi_vc_send_bta_sync(int channel)
1853 {
1854 int r = 0;
1855 u32 err;
1856
1857 INIT_COMPLETION(dsi.bta_completion);
1858
1859 dsi_vc_enable_bta_irq(channel);
1860
1861 r = dsi_vc_send_bta(channel);
1862 if (r)
1863 goto err;
1864
1865 if (wait_for_completion_timeout(&dsi.bta_completion,
1866 msecs_to_jiffies(500)) == 0) {
1867 DSSERR("Failed to receive BTA\n");
1868 r = -EIO;
1869 goto err;
1870 }
1871
1872 err = dsi_get_errors();
1873 if (err) {
1874 DSSERR("Error while sending BTA: %x\n", err);
1875 r = -EIO;
1876 goto err;
1877 }
1878 err:
1879 dsi_vc_disable_bta_irq(channel);
1880
1881 return r;
1882 }
1883 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
1884
1885 static inline void dsi_vc_write_long_header(int channel, u8 data_type,
1886 u16 len, u8 ecc)
1887 {
1888 u32 val;
1889 u8 data_id;
1890
1891 WARN_ON(!mutex_is_locked(&dsi.bus_lock));
1892
1893 /*data_id = data_type | channel << 6; */
1894 data_id = data_type | dsi.vc[channel].dest_per << 6;
1895
1896 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
1897 FLD_VAL(ecc, 31, 24);
1898
1899 dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
1900 }
1901
1902 static inline void dsi_vc_write_long_payload(int channel,
1903 u8 b1, u8 b2, u8 b3, u8 b4)
1904 {
1905 u32 val;
1906
1907 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
1908
1909 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
1910 b1, b2, b3, b4, val); */
1911
1912 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
1913 }
1914
1915 static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
1916 u8 ecc)
1917 {
1918 /*u32 val; */
1919 int i;
1920 u8 *p;
1921 int r = 0;
1922 u8 b1, b2, b3, b4;
1923
1924 if (dsi.debug_write)
1925 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
1926
1927 /* len + header */
1928 if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) {
1929 DSSERR("unable to send long packet: packet too long.\n");
1930 return -EINVAL;
1931 }
1932
1933 dsi_vc_config_l4(channel);
1934
1935 dsi_vc_write_long_header(channel, data_type, len, ecc);
1936
1937 /*dsi_vc_print_status(0); */
1938
1939 p = data;
1940 for (i = 0; i < len >> 2; i++) {
1941 if (dsi.debug_write)
1942 DSSDBG("\tsending full packet %d\n", i);
1943 /*dsi_vc_print_status(0); */
1944
1945 b1 = *p++;
1946 b2 = *p++;
1947 b3 = *p++;
1948 b4 = *p++;
1949
1950 dsi_vc_write_long_payload(channel, b1, b2, b3, b4);
1951 }
1952
1953 i = len % 4;
1954 if (i) {
1955 b1 = 0; b2 = 0; b3 = 0;
1956
1957 if (dsi.debug_write)
1958 DSSDBG("\tsending remainder bytes %d\n", i);
1959
1960 switch (i) {
1961 case 3:
1962 b1 = *p++;
1963 b2 = *p++;
1964 b3 = *p++;
1965 break;
1966 case 2:
1967 b1 = *p++;
1968 b2 = *p++;
1969 break;
1970 case 1:
1971 b1 = *p++;
1972 break;
1973 }
1974
1975 dsi_vc_write_long_payload(channel, b1, b2, b3, 0);
1976 }
1977
1978 return r;
1979 }
1980
1981 static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
1982 {
1983 u32 r;
1984 u8 data_id;
1985
1986 WARN_ON(!mutex_is_locked(&dsi.bus_lock));
1987
1988 if (dsi.debug_write)
1989 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
1990 channel,
1991 data_type, data & 0xff, (data >> 8) & 0xff);
1992
1993 dsi_vc_config_l4(channel);
1994
1995 if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
1996 DSSERR("ERROR FIFO FULL, aborting transfer\n");
1997 return -EINVAL;
1998 }
1999
2000 data_id = data_type | channel << 6;
2001
2002 r = (data_id << 0) | (data << 8) | (ecc << 24);
2003
2004 dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
2005
2006 return 0;
2007 }
2008
2009 int dsi_vc_send_null(int channel)
2010 {
2011 u8 nullpkg[] = {0, 0, 0, 0};
2012 return dsi_vc_send_long(0, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
2013 }
2014 EXPORT_SYMBOL(dsi_vc_send_null);
2015
2016 int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
2017 {
2018 int r;
2019
2020 BUG_ON(len == 0);
2021
2022 if (len == 1) {
2023 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
2024 data[0], 0);
2025 } else if (len == 2) {
2026 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
2027 data[0] | (data[1] << 8), 0);
2028 } else {
2029 /* 0x39 = DCS Long Write */
2030 r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
2031 data, len, 0);
2032 }
2033
2034 return r;
2035 }
2036 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
2037
2038 int dsi_vc_dcs_write(int channel, u8 *data, int len)
2039 {
2040 int r;
2041
2042 r = dsi_vc_dcs_write_nosync(channel, data, len);
2043 if (r)
2044 return r;
2045
2046 r = dsi_vc_send_bta_sync(channel);
2047
2048 return r;
2049 }
2050 EXPORT_SYMBOL(dsi_vc_dcs_write);
2051
2052 int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
2053 {
2054 u32 val;
2055 u8 dt;
2056 int r;
2057
2058 if (dsi.debug_read)
2059 DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %u)\n", channel, dcs_cmd);
2060
2061 r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
2062 if (r)
2063 return r;
2064
2065 r = dsi_vc_send_bta_sync(channel);
2066 if (r)
2067 return r;
2068
2069 /* RX_FIFO_NOT_EMPTY */
2070 if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) {
2071 DSSERR("RX fifo empty when trying to read.\n");
2072 return -EIO;
2073 }
2074
2075 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2076 if (dsi.debug_read)
2077 DSSDBG("\theader: %08x\n", val);
2078 dt = FLD_GET(val, 5, 0);
2079 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
2080 u16 err = FLD_GET(val, 23, 8);
2081 dsi_show_rx_ack_with_err(err);
2082 return -EIO;
2083
2084 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
2085 u8 data = FLD_GET(val, 15, 8);
2086 if (dsi.debug_read)
2087 DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
2088
2089 if (buflen < 1)
2090 return -EIO;
2091
2092 buf[0] = data;
2093
2094 return 1;
2095 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
2096 u16 data = FLD_GET(val, 23, 8);
2097 if (dsi.debug_read)
2098 DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
2099
2100 if (buflen < 2)
2101 return -EIO;
2102
2103 buf[0] = data & 0xff;
2104 buf[1] = (data >> 8) & 0xff;
2105
2106 return 2;
2107 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
2108 int w;
2109 int len = FLD_GET(val, 23, 8);
2110 if (dsi.debug_read)
2111 DSSDBG("\tDCS long response, len %d\n", len);
2112
2113 if (len > buflen)
2114 return -EIO;
2115
2116 /* two byte checksum ends the packet, not included in len */
2117 for (w = 0; w < len + 2;) {
2118 int b;
2119 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2120 if (dsi.debug_read)
2121 DSSDBG("\t\t%02x %02x %02x %02x\n",
2122 (val >> 0) & 0xff,
2123 (val >> 8) & 0xff,
2124 (val >> 16) & 0xff,
2125 (val >> 24) & 0xff);
2126
2127 for (b = 0; b < 4; ++b) {
2128 if (w < len)
2129 buf[w] = (val >> (b * 8)) & 0xff;
2130 /* we discard the 2 byte checksum */
2131 ++w;
2132 }
2133 }
2134
2135 return len;
2136
2137 } else {
2138 DSSERR("\tunknown datatype 0x%02x\n", dt);
2139 return -EIO;
2140 }
2141 }
2142 EXPORT_SYMBOL(dsi_vc_dcs_read);
2143
2144
2145 int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
2146 {
2147 int r;
2148 r = dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
2149 len, 0);
2150
2151 if (r)
2152 return r;
2153
2154 r = dsi_vc_send_bta_sync(channel);
2155
2156 return r;
2157 }
2158 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
2159
2160 static void dsi_set_lp_rx_timeout(unsigned long ns)
2161 {
2162 u32 r;
2163 unsigned x4, x16;
2164 unsigned long fck;
2165 unsigned long ticks;
2166
2167 /* ticks in DSI_FCK */
2168
2169 fck = dsi_fclk_rate();
2170 ticks = (fck / 1000 / 1000) * ns / 1000;
2171 x4 = 0;
2172 x16 = 0;
2173
2174 if (ticks > 0x1fff) {
2175 ticks = (fck / 1000 / 1000) * ns / 1000 / 4;
2176 x4 = 1;
2177 x16 = 0;
2178 }
2179
2180 if (ticks > 0x1fff) {
2181 ticks = (fck / 1000 / 1000) * ns / 1000 / 16;
2182 x4 = 0;
2183 x16 = 1;
2184 }
2185
2186 if (ticks > 0x1fff) {
2187 ticks = (fck / 1000 / 1000) * ns / 1000 / (4 * 16);
2188 x4 = 1;
2189 x16 = 1;
2190 }
2191
2192 if (ticks > 0x1fff) {
2193 DSSWARN("LP_TX_TO over limit, setting it to max\n");
2194 ticks = 0x1fff;
2195 x4 = 1;
2196 x16 = 1;
2197 }
2198
2199 r = dsi_read_reg(DSI_TIMING2);
2200 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
2201 r = FLD_MOD(r, x16, 14, 14); /* LP_RX_TO_X16 */
2202 r = FLD_MOD(r, x4, 13, 13); /* LP_RX_TO_X4 */
2203 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
2204 dsi_write_reg(DSI_TIMING2, r);
2205
2206 DSSDBG("LP_RX_TO %lu ns (%#lx ticks%s%s)\n",
2207 (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
2208 (fck / 1000 / 1000),
2209 ticks, x4 ? " x4" : "", x16 ? " x16" : "");
2210 }
2211
2212 static void dsi_set_ta_timeout(unsigned long ns)
2213 {
2214 u32 r;
2215 unsigned x8, x16;
2216 unsigned long fck;
2217 unsigned long ticks;
2218
2219 /* ticks in DSI_FCK */
2220 fck = dsi_fclk_rate();
2221 ticks = (fck / 1000 / 1000) * ns / 1000;
2222 x8 = 0;
2223 x16 = 0;
2224
2225 if (ticks > 0x1fff) {
2226 ticks = (fck / 1000 / 1000) * ns / 1000 / 8;
2227 x8 = 1;
2228 x16 = 0;
2229 }
2230
2231 if (ticks > 0x1fff) {
2232 ticks = (fck / 1000 / 1000) * ns / 1000 / 16;
2233 x8 = 0;
2234 x16 = 1;
2235 }
2236
2237 if (ticks > 0x1fff) {
2238 ticks = (fck / 1000 / 1000) * ns / 1000 / (8 * 16);
2239 x8 = 1;
2240 x16 = 1;
2241 }
2242
2243 if (ticks > 0x1fff) {
2244 DSSWARN("TA_TO over limit, setting it to max\n");
2245 ticks = 0x1fff;
2246 x8 = 1;
2247 x16 = 1;
2248 }
2249
2250 r = dsi_read_reg(DSI_TIMING1);
2251 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
2252 r = FLD_MOD(r, x16, 30, 30); /* TA_TO_X16 */
2253 r = FLD_MOD(r, x8, 29, 29); /* TA_TO_X8 */
2254 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
2255 dsi_write_reg(DSI_TIMING1, r);
2256
2257 DSSDBG("TA_TO %lu ns (%#lx ticks%s%s)\n",
2258 (ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1) * 1000) /
2259 (fck / 1000 / 1000),
2260 ticks, x8 ? " x8" : "", x16 ? " x16" : "");
2261 }
2262
2263 static void dsi_set_stop_state_counter(unsigned long ns)
2264 {
2265 u32 r;
2266 unsigned x4, x16;
2267 unsigned long fck;
2268 unsigned long ticks;
2269
2270 /* ticks in DSI_FCK */
2271
2272 fck = dsi_fclk_rate();
2273 ticks = (fck / 1000 / 1000) * ns / 1000;
2274 x4 = 0;
2275 x16 = 0;
2276
2277 if (ticks > 0x1fff) {
2278 ticks = (fck / 1000 / 1000) * ns / 1000 / 4;
2279 x4 = 1;
2280 x16 = 0;
2281 }
2282
2283 if (ticks > 0x1fff) {
2284 ticks = (fck / 1000 / 1000) * ns / 1000 / 16;
2285 x4 = 0;
2286 x16 = 1;
2287 }
2288
2289 if (ticks > 0x1fff) {
2290 ticks = (fck / 1000 / 1000) * ns / 1000 / (4 * 16);
2291 x4 = 1;
2292 x16 = 1;
2293 }
2294
2295 if (ticks > 0x1fff) {
2296 DSSWARN("STOP_STATE_COUNTER_IO over limit, "
2297 "setting it to max\n");
2298 ticks = 0x1fff;
2299 x4 = 1;
2300 x16 = 1;
2301 }
2302
2303 r = dsi_read_reg(DSI_TIMING1);
2304 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2305 r = FLD_MOD(r, x16, 14, 14); /* STOP_STATE_X16_IO */
2306 r = FLD_MOD(r, x4, 13, 13); /* STOP_STATE_X4_IO */
2307 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
2308 dsi_write_reg(DSI_TIMING1, r);
2309
2310 DSSDBG("STOP_STATE_COUNTER %lu ns (%#lx ticks%s%s)\n",
2311 (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
2312 (fck / 1000 / 1000),
2313 ticks, x4 ? " x4" : "", x16 ? " x16" : "");
2314 }
2315
2316 static void dsi_set_hs_tx_timeout(unsigned long ns)
2317 {
2318 u32 r;
2319 unsigned x4, x16;
2320 unsigned long fck;
2321 unsigned long ticks;
2322
2323 /* ticks in TxByteClkHS */
2324
2325 fck = dsi_get_txbyteclkhs();
2326 ticks = (fck / 1000 / 1000) * ns / 1000;
2327 x4 = 0;
2328 x16 = 0;
2329
2330 if (ticks > 0x1fff) {
2331 ticks = (fck / 1000 / 1000) * ns / 1000 / 4;
2332 x4 = 1;
2333 x16 = 0;
2334 }
2335
2336 if (ticks > 0x1fff) {
2337 ticks = (fck / 1000 / 1000) * ns / 1000 / 16;
2338 x4 = 0;
2339 x16 = 1;
2340 }
2341
2342 if (ticks > 0x1fff) {
2343 ticks = (fck / 1000 / 1000) * ns / 1000 / (4 * 16);
2344 x4 = 1;
2345 x16 = 1;
2346 }
2347
2348 if (ticks > 0x1fff) {
2349 DSSWARN("HS_TX_TO over limit, setting it to max\n");
2350 ticks = 0x1fff;
2351 x4 = 1;
2352 x16 = 1;
2353 }
2354
2355 r = dsi_read_reg(DSI_TIMING2);
2356 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
2357 r = FLD_MOD(r, x16, 30, 30); /* HS_TX_TO_X16 */
2358 r = FLD_MOD(r, x4, 29, 29); /* HS_TX_TO_X8 (4 really) */
2359 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
2360 dsi_write_reg(DSI_TIMING2, r);
2361
2362 DSSDBG("HS_TX_TO %lu ns (%#lx ticks%s%s)\n",
2363 (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
2364 (fck / 1000 / 1000),
2365 ticks, x4 ? " x4" : "", x16 ? " x16" : "");
2366 }
2367 static int dsi_proto_config(struct omap_dss_device *dssdev)
2368 {
2369 u32 r;
2370 int buswidth = 0;
2371
2372 dsi_config_tx_fifo(DSI_FIFO_SIZE_128,
2373 DSI_FIFO_SIZE_0,
2374 DSI_FIFO_SIZE_0,
2375 DSI_FIFO_SIZE_0);
2376
2377 dsi_config_rx_fifo(DSI_FIFO_SIZE_128,
2378 DSI_FIFO_SIZE_0,
2379 DSI_FIFO_SIZE_0,
2380 DSI_FIFO_SIZE_0);
2381
2382 /* XXX what values for the timeouts? */
2383 dsi_set_stop_state_counter(1000);
2384 dsi_set_ta_timeout(6400000);
2385 dsi_set_lp_rx_timeout(48000);
2386 dsi_set_hs_tx_timeout(1000000);
2387
2388 switch (dssdev->ctrl.pixel_size) {
2389 case 16:
2390 buswidth = 0;
2391 break;
2392 case 18:
2393 buswidth = 1;
2394 break;
2395 case 24:
2396 buswidth = 2;
2397 break;
2398 default:
2399 BUG();
2400 }
2401
2402 r = dsi_read_reg(DSI_CTRL);
2403 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
2404 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
2405 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
2406 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
2407 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
2408 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
2409 r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
2410 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
2411 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
2412 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
2413 r = FLD_MOD(r, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */
2414
2415 dsi_write_reg(DSI_CTRL, r);
2416
2417 dsi_vc_initial_config(0);
2418
2419 /* set all vc targets to peripheral 0 */
2420 dsi.vc[0].dest_per = 0;
2421 dsi.vc[1].dest_per = 0;
2422 dsi.vc[2].dest_per = 0;
2423 dsi.vc[3].dest_per = 0;
2424
2425 return 0;
2426 }
2427
2428 static void dsi_proto_timings(struct omap_dss_device *dssdev)
2429 {
2430 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
2431 unsigned tclk_pre, tclk_post;
2432 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
2433 unsigned ths_trail, ths_exit;
2434 unsigned ddr_clk_pre, ddr_clk_post;
2435 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
2436 unsigned ths_eot;
2437 u32 r;
2438
2439 r = dsi_read_reg(DSI_DSIPHY_CFG0);
2440 ths_prepare = FLD_GET(r, 31, 24);
2441 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
2442 ths_zero = ths_prepare_ths_zero - ths_prepare;
2443 ths_trail = FLD_GET(r, 15, 8);
2444 ths_exit = FLD_GET(r, 7, 0);
2445
2446 r = dsi_read_reg(DSI_DSIPHY_CFG1);
2447 tlpx = FLD_GET(r, 22, 16) * 2;
2448 tclk_trail = FLD_GET(r, 15, 8);
2449 tclk_zero = FLD_GET(r, 7, 0);
2450
2451 r = dsi_read_reg(DSI_DSIPHY_CFG2);
2452 tclk_prepare = FLD_GET(r, 7, 0);
2453
2454 /* min 8*UI */
2455 tclk_pre = 20;
2456 /* min 60ns + 52*UI */
2457 tclk_post = ns2ddr(60) + 26;
2458
2459 /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
2460 if (dssdev->phy.dsi.data1_lane != 0 &&
2461 dssdev->phy.dsi.data2_lane != 0)
2462 ths_eot = 2;
2463 else
2464 ths_eot = 4;
2465
2466 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
2467 4);
2468 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
2469
2470 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
2471 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
2472
2473 r = dsi_read_reg(DSI_CLK_TIMING);
2474 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
2475 r = FLD_MOD(r, ddr_clk_post, 7, 0);
2476 dsi_write_reg(DSI_CLK_TIMING, r);
2477
2478 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
2479 ddr_clk_pre,
2480 ddr_clk_post);
2481
2482 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
2483 DIV_ROUND_UP(ths_prepare, 4) +
2484 DIV_ROUND_UP(ths_zero + 3, 4);
2485
2486 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
2487
2488 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
2489 FLD_VAL(exit_hs_mode_lat, 15, 0);
2490 dsi_write_reg(DSI_VM_TIMING7, r);
2491
2492 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
2493 enter_hs_mode_lat, exit_hs_mode_lat);
2494 }
2495
2496
2497 #define DSI_DECL_VARS \
2498 int __dsi_cb = 0; u32 __dsi_cv = 0;
2499
2500 #define DSI_FLUSH(ch) \
2501 if (__dsi_cb > 0) { \
2502 /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
2503 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
2504 __dsi_cb = __dsi_cv = 0; \
2505 }
2506
2507 #define DSI_PUSH(ch, data) \
2508 do { \
2509 __dsi_cv |= (data) << (__dsi_cb * 8); \
2510 /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
2511 if (++__dsi_cb > 3) \
2512 DSI_FLUSH(ch); \
2513 } while (0)
2514
2515 static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
2516 int x, int y, int w, int h)
2517 {
2518 /* Note: supports only 24bit colors in 32bit container */
2519 int first = 1;
2520 int fifo_stalls = 0;
2521 int max_dsi_packet_size;
2522 int max_data_per_packet;
2523 int max_pixels_per_packet;
2524 int pixels_left;
2525 int bytespp = dssdev->ctrl.pixel_size / 8;
2526 int scr_width;
2527 u32 __iomem *data;
2528 int start_offset;
2529 int horiz_inc;
2530 int current_x;
2531 struct omap_overlay *ovl;
2532
2533 debug_irq = 0;
2534
2535 DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
2536 x, y, w, h);
2537
2538 ovl = dssdev->manager->overlays[0];
2539
2540 if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
2541 return -EINVAL;
2542
2543 if (dssdev->ctrl.pixel_size != 24)
2544 return -EINVAL;
2545
2546 scr_width = ovl->info.screen_width;
2547 data = ovl->info.vaddr;
2548
2549 start_offset = scr_width * y + x;
2550 horiz_inc = scr_width - w;
2551 current_x = x;
2552
2553 /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
2554 * in fifo */
2555
2556 /* When using CPU, max long packet size is TX buffer size */
2557 max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
2558
2559 /* we seem to get better perf if we divide the tx fifo to half,
2560 and while the other half is being sent, we fill the other half
2561 max_dsi_packet_size /= 2; */
2562
2563 max_data_per_packet = max_dsi_packet_size - 4 - 1;
2564
2565 max_pixels_per_packet = max_data_per_packet / bytespp;
2566
2567 DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
2568
2569 pixels_left = w * h;
2570
2571 DSSDBG("total pixels %d\n", pixels_left);
2572
2573 data += start_offset;
2574
2575 while (pixels_left > 0) {
2576 /* 0x2c = write_memory_start */
2577 /* 0x3c = write_memory_continue */
2578 u8 dcs_cmd = first ? 0x2c : 0x3c;
2579 int pixels;
2580 DSI_DECL_VARS;
2581 first = 0;
2582
2583 #if 1
2584 /* using fifo not empty */
2585 /* TX_FIFO_NOT_EMPTY */
2586 while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
2587 udelay(1);
2588 fifo_stalls++;
2589 if (fifo_stalls > 0xfffff) {
2590 DSSERR("fifo stalls overflow, pixels left %d\n",
2591 pixels_left);
2592 dsi_if_enable(0);
2593 return -EIO;
2594 }
2595 }
2596 #elif 1
2597 /* using fifo emptiness */
2598 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
2599 max_dsi_packet_size) {
2600 fifo_stalls++;
2601 if (fifo_stalls > 0xfffff) {
2602 DSSERR("fifo stalls overflow, pixels left %d\n",
2603 pixels_left);
2604 dsi_if_enable(0);
2605 return -EIO;
2606 }
2607 }
2608 #else
2609 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {
2610 fifo_stalls++;
2611 if (fifo_stalls > 0xfffff) {
2612 DSSERR("fifo stalls overflow, pixels left %d\n",
2613 pixels_left);
2614 dsi_if_enable(0);
2615 return -EIO;
2616 }
2617 }
2618 #endif
2619 pixels = min(max_pixels_per_packet, pixels_left);
2620
2621 pixels_left -= pixels;
2622
2623 dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
2624 1 + pixels * bytespp, 0);
2625
2626 DSI_PUSH(0, dcs_cmd);
2627
2628 while (pixels-- > 0) {
2629 u32 pix = __raw_readl(data++);
2630
2631 DSI_PUSH(0, (pix >> 16) & 0xff);
2632 DSI_PUSH(0, (pix >> 8) & 0xff);
2633 DSI_PUSH(0, (pix >> 0) & 0xff);
2634
2635 current_x++;
2636 if (current_x == x+w) {
2637 current_x = x;
2638 data += horiz_inc;
2639 }
2640 }
2641
2642 DSI_FLUSH(0);
2643 }
2644
2645 return 0;
2646 }
2647
2648 static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
2649 u16 x, u16 y, u16 w, u16 h)
2650 {
2651 unsigned bytespp;
2652 unsigned bytespl;
2653 unsigned bytespf;
2654 unsigned total_len;
2655 unsigned packet_payload;
2656 unsigned packet_len;
2657 u32 l;
2658 bool use_te_trigger;
2659 const unsigned channel = 0;
2660 /* line buffer is 1024 x 24bits */
2661 /* XXX: for some reason using full buffer size causes considerable TX
2662 * slowdown with update sizes that fill the whole buffer */
2663 const unsigned line_buf_size = 1023 * 3;
2664
2665 use_te_trigger = dsi.te_enabled && !dsi.use_ext_te;
2666
2667 if (dsi.update_mode != OMAP_DSS_UPDATE_AUTO)
2668 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
2669 x, y, w, h);
2670
2671 bytespp = dssdev->ctrl.pixel_size / 8;
2672 bytespl = w * bytespp;
2673 bytespf = bytespl * h;
2674
2675 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
2676 * number of lines in a packet. See errata about VP_CLK_RATIO */
2677
2678 if (bytespf < line_buf_size)
2679 packet_payload = bytespf;
2680 else
2681 packet_payload = (line_buf_size) / bytespl * bytespl;
2682
2683 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
2684 total_len = (bytespf / packet_payload) * packet_len;
2685
2686 if (bytespf % packet_payload)
2687 total_len += (bytespf % packet_payload) + 1;
2688
2689 if (0)
2690 dsi_vc_print_status(1);
2691
2692 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
2693 dsi_write_reg(DSI_VC_TE(channel), l);
2694
2695 dsi_vc_write_long_header(channel, DSI_DT_DCS_LONG_WRITE, packet_len, 0);
2696
2697 if (use_te_trigger)
2698 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
2699 else
2700 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
2701 dsi_write_reg(DSI_VC_TE(channel), l);
2702
2703 /* We put SIDLEMODE to no-idle for the duration of the transfer,
2704 * because DSS interrupts are not capable of waking up the CPU and the
2705 * framedone interrupt could be delayed for quite a long time. I think
2706 * the same goes for any DSS interrupts, but for some reason I have not
2707 * seen the problem anywhere else than here.
2708 */
2709 dispc_disable_sidle();
2710
2711 dss_start_update(dssdev);
2712
2713 if (use_te_trigger) {
2714 /* disable LP_RX_TO, so that we can receive TE. Time to wait
2715 * for TE is longer than the timer allows */
2716 REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
2717
2718 dsi_vc_send_bta(channel);
2719
2720 #ifdef DSI_CATCH_MISSING_TE
2721 mod_timer(&dsi.te_timer, jiffies + msecs_to_jiffies(250));
2722 #endif
2723 }
2724 }
2725
2726 #ifdef DSI_CATCH_MISSING_TE
2727 static void dsi_te_timeout(unsigned long arg)
2728 {
2729 DSSERR("TE not received for 250ms!\n");
2730 }
2731 #endif
2732
2733 static void dsi_framedone_irq_callback(void *data, u32 mask)
2734 {
2735 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
2736 * turns itself off. However, DSI still has the pixels in its buffers,
2737 * and is sending the data.
2738 */
2739
2740 /* SIDLEMODE back to smart-idle */
2741 dispc_enable_sidle();
2742
2743 dsi.framedone_received = true;
2744 wake_up(&dsi.waitqueue);
2745 }
2746
2747 static void dsi_set_update_region(struct omap_dss_device *dssdev,
2748 u16 x, u16 y, u16 w, u16 h)
2749 {
2750 spin_lock(&dsi.update_lock);
2751 if (dsi.update_region.dirty) {
2752 dsi.update_region.x = min(x, dsi.update_region.x);
2753 dsi.update_region.y = min(y, dsi.update_region.y);
2754 dsi.update_region.w = max(w, dsi.update_region.w);
2755 dsi.update_region.h = max(h, dsi.update_region.h);
2756 } else {
2757 dsi.update_region.x = x;
2758 dsi.update_region.y = y;
2759 dsi.update_region.w = w;
2760 dsi.update_region.h = h;
2761 }
2762
2763 dsi.update_region.device = dssdev;
2764 dsi.update_region.dirty = true;
2765
2766 spin_unlock(&dsi.update_lock);
2767
2768 }
2769
2770 static int dsi_set_update_mode(struct omap_dss_device *dssdev,
2771 enum omap_dss_update_mode mode)
2772 {
2773 int r = 0;
2774 int i;
2775
2776 WARN_ON(!mutex_is_locked(&dsi.bus_lock));
2777
2778 if (dsi.update_mode != mode) {
2779 dsi.update_mode = mode;
2780
2781 /* Mark the overlays dirty, and do apply(), so that we get the
2782 * overlays configured properly after update mode change. */
2783 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2784 struct omap_overlay *ovl;
2785 ovl = omap_dss_get_overlay(i);
2786 if (ovl->manager == dssdev->manager)
2787 ovl->info_dirty = true;
2788 }
2789
2790 r = dssdev->manager->apply(dssdev->manager);
2791
2792 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE &&
2793 mode == OMAP_DSS_UPDATE_AUTO) {
2794 u16 w, h;
2795
2796 DSSDBG("starting auto update\n");
2797
2798 dssdev->get_resolution(dssdev, &w, &h);
2799
2800 dsi_set_update_region(dssdev, 0, 0, w, h);
2801
2802 dsi_perf_mark_start_auto();
2803
2804 wake_up(&dsi.waitqueue);
2805 }
2806 }
2807
2808 return r;
2809 }
2810
2811 static int dsi_set_te(struct omap_dss_device *dssdev, bool enable)
2812 {
2813 int r;
2814 r = dssdev->driver->enable_te(dssdev, enable);
2815 /* XXX for some reason, DSI TE breaks if we don't wait here.
2816 * Panel bug? Needs more studying */
2817 msleep(100);
2818 return r;
2819 }
2820
2821 static void dsi_handle_framedone(void)
2822 {
2823 int r;
2824 const int channel = 0;
2825 bool use_te_trigger;
2826
2827 use_te_trigger = dsi.te_enabled && !dsi.use_ext_te;
2828
2829 if (dsi.update_mode != OMAP_DSS_UPDATE_AUTO)
2830 DSSDBG("FRAMEDONE\n");
2831
2832 if (use_te_trigger) {
2833 /* enable LP_RX_TO again after the TE */
2834 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
2835 }
2836
2837 /* Send BTA after the frame. We need this for the TE to work, as TE
2838 * trigger is only sent for BTAs without preceding packet. Thus we need
2839 * to BTA after the pixel packets so that next BTA will cause TE
2840 * trigger.
2841 *
2842 * This is not needed when TE is not in use, but we do it anyway to
2843 * make sure that the transfer has been completed. It would be more
2844 * optimal, but more complex, to wait only just before starting next
2845 * transfer. */
2846 r = dsi_vc_send_bta_sync(channel);
2847 if (r)
2848 DSSERR("BTA after framedone failed\n");
2849
2850 /* RX_FIFO_NOT_EMPTY */
2851 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
2852 DSSERR("Received error during frame transfer:\n");
2853 dsi_vc_flush_receive_data(0);
2854 }
2855
2856 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
2857 dispc_fake_vsync_irq();
2858 #endif
2859 }
2860
2861 static int dsi_update_thread(void *data)
2862 {
2863 unsigned long timeout;
2864 struct omap_dss_device *device;
2865 u16 x, y, w, h;
2866
2867 while (1) {
2868 bool sched;
2869
2870 wait_event_interruptible(dsi.waitqueue,
2871 dsi.update_mode == OMAP_DSS_UPDATE_AUTO ||
2872 (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL &&
2873 dsi.update_region.dirty == true) ||
2874 kthread_should_stop());
2875
2876 if (kthread_should_stop())
2877 break;
2878
2879 dsi_bus_lock();
2880
2881 if (dsi.update_mode == OMAP_DSS_UPDATE_DISABLED ||
2882 kthread_should_stop()) {
2883 dsi_bus_unlock();
2884 break;
2885 }
2886
2887 dsi_perf_mark_setup();
2888
2889 if (dsi.update_region.dirty) {
2890 spin_lock(&dsi.update_lock);
2891 dsi.active_update_region = dsi.update_region;
2892 dsi.update_region.dirty = false;
2893 spin_unlock(&dsi.update_lock);
2894 }
2895
2896 device = dsi.active_update_region.device;
2897 x = dsi.active_update_region.x;
2898 y = dsi.active_update_region.y;
2899 w = dsi.active_update_region.w;
2900 h = dsi.active_update_region.h;
2901
2902 if (device->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
2903
2904 if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL)
2905 dss_setup_partial_planes(device,
2906 &x, &y, &w, &h);
2907
2908 dispc_set_lcd_size(w, h);
2909 }
2910
2911 if (dsi.active_update_region.dirty) {
2912 dsi.active_update_region.dirty = false;
2913 /* XXX TODO we don't need to send the coords, if they
2914 * are the same that are already programmed to the
2915 * panel. That should speed up manual update a bit */
2916 device->driver->setup_update(device, x, y, w, h);
2917 }
2918
2919 dsi_perf_mark_start();
2920
2921 if (device->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
2922 dsi_vc_config_vp(0);
2923
2924 if (dsi.te_enabled && dsi.use_ext_te)
2925 device->driver->wait_for_te(device);
2926
2927 dsi.framedone_received = false;
2928
2929 dsi_update_screen_dispc(device, x, y, w, h);
2930
2931 /* wait for framedone */
2932 timeout = msecs_to_jiffies(1000);
2933 wait_event_timeout(dsi.waitqueue,
2934 dsi.framedone_received == true,
2935 timeout);
2936
2937 if (!dsi.framedone_received) {
2938 DSSERR("framedone timeout\n");
2939 DSSERR("failed update %d,%d %dx%d\n",
2940 x, y, w, h);
2941
2942 dispc_enable_sidle();
2943 dispc_enable_lcd_out(0);
2944
2945 dsi_reset_tx_fifo(0);
2946 } else {
2947 dsi_handle_framedone();
2948 dsi_perf_show("DISPC");
2949 }
2950 } else {
2951 dsi_update_screen_l4(device, x, y, w, h);
2952 dsi_perf_show("L4");
2953 }
2954
2955 sched = atomic_read(&dsi.bus_lock.count) < 0;
2956
2957 complete_all(&dsi.update_completion);
2958
2959 dsi_bus_unlock();
2960
2961 /* XXX We need to give others chance to get the bus lock. Is
2962 * there a better way for this? */
2963 if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO && sched)
2964 schedule_timeout_interruptible(1);
2965 }
2966
2967 DSSDBG("update thread exiting\n");
2968
2969 return 0;
2970 }
2971
2972
2973
2974 /* Display funcs */
2975
2976 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
2977 {
2978 int r;
2979
2980 r = omap_dispc_register_isr(dsi_framedone_irq_callback, NULL,
2981 DISPC_IRQ_FRAMEDONE);
2982 if (r) {
2983 DSSERR("can't get FRAMEDONE irq\n");
2984 return r;
2985 }
2986
2987 dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
2988
2989 dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_DSI);
2990 dispc_enable_fifohandcheck(1);
2991
2992 dispc_set_tft_data_lines(dssdev->ctrl.pixel_size);
2993
2994 {
2995 struct omap_video_timings timings = {
2996 .hsw = 1,
2997 .hfp = 1,
2998 .hbp = 1,
2999 .vsw = 1,
3000 .vfp = 0,
3001 .vbp = 0,
3002 };
3003
3004 dispc_set_lcd_timings(&timings);
3005 }
3006
3007 return 0;
3008 }
3009
3010 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
3011 {
3012 omap_dispc_unregister_isr(dsi_framedone_irq_callback, NULL,
3013 DISPC_IRQ_FRAMEDONE);
3014 }
3015
3016 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
3017 {
3018 struct dsi_clock_info cinfo;
3019 int r;
3020
3021 /* we always use DSS2_FCK as input clock */
3022 cinfo.use_dss2_fck = true;
3023 cinfo.regn = dssdev->phy.dsi.div.regn;
3024 cinfo.regm = dssdev->phy.dsi.div.regm;
3025 cinfo.regm3 = dssdev->phy.dsi.div.regm3;
3026 cinfo.regm4 = dssdev->phy.dsi.div.regm4;
3027 r = dsi_calc_clock_rates(&cinfo);
3028 if (r)
3029 return r;
3030
3031 r = dsi_pll_set_clock_div(&cinfo);
3032 if (r) {
3033 DSSERR("Failed to set dsi clocks\n");
3034 return r;
3035 }
3036
3037 return 0;
3038 }
3039
3040 static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
3041 {
3042 struct dispc_clock_info dispc_cinfo;
3043 int r;
3044 unsigned long long fck;
3045
3046 fck = dsi_get_dsi1_pll_rate();
3047
3048 dispc_cinfo.lck_div = dssdev->phy.dsi.div.lck_div;
3049 dispc_cinfo.pck_div = dssdev->phy.dsi.div.pck_div;
3050
3051 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
3052 if (r) {
3053 DSSERR("Failed to calc dispc clocks\n");
3054 return r;
3055 }
3056
3057 r = dispc_set_clock_div(&dispc_cinfo);
3058 if (r) {
3059 DSSERR("Failed to set dispc clocks\n");
3060 return r;
3061 }
3062
3063 return 0;
3064 }
3065
3066 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
3067 {
3068 int r;
3069
3070 _dsi_print_reset_status();
3071
3072 r = dsi_pll_init(dssdev, true, true);
3073 if (r)
3074 goto err0;
3075
3076 r = dsi_configure_dsi_clocks(dssdev);
3077 if (r)
3078 goto err1;
3079
3080 dss_select_clk_source(true, true);
3081
3082 DSSDBG("PLL OK\n");
3083
3084 r = dsi_configure_dispc_clocks(dssdev);
3085 if (r)
3086 goto err2;
3087
3088 r = dsi_complexio_init(dssdev);
3089 if (r)
3090 goto err2;
3091
3092 _dsi_print_reset_status();
3093
3094 dsi_proto_timings(dssdev);
3095 dsi_set_lp_clk_divisor(dssdev);
3096
3097 if (1)
3098 _dsi_print_reset_status();
3099
3100 r = dsi_proto_config(dssdev);
3101 if (r)
3102 goto err3;
3103
3104 /* enable interface */
3105 dsi_vc_enable(0, 1);
3106 dsi_if_enable(1);
3107 dsi_force_tx_stop_mode_io();
3108
3109 if (dssdev->driver->enable) {
3110 r = dssdev->driver->enable(dssdev);
3111 if (r)
3112 goto err4;
3113 }
3114
3115 /* enable high-speed after initial config */
3116 dsi_vc_enable_hs(0, 1);
3117
3118 return 0;
3119 err4:
3120 dsi_if_enable(0);
3121 err3:
3122 dsi_complexio_uninit();
3123 err2:
3124 dss_select_clk_source(false, false);
3125 err1:
3126 dsi_pll_uninit();
3127 err0:
3128 return r;
3129 }
3130
3131 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev)
3132 {
3133 if (dssdev->driver->disable)
3134 dssdev->driver->disable(dssdev);
3135
3136 dss_select_clk_source(false, false);
3137 dsi_complexio_uninit();
3138 dsi_pll_uninit();
3139 }
3140
3141 static int dsi_core_init(void)
3142 {
3143 /* Autoidle */
3144 REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0);
3145
3146 /* ENWAKEUP */
3147 REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
3148
3149 /* SIDLEMODE smart-idle */
3150 REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);
3151
3152 _dsi_initialize_irq();
3153
3154 return 0;
3155 }
3156
3157 static int dsi_display_enable(struct omap_dss_device *dssdev)
3158 {
3159 int r = 0;
3160
3161 DSSDBG("dsi_display_enable\n");
3162
3163 mutex_lock(&dsi.lock);
3164 dsi_bus_lock();
3165
3166 r = omap_dss_start_device(dssdev);
3167 if (r) {
3168 DSSERR("failed to start device\n");
3169 goto err0;
3170 }
3171
3172 if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) {
3173 DSSERR("dssdev already enabled\n");
3174 r = -EINVAL;
3175 goto err1;
3176 }
3177
3178 enable_clocks(1);
3179 dsi_enable_pll_clock(1);
3180
3181 r = _dsi_reset();
3182 if (r)
3183 goto err2;
3184
3185 dsi_core_init();
3186
3187 r = dsi_display_init_dispc(dssdev);
3188 if (r)
3189 goto err2;
3190
3191 r = dsi_display_init_dsi(dssdev);
3192 if (r)
3193 goto err3;
3194
3195 dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
3196
3197 dsi.use_ext_te = dssdev->phy.dsi.ext_te;
3198 r = dsi_set_te(dssdev, dsi.te_enabled);
3199 if (r)
3200 goto err4;
3201
3202 dsi_set_update_mode(dssdev, dsi.user_update_mode);
3203
3204 dsi_bus_unlock();
3205 mutex_unlock(&dsi.lock);
3206
3207 return 0;
3208
3209 err4:
3210
3211 dsi_display_uninit_dsi(dssdev);
3212 err3:
3213 dsi_display_uninit_dispc(dssdev);
3214 err2:
3215 enable_clocks(0);
3216 dsi_enable_pll_clock(0);
3217 err1:
3218 omap_dss_stop_device(dssdev);
3219 err0:
3220 dsi_bus_unlock();
3221 mutex_unlock(&dsi.lock);
3222 DSSDBG("dsi_display_enable FAILED\n");
3223 return r;
3224 }
3225
3226 static void dsi_display_disable(struct omap_dss_device *dssdev)
3227 {
3228 DSSDBG("dsi_display_disable\n");
3229
3230 mutex_lock(&dsi.lock);
3231 dsi_bus_lock();
3232
3233 if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED ||
3234 dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED)
3235 goto end;
3236
3237 dsi.update_mode = OMAP_DSS_UPDATE_DISABLED;
3238 dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
3239
3240 dsi_display_uninit_dispc(dssdev);
3241
3242 dsi_display_uninit_dsi(dssdev);
3243
3244 enable_clocks(0);
3245 dsi_enable_pll_clock(0);
3246
3247 omap_dss_stop_device(dssdev);
3248 end:
3249 dsi_bus_unlock();
3250 mutex_unlock(&dsi.lock);
3251 }
3252
3253 static int dsi_display_suspend(struct omap_dss_device *dssdev)
3254 {
3255 DSSDBG("dsi_display_suspend\n");
3256
3257 mutex_lock(&dsi.lock);
3258 dsi_bus_lock();
3259
3260 if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED ||
3261 dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED)
3262 goto end;
3263
3264 dsi.update_mode = OMAP_DSS_UPDATE_DISABLED;
3265 dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED;
3266
3267 dsi_display_uninit_dispc(dssdev);
3268
3269 dsi_display_uninit_dsi(dssdev);
3270
3271 enable_clocks(0);
3272 dsi_enable_pll_clock(0);
3273 end:
3274 dsi_bus_unlock();
3275 mutex_unlock(&dsi.lock);
3276
3277 return 0;
3278 }
3279
3280 static int dsi_display_resume(struct omap_dss_device *dssdev)
3281 {
3282 int r;
3283
3284 DSSDBG("dsi_display_resume\n");
3285
3286 mutex_lock(&dsi.lock);
3287 dsi_bus_lock();
3288
3289 if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED) {
3290 DSSERR("dssdev not suspended\n");
3291 r = -EINVAL;
3292 goto err0;
3293 }
3294
3295 enable_clocks(1);
3296 dsi_enable_pll_clock(1);
3297
3298 r = _dsi_reset();
3299 if (r)
3300 goto err1;
3301
3302 dsi_core_init();
3303
3304 r = dsi_display_init_dispc(dssdev);
3305 if (r)
3306 goto err1;
3307
3308 r = dsi_display_init_dsi(dssdev);
3309 if (r)
3310 goto err2;
3311
3312 dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
3313
3314 r = dsi_set_te(dssdev, dsi.te_enabled);
3315 if (r)
3316 goto err2;
3317
3318 dsi_set_update_mode(dssdev, dsi.user_update_mode);
3319
3320 dsi_bus_unlock();
3321 mutex_unlock(&dsi.lock);
3322
3323 return 0;
3324
3325 err2:
3326 dsi_display_uninit_dispc(dssdev);
3327 err1:
3328 enable_clocks(0);
3329 dsi_enable_pll_clock(0);
3330 err0:
3331 dsi_bus_unlock();
3332 mutex_unlock(&dsi.lock);
3333 DSSDBG("dsi_display_resume FAILED\n");
3334 return r;
3335 }
3336
3337 static int dsi_display_update(struct omap_dss_device *dssdev,
3338 u16 x, u16 y, u16 w, u16 h)
3339 {
3340 int r = 0;
3341 u16 dw, dh;
3342
3343 DSSDBG("dsi_display_update(%d,%d %dx%d)\n", x, y, w, h);
3344
3345 mutex_lock(&dsi.lock);
3346
3347 if (dsi.update_mode != OMAP_DSS_UPDATE_MANUAL)
3348 goto end;
3349
3350 if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
3351 goto end;
3352
3353 dssdev->get_resolution(dssdev, &dw, &dh);
3354
3355 if (x > dw || y > dh)
3356 goto end;
3357
3358 if (x + w > dw)
3359 w = dw - x;
3360
3361 if (y + h > dh)
3362 h = dh - y;
3363
3364 if (w == 0 || h == 0)
3365 goto end;
3366
3367 if (w == 1) {
3368 r = -EINVAL;
3369 goto end;
3370 }
3371
3372 dsi_set_update_region(dssdev, x, y, w, h);
3373
3374 wake_up(&dsi.waitqueue);
3375
3376 end:
3377 mutex_unlock(&dsi.lock);
3378
3379 return r;
3380 }
3381
3382 static int dsi_display_sync(struct omap_dss_device *dssdev)
3383 {
3384 bool wait;
3385
3386 DSSDBG("dsi_display_sync()\n");
3387
3388 mutex_lock(&dsi.lock);
3389 dsi_bus_lock();
3390
3391 if (dsi.update_mode == OMAP_DSS_UPDATE_MANUAL &&
3392 dsi.update_region.dirty) {
3393 INIT_COMPLETION(dsi.update_completion);
3394 wait = true;
3395 } else {
3396 wait = false;
3397 }
3398
3399 dsi_bus_unlock();
3400 mutex_unlock(&dsi.lock);
3401
3402 if (wait)
3403 wait_for_completion_interruptible(&dsi.update_completion);
3404
3405 DSSDBG("dsi_display_sync() done\n");
3406 return 0;
3407 }
3408
3409 static int dsi_display_set_update_mode(struct omap_dss_device *dssdev,
3410 enum omap_dss_update_mode mode)
3411 {
3412 int r = 0;
3413
3414 DSSDBGF("%d", mode);
3415
3416 mutex_lock(&dsi.lock);
3417 dsi_bus_lock();
3418
3419 dsi.user_update_mode = mode;
3420 r = dsi_set_update_mode(dssdev, mode);
3421
3422 dsi_bus_unlock();
3423 mutex_unlock(&dsi.lock);
3424
3425 return r;
3426 }
3427
3428 static enum omap_dss_update_mode dsi_display_get_update_mode(
3429 struct omap_dss_device *dssdev)
3430 {
3431 return dsi.update_mode;
3432 }
3433
3434
3435 static int dsi_display_enable_te(struct omap_dss_device *dssdev, bool enable)
3436 {
3437 int r = 0;
3438
3439 DSSDBGF("%d", enable);
3440
3441 if (!dssdev->driver->enable_te)
3442 return -ENOENT;
3443
3444 dsi_bus_lock();
3445
3446 dsi.te_enabled = enable;
3447
3448 if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
3449 goto end;
3450
3451 r = dsi_set_te(dssdev, enable);
3452 end:
3453 dsi_bus_unlock();
3454
3455 return r;
3456 }
3457
3458 static int dsi_display_get_te(struct omap_dss_device *dssdev)
3459 {
3460 return dsi.te_enabled;
3461 }
3462
3463 static int dsi_display_set_rotate(struct omap_dss_device *dssdev, u8 rotate)
3464 {
3465
3466 DSSDBGF("%d", rotate);
3467
3468 if (!dssdev->driver->set_rotate || !dssdev->driver->get_rotate)
3469 return -EINVAL;
3470
3471 dsi_bus_lock();
3472 dssdev->driver->set_rotate(dssdev, rotate);
3473 if (dsi.update_mode == OMAP_DSS_UPDATE_AUTO) {
3474 u16 w, h;
3475 /* the display dimensions may have changed, so set a new
3476 * update region */
3477 dssdev->get_resolution(dssdev, &w, &h);
3478 dsi_set_update_region(dssdev, 0, 0, w, h);
3479 }
3480 dsi_bus_unlock();
3481
3482 return 0;
3483 }
3484
3485 static u8 dsi_display_get_rotate(struct omap_dss_device *dssdev)
3486 {
3487 if (!dssdev->driver->set_rotate || !dssdev->driver->get_rotate)
3488 return 0;
3489
3490 return dssdev->driver->get_rotate(dssdev);
3491 }
3492
3493 static int dsi_display_set_mirror(struct omap_dss_device *dssdev, bool mirror)
3494 {
3495 DSSDBGF("%d", mirror);
3496
3497 if (!dssdev->driver->set_mirror || !dssdev->driver->get_mirror)
3498 return -EINVAL;
3499
3500 dsi_bus_lock();
3501 dssdev->driver->set_mirror(dssdev, mirror);
3502 dsi_bus_unlock();
3503
3504 return 0;
3505 }
3506
3507 static bool dsi_display_get_mirror(struct omap_dss_device *dssdev)
3508 {
3509 if (!dssdev->driver->set_mirror || !dssdev->driver->get_mirror)
3510 return 0;
3511
3512 return dssdev->driver->get_mirror(dssdev);
3513 }
3514
3515 static int dsi_display_run_test(struct omap_dss_device *dssdev, int test_num)
3516 {
3517 int r;
3518
3519 if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
3520 return -EIO;
3521
3522 DSSDBGF("%d", test_num);
3523
3524 dsi_bus_lock();
3525
3526 /* run test first in low speed mode */
3527 dsi_vc_enable_hs(0, 0);
3528
3529 if (dssdev->driver->run_test) {
3530 r = dssdev->driver->run_test(dssdev, test_num);
3531 if (r)
3532 goto end;
3533 }
3534
3535 /* then in high speed */
3536 dsi_vc_enable_hs(0, 1);
3537
3538 if (dssdev->driver->run_test) {
3539 r = dssdev->driver->run_test(dssdev, test_num);
3540 if (r)
3541 goto end;
3542 }
3543
3544 end:
3545 dsi_vc_enable_hs(0, 1);
3546
3547 dsi_bus_unlock();
3548
3549 return r;
3550 }
3551
3552 static int dsi_display_memory_read(struct omap_dss_device *dssdev,
3553 void *buf, size_t size,
3554 u16 x, u16 y, u16 w, u16 h)
3555 {
3556 int r;
3557
3558 DSSDBGF("");
3559
3560 if (!dssdev->driver->memory_read)
3561 return -EINVAL;
3562
3563 if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
3564 return -EIO;
3565
3566 dsi_bus_lock();
3567
3568 r = dssdev->driver->memory_read(dssdev, buf, size,
3569 x, y, w, h);
3570
3571 /* Memory read usually changes the update area. This will
3572 * force the next update to re-set the update area */
3573 dsi.active_update_region.dirty = true;
3574
3575 dsi_bus_unlock();
3576
3577 return r;
3578 }
3579
3580 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
3581 u32 fifo_size, enum omap_burst_size *burst_size,
3582 u32 *fifo_low, u32 *fifo_high)
3583 {
3584 unsigned burst_size_bytes;
3585
3586 *burst_size = OMAP_DSS_BURST_16x32;
3587 burst_size_bytes = 16 * 32 / 8;
3588
3589 *fifo_high = fifo_size - burst_size_bytes;
3590 *fifo_low = fifo_size - burst_size_bytes * 8;
3591 }
3592
3593 int dsi_init_display(struct omap_dss_device *dssdev)
3594 {
3595 DSSDBG("DSI init\n");
3596
3597 dssdev->enable = dsi_display_enable;
3598 dssdev->disable = dsi_display_disable;
3599 dssdev->suspend = dsi_display_suspend;
3600 dssdev->resume = dsi_display_resume;
3601 dssdev->update = dsi_display_update;
3602 dssdev->sync = dsi_display_sync;
3603 dssdev->set_update_mode = dsi_display_set_update_mode;
3604 dssdev->get_update_mode = dsi_display_get_update_mode;
3605 dssdev->enable_te = dsi_display_enable_te;
3606 dssdev->get_te = dsi_display_get_te;
3607
3608 dssdev->get_rotate = dsi_display_get_rotate;
3609 dssdev->set_rotate = dsi_display_set_rotate;
3610
3611 dssdev->get_mirror = dsi_display_get_mirror;
3612 dssdev->set_mirror = dsi_display_set_mirror;
3613
3614 dssdev->run_test = dsi_display_run_test;
3615 dssdev->memory_read = dsi_display_memory_read;
3616
3617 /* XXX these should be figured out dynamically */
3618 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
3619 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
3620
3621 dsi.vc[0].dssdev = dssdev;
3622 dsi.vc[1].dssdev = dssdev;
3623
3624 return 0;
3625 }
3626
3627 int dsi_init(struct platform_device *pdev)
3628 {
3629 u32 rev;
3630 int r;
3631 struct sched_param param = {
3632 .sched_priority = MAX_USER_RT_PRIO-1
3633 };
3634
3635 spin_lock_init(&dsi.errors_lock);
3636 dsi.errors = 0;
3637
3638 init_completion(&dsi.bta_completion);
3639 init_completion(&dsi.update_completion);
3640
3641 dsi.thread = kthread_create(dsi_update_thread, NULL, "dsi");
3642 if (IS_ERR(dsi.thread)) {
3643 DSSERR("cannot create kthread\n");
3644 r = PTR_ERR(dsi.thread);
3645 goto err0;
3646 }
3647 sched_setscheduler(dsi.thread, SCHED_FIFO, &param);
3648
3649 init_waitqueue_head(&dsi.waitqueue);
3650 spin_lock_init(&dsi.update_lock);
3651
3652 mutex_init(&dsi.lock);
3653 mutex_init(&dsi.bus_lock);
3654
3655 #ifdef DSI_CATCH_MISSING_TE
3656 init_timer(&dsi.te_timer);
3657 dsi.te_timer.function = dsi_te_timeout;
3658 dsi.te_timer.data = 0;
3659 #endif
3660
3661 dsi.update_mode = OMAP_DSS_UPDATE_DISABLED;
3662 dsi.user_update_mode = OMAP_DSS_UPDATE_DISABLED;
3663
3664 dsi.base = ioremap(DSI_BASE, DSI_SZ_REGS);
3665 if (!dsi.base) {
3666 DSSERR("can't ioremap DSI\n");
3667 r = -ENOMEM;
3668 goto err1;
3669 }
3670
3671 dsi.vdds_dsi_reg = regulator_get(&pdev->dev, "vdds_dsi");
3672 if (IS_ERR(dsi.vdds_dsi_reg)) {
3673 iounmap(dsi.base);
3674 DSSERR("can't get VDDS_DSI regulator\n");
3675 r = PTR_ERR(dsi.vdds_dsi_reg);
3676 goto err2;
3677 }
3678
3679 enable_clocks(1);
3680
3681 rev = dsi_read_reg(DSI_REVISION);
3682 printk(KERN_INFO "OMAP DSI rev %d.%d\n",
3683 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3684
3685 enable_clocks(0);
3686
3687 wake_up_process(dsi.thread);
3688
3689 return 0;
3690 err2:
3691 iounmap(dsi.base);
3692 err1:
3693 kthread_stop(dsi.thread);
3694 err0:
3695 return r;
3696 }
3697
3698 void dsi_exit(void)
3699 {
3700 kthread_stop(dsi.thread);
3701
3702 regulator_put(dsi.vdds_dsi_reg);
3703
3704 iounmap(dsi.base);
3705
3706 DSSDBG("omap_dsi_exit\n");
3707 }
3708
Linux for Ginger Game Console