drivers/video/omap2/dss/dss.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DSS"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/io.h>
  27 #include <linux/err.h>
  28 #include <linux/delay.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/seq_file.h>
  31 #include <linux/clk.h>
  32
  33 #include <plat/display.h>
  34 #include "dss.h"
  35
  36 #define DSS_BASE                        0x48050000
  37
  38 #define DSS_SZ_REGS                     SZ_512
  39
  40 struct dss_reg {
  41         u16 idx;
  42 };
  43
  44 #define DSS_REG(idx)                    ((const struct dss_reg) { idx })
  45
  46 #define DSS_REVISION                    DSS_REG(0x0000)
  47 #define DSS_SYSCONFIG                   DSS_REG(0x0010)
  48 #define DSS_SYSSTATUS                   DSS_REG(0x0014)
  49 #define DSS_IRQSTATUS                   DSS_REG(0x0018)
  50 #define DSS_CONTROL                     DSS_REG(0x0040)
  51 #define DSS_SDI_CONTROL                 DSS_REG(0x0044)
  52 #define DSS_PLL_CONTROL                 DSS_REG(0x0048)
  53 #define DSS_SDI_STATUS                  DSS_REG(0x005C)
  54
  55 #define REG_GET(idx, start, end) \
  56         FLD_GET(dss_read_reg(idx), start, end)
  57
  58 #define REG_FLD_MOD(idx, val, start, end) \
  59         dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
  60
  61 static struct {
  62         void __iomem    *base;
  63
  64         struct clk      *dpll4_m4_ck;
  65
  66         unsigned long   cache_req_pck;
  67         unsigned long   cache_prate;
  68         struct dss_clock_info cache_dss_cinfo;
  69         struct dispc_clock_info cache_dispc_cinfo;
  70
  71         u32             ctx[DSS_SZ_REGS / sizeof(u32)];
  72 } dss;
  73
  74 static int _omap_dss_wait_reset(void);
  75
  76 static inline void dss_write_reg(const struct dss_reg idx, u32 val)
  77 {
  78         __raw_writel(val, dss.base + idx.idx);
  79 }
  80
  81 static inline u32 dss_read_reg(const struct dss_reg idx)
  82 {
  83         return __raw_readl(dss.base + idx.idx);
  84 }
  85
  86 #define SR(reg) \
  87         dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
  88 #define RR(reg) \
  89         dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
  90
  91 void dss_save_context(void)
  92 {
  93         if (cpu_is_omap24xx())
  94                 return;
  95
  96         SR(SYSCONFIG);
  97         SR(CONTROL);
  98
  99 #ifdef CONFIG_OMAP2_DSS_SDI
 100         SR(SDI_CONTROL);
 101         SR(PLL_CONTROL);
 102 #endif
 103 }
 104
 105 void dss_restore_context(void)
 106 {
 107         if (_omap_dss_wait_reset())
 108                 DSSERR("DSS not coming out of reset after sleep\n");
 109
 110         RR(SYSCONFIG);
 111         RR(CONTROL);
 112
 113 #ifdef CONFIG_OMAP2_DSS_SDI
 114         RR(SDI_CONTROL);
 115         RR(PLL_CONTROL);
 116 #endif
 117 }
 118
 119 #undef SR
 120 #undef RR
 121
 122 void dss_sdi_init(u8 datapairs)
 123 {
 124         u32 l;
 125
 126         BUG_ON(datapairs > 3 || datapairs < 1);
 127
 128         l = dss_read_reg(DSS_SDI_CONTROL);
 129         l = FLD_MOD(l, 0xf, 19, 15);            /* SDI_PDIV */
 130         l = FLD_MOD(l, datapairs-1, 3, 2);      /* SDI_PRSEL */
 131         l = FLD_MOD(l, 2, 1, 0);                /* SDI_BWSEL */
 132         dss_write_reg(DSS_SDI_CONTROL, l);
 133
 134         l = dss_read_reg(DSS_PLL_CONTROL);
 135         l = FLD_MOD(l, 0x7, 25, 22);    /* SDI_PLL_FREQSEL */
 136         l = FLD_MOD(l, 0xb, 16, 11);    /* SDI_PLL_REGN */
 137         l = FLD_MOD(l, 0xb4, 10, 1);    /* SDI_PLL_REGM */
 138         dss_write_reg(DSS_PLL_CONTROL, l);
 139 }
 140
 141 int dss_sdi_enable(void)
 142 {
 143         unsigned long timeout;
 144
 145         dispc_pck_free_enable(1);
 146
 147         /* Reset SDI PLL */
 148         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
 149         udelay(1);      /* wait 2x PCLK */
 150
 151         /* Lock SDI PLL */
 152         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
 153
 154         /* Waiting for PLL lock request to complete */
 155         timeout = jiffies + msecs_to_jiffies(500);
 156         while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
 157                 if (time_after_eq(jiffies, timeout)) {
 158                         DSSERR("PLL lock request timed out\n");
 159                         goto err1;
 160                 }
 161         }
 162
 163         /* Clearing PLL_GO bit */
 164         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
 165
 166         /* Waiting for PLL to lock */
 167         timeout = jiffies + msecs_to_jiffies(500);
 168         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
 169                 if (time_after_eq(jiffies, timeout)) {
 170                         DSSERR("PLL lock timed out\n");
 171                         goto err1;
 172                 }
 173         }
 174
 175         dispc_lcd_enable_signal(1);
 176
 177         /* Waiting for SDI reset to complete */
 178         timeout = jiffies + msecs_to_jiffies(500);
 179         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
 180                 if (time_after_eq(jiffies, timeout)) {
 181                         DSSERR("SDI reset timed out\n");
 182                         goto err2;
 183                 }
 184         }
 185
 186         return 0;
 187
 188  err2:
 189         dispc_lcd_enable_signal(0);
 190  err1:
 191         /* Reset SDI PLL */
 192         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 193
 194         dispc_pck_free_enable(0);
 195
 196         return -ETIMEDOUT;
 197 }
 198
 199 void dss_sdi_disable(void)
 200 {
 201         dispc_lcd_enable_signal(0);
 202
 203         dispc_pck_free_enable(0);
 204
 205         /* Reset SDI PLL */
 206         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 207 }
 208
 209 void dss_dump_clocks(struct seq_file *s)
 210 {
 211         unsigned long dpll4_ck_rate;
 212         unsigned long dpll4_m4_ck_rate;
 213
 214         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
 215
 216         dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 217         dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
 218
 219         seq_printf(s, "- DSS -\n");
 220
 221         seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
 222
 223         seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n",
 224                         dpll4_ck_rate,
 225                         dpll4_ck_rate / dpll4_m4_ck_rate,
 226                         dss_clk_get_rate(DSS_CLK_FCK1));
 227
 228         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
 229 }
 230
 231 void dss_dump_regs(struct seq_file *s)
 232 {
 233 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
 234
 235         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
 236
 237         DUMPREG(DSS_REVISION);
 238         DUMPREG(DSS_SYSCONFIG);
 239         DUMPREG(DSS_SYSSTATUS);
 240         DUMPREG(DSS_IRQSTATUS);
 241         DUMPREG(DSS_CONTROL);
 242         DUMPREG(DSS_SDI_CONTROL);
 243         DUMPREG(DSS_PLL_CONTROL);
 244         DUMPREG(DSS_SDI_STATUS);
 245
 246         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
 247 #undef DUMPREG
 248 }
 249
 250 void dss_select_clk_source(bool dsi, bool dispc)
 251 {
 252         u32 r;
 253         r = dss_read_reg(DSS_CONTROL);
 254         r = FLD_MOD(r, dsi, 1, 1);      /* DSI_CLK_SWITCH */
 255         r = FLD_MOD(r, dispc, 0, 0);    /* DISPC_CLK_SWITCH */
 256         dss_write_reg(DSS_CONTROL, r);
 257 }
 258
 259 int dss_get_dsi_clk_source(void)
 260 {
 261         return FLD_GET(dss_read_reg(DSS_CONTROL), 1, 1);
 262 }
 263
 264 int dss_get_dispc_clk_source(void)
 265 {
 266         return FLD_GET(dss_read_reg(DSS_CONTROL), 0, 0);
 267 }
 268
 269 /* calculate clock rates using dividers in cinfo */
 270 int dss_calc_clock_rates(struct dss_clock_info *cinfo)
 271 {
 272         unsigned long prate;
 273
 274         if (cinfo->fck_div > 16 || cinfo->fck_div == 0)
 275                 return -EINVAL;
 276
 277         prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 278
 279         cinfo->fck = prate / cinfo->fck_div;
 280
 281         return 0;
 282 }
 283
 284 int dss_set_clock_div(struct dss_clock_info *cinfo)
 285 {
 286         unsigned long prate;
 287         int r;
 288
 289         if (cpu_is_omap34xx()) {
 290                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 291                 DSSDBG("dpll4_m4 = %ld\n", prate);
 292
 293                 r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div);
 294                 if (r)
 295                         return r;
 296         }
 297
 298         DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
 299
 300         return 0;
 301 }
 302
 303 int dss_get_clock_div(struct dss_clock_info *cinfo)
 304 {
 305         cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1);
 306
 307         if (cpu_is_omap34xx()) {
 308                 unsigned long prate;
 309                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 310                 cinfo->fck_div = prate / (cinfo->fck / 2);
 311         } else {
 312                 cinfo->fck_div = 0;
 313         }
 314
 315         return 0;
 316 }
 317
 318 unsigned long dss_get_dpll4_rate(void)
 319 {
 320         if (cpu_is_omap34xx())
 321                 return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 322         else
 323                 return 0;
 324 }
 325
 326 int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
 327                 struct dss_clock_info *dss_cinfo,
 328                 struct dispc_clock_info *dispc_cinfo)
 329 {
 330         unsigned long prate;
 331         struct dss_clock_info best_dss;
 332         struct dispc_clock_info best_dispc;
 333
 334         unsigned long fck;
 335
 336         u16 fck_div;
 337
 338         int match = 0;
 339         int min_fck_per_pck;
 340
 341         prate = dss_get_dpll4_rate();
 342
 343         fck = dss_clk_get_rate(DSS_CLK_FCK1);
 344         if (req_pck == dss.cache_req_pck &&
 345                         ((cpu_is_omap34xx() && prate == dss.cache_prate) ||
 346                          dss.cache_dss_cinfo.fck == fck)) {
 347                 DSSDBG("dispc clock info found from cache.\n");
 348                 *dss_cinfo = dss.cache_dss_cinfo;
 349                 *dispc_cinfo = dss.cache_dispc_cinfo;
 350                 return 0;
 351         }
 352
 353         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
 354
 355         if (min_fck_per_pck &&
 356                 req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
 357                 DSSERR("Requested pixel clock not possible with the current "
 358                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
 359                                 "the constraint off.\n");
 360                 min_fck_per_pck = 0;
 361         }
 362
 363 retry:
 364         memset(&best_dss, 0, sizeof(best_dss));
 365         memset(&best_dispc, 0, sizeof(best_dispc));
 366
 367         if (cpu_is_omap24xx()) {
 368                 struct dispc_clock_info cur_dispc;
 369                 /* XXX can we change the clock on omap2? */
 370                 fck = dss_clk_get_rate(DSS_CLK_FCK1);
 371                 fck_div = 1;
 372
 373                 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
 374                 match = 1;
 375
 376                 best_dss.fck = fck;
 377                 best_dss.fck_div = fck_div;
 378
 379                 best_dispc = cur_dispc;
 380
 381                 goto found;
 382         } else if (cpu_is_omap34xx()) {
 383                 for (fck_div = 16; fck_div > 0; --fck_div) {
 384                         struct dispc_clock_info cur_dispc;
 385
 386                         fck = prate / fck_div * 2;
 387
 388                         if (fck > DISPC_MAX_FCK)
 389                                 continue;
 390
 391                         if (min_fck_per_pck &&
 392                                         fck < req_pck * min_fck_per_pck)
 393                                 continue;
 394
 395                         match = 1;
 396
 397                         dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
 398
 399                         if (abs(cur_dispc.pck - req_pck) <
 400                                         abs(best_dispc.pck - req_pck)) {
 401
 402                                 best_dss.fck = fck;
 403                                 best_dss.fck_div = fck_div;
 404
 405                                 best_dispc = cur_dispc;
 406
 407                                 if (cur_dispc.pck == req_pck)
 408                                         goto found;
 409                         }
 410                 }
 411         } else {
 412                 BUG();
 413         }
 414
 415 found:
 416         if (!match) {
 417                 if (min_fck_per_pck) {
 418                         DSSERR("Could not find suitable clock settings.\n"
 419                                         "Turning FCK/PCK constraint off and"
 420                                         "trying again.\n");
 421                         min_fck_per_pck = 0;
 422                         goto retry;
 423                 }
 424
 425                 DSSERR("Could not find suitable clock settings.\n");
 426
 427                 return -EINVAL;
 428         }
 429
 430         if (dss_cinfo)
 431                 *dss_cinfo = best_dss;
 432         if (dispc_cinfo)
 433                 *dispc_cinfo = best_dispc;
 434
 435         dss.cache_req_pck = req_pck;
 436         dss.cache_prate = prate;
 437         dss.cache_dss_cinfo = best_dss;
 438         dss.cache_dispc_cinfo = best_dispc;
 439
 440         return 0;
 441 }
 442
 443
 444
 445 static irqreturn_t dss_irq_handler_omap2(int irq, void *arg)
 446 {
 447         dispc_irq_handler();
 448
 449         return IRQ_HANDLED;
 450 }
 451
 452 static irqreturn_t dss_irq_handler_omap3(int irq, void *arg)
 453 {
 454         u32 irqstatus;
 455
 456         irqstatus = dss_read_reg(DSS_IRQSTATUS);
 457
 458         if (irqstatus & (1<<0)) /* DISPC_IRQ */
 459                 dispc_irq_handler();
 460 #ifdef CONFIG_OMAP2_DSS_DSI
 461         if (irqstatus & (1<<1)) /* DSI_IRQ */
 462                 dsi_irq_handler();
 463 #endif
 464
 465         return IRQ_HANDLED;
 466 }
 467
 468 static int _omap_dss_wait_reset(void)
 469 {
 470         unsigned timeout = 1000;
 471
 472         while (REG_GET(DSS_SYSSTATUS, 0, 0) == 0) {
 473                 udelay(1);
 474                 if (!--timeout) {
 475                         DSSERR("soft reset failed\n");
 476                         return -ENODEV;
 477                 }
 478         }
 479
 480         return 0;
 481 }
 482
 483 static int _omap_dss_reset(void)
 484 {
 485         /* Soft reset */
 486         REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1);
 487         return _omap_dss_wait_reset();
 488 }
 489
 490 void dss_set_venc_output(enum omap_dss_venc_type type)
 491 {
 492         int l = 0;
 493
 494         if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
 495                 l = 0;
 496         else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
 497                 l = 1;
 498         else
 499                 BUG();
 500
 501         /* venc out selection. 0 = comp, 1 = svideo */
 502         REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
 503 }
 504
 505 void dss_set_dac_pwrdn_bgz(bool enable)
 506 {
 507         REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
 508 }
 509
 510 int dss_init(bool skip_init)
 511 {
 512         int r;
 513         u32 rev;
 514
 515         dss.base = ioremap(DSS_BASE, DSS_SZ_REGS);
 516         if (!dss.base) {
 517                 DSSERR("can't ioremap DSS\n");
 518                 r = -ENOMEM;
 519                 goto fail0;
 520         }
 521
 522         if (!skip_init) {
 523                 /* disable LCD and DIGIT output. This seems to fix the synclost
 524                  * problem that we get, if the bootloader starts the DSS and
 525                  * the kernel resets it */
 526                 omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440);
 527
 528                 /* We need to wait here a bit, otherwise we sometimes start to
 529                  * get synclost errors, and after that only power cycle will
 530                  * restore DSS functionality. I have no idea why this happens.
 531                  * And we have to wait _before_ resetting the DSS, but after
 532                  * enabling clocks.
 533                  */
 534                 msleep(50);
 535
 536                 _omap_dss_reset();
 537         }
 538
 539         /* autoidle */
 540         REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0);
 541
 542         /* Select DPLL */
 543         REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
 544
 545 #ifdef CONFIG_OMAP2_DSS_VENC
 546         REG_FLD_MOD(DSS_CONTROL, 1, 4, 4);      /* venc dac demen */
 547         REG_FLD_MOD(DSS_CONTROL, 1, 3, 3);      /* venc clock 4x enable */
 548         REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);      /* venc clock mode = normal */
 549 #endif
 550
 551         r = request_irq(INT_24XX_DSS_IRQ,
 552                         cpu_is_omap24xx()
 553                         ? dss_irq_handler_omap2
 554                         : dss_irq_handler_omap3,
 555                         0, "OMAP DSS", NULL);
 556
 557         if (r < 0) {
 558                 DSSERR("omap2 dss: request_irq failed\n");
 559                 goto fail1;
 560         }
 561
 562         if (cpu_is_omap34xx()) {
 563                 dss.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
 564                 if (IS_ERR(dss.dpll4_m4_ck)) {
 565                         DSSERR("Failed to get dpll4_m4_ck\n");
 566                         r = PTR_ERR(dss.dpll4_m4_ck);
 567                         goto fail2;
 568                 }
 569         }
 570
 571         dss_save_context();
 572
 573         rev = dss_read_reg(DSS_REVISION);
 574         printk(KERN_INFO "OMAP DSS rev %d.%d\n",
 575                         FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
 576
 577         return 0;
 578
 579 fail2:
 580         free_irq(INT_24XX_DSS_IRQ, NULL);
 581 fail1:
 582         iounmap(dss.base);
 583 fail0:
 584         return r;
 585 }
 586
 587 void dss_exit(void)
 588 {
 589         if (cpu_is_omap34xx())
 590                 clk_put(dss.dpll4_m4_ck);
 591
 592         free_irq(INT_24XX_DSS_IRQ, NULL);
 593
 594         iounmap(dss.base);
 595 }
 596