drivers/video/via/viamode.c

   1 /*
   2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
   4
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public
   7  * License as published by the Free Software Foundation;
   8  * either version 2, or (at your option) any later version.
   9
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE.See the GNU General Public License
  14  * for more details.
  15
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.,
  19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20  */
  21
  22 #include "global.h"
  23 struct res_map_refresh res_map_refresh_tbl[] = {
  24 /*hres, vres, vclock, vmode_refresh*/
  25         {480, 640, RES_480X640_60HZ_PIXCLOCK, 60},
  26         {640, 480, RES_640X480_60HZ_PIXCLOCK, 60},
  27         {640, 480, RES_640X480_75HZ_PIXCLOCK, 75},
  28         {640, 480, RES_640X480_85HZ_PIXCLOCK, 85},
  29         {640, 480, RES_640X480_100HZ_PIXCLOCK, 100},
  30         {640, 480, RES_640X480_120HZ_PIXCLOCK, 120},
  31         {720, 480, RES_720X480_60HZ_PIXCLOCK, 60},
  32         {720, 576, RES_720X576_60HZ_PIXCLOCK, 60},
  33         {800, 480, RES_800X480_60HZ_PIXCLOCK, 60},
  34         {800, 600, RES_800X600_60HZ_PIXCLOCK, 60},
  35         {800, 600, RES_800X600_75HZ_PIXCLOCK, 75},
  36         {800, 600, RES_800X600_85HZ_PIXCLOCK, 85},
  37         {800, 600, RES_800X600_100HZ_PIXCLOCK, 100},
  38         {800, 600, RES_800X600_120HZ_PIXCLOCK, 120},
  39         {848, 480, RES_848X480_60HZ_PIXCLOCK, 60},
  40         {856, 480, RES_856X480_60HZ_PIXCLOCK, 60},
  41         {1024, 512, RES_1024X512_60HZ_PIXCLOCK, 60},
  42         {1024, 600, RES_1024X600_60HZ_PIXCLOCK, 60},
  43         {1024, 768, RES_1024X768_60HZ_PIXCLOCK, 60},
  44         {1024, 768, RES_1024X768_75HZ_PIXCLOCK, 75},
  45         {1024, 768, RES_1024X768_85HZ_PIXCLOCK, 85},
  46         {1024, 768, RES_1024X768_100HZ_PIXCLOCK, 100},
  47 /*  {1152,864, RES_1152X864_70HZ_PIXCLOCK,  70},*/
  48         {1152, 864, RES_1152X864_75HZ_PIXCLOCK, 75},
  49         {1280, 768, RES_1280X768_60HZ_PIXCLOCK, 60},
  50         {1280, 800, RES_1280X800_60HZ_PIXCLOCK, 60},
  51         {1280, 960, RES_1280X960_60HZ_PIXCLOCK, 60},
  52         {1280, 1024, RES_1280X1024_60HZ_PIXCLOCK, 60},
  53         {1280, 1024, RES_1280X1024_75HZ_PIXCLOCK, 75},
  54         {1280, 1024, RES_1280X768_85HZ_PIXCLOCK, 85},
  55         {1440, 1050, RES_1440X1050_60HZ_PIXCLOCK, 60},
  56         {1600, 1200, RES_1600X1200_60HZ_PIXCLOCK, 60},
  57         {1600, 1200, RES_1600X1200_75HZ_PIXCLOCK, 75},
  58         {1280, 720, RES_1280X720_60HZ_PIXCLOCK, 60},
  59         {1920, 1080, RES_1920X1080_60HZ_PIXCLOCK, 60},
  60         {1400, 1050, RES_1400X1050_60HZ_PIXCLOCK, 60},
  61         {1400, 1050, RES_1400X1050_75HZ_PIXCLOCK, 75},
  62         {1368, 768, RES_1368X768_60HZ_PIXCLOCK, 60},
  63         {960, 600, RES_960X600_60HZ_PIXCLOCK, 60},
  64         {1000, 600, RES_1000X600_60HZ_PIXCLOCK, 60},
  65         {1024, 576, RES_1024X576_60HZ_PIXCLOCK, 60},
  66         {1088, 612, RES_1088X612_60HZ_PIXCLOCK, 60},
  67         {1152, 720, RES_1152X720_60HZ_PIXCLOCK, 60},
  68         {1200, 720, RES_1200X720_60HZ_PIXCLOCK, 60},
  69         {1280, 600, RES_1280X600_60HZ_PIXCLOCK, 60},
  70         {1280, 720, RES_1280X720_50HZ_PIXCLOCK, 50},
  71         {1280, 768, RES_1280X768_50HZ_PIXCLOCK, 50},
  72         {1360, 768, RES_1360X768_60HZ_PIXCLOCK, 60},
  73         {1366, 768, RES_1366X768_50HZ_PIXCLOCK, 50},
  74         {1366, 768, RES_1366X768_60HZ_PIXCLOCK, 60},
  75         {1440, 900, RES_1440X900_60HZ_PIXCLOCK, 60},
  76         {1440, 900, RES_1440X900_75HZ_PIXCLOCK, 75},
  77         {1600, 900, RES_1600X900_60HZ_PIXCLOCK, 60},
  78         {1600, 1024, RES_1600X1024_60HZ_PIXCLOCK, 60},
  79         {1680, 1050, RES_1680X1050_60HZ_PIXCLOCK, 60},
  80         {1680, 1050, RES_1680X1050_75HZ_PIXCLOCK, 75},
  81         {1792, 1344, RES_1792X1344_60HZ_PIXCLOCK, 60},
  82         {1856, 1392, RES_1856X1392_60HZ_PIXCLOCK, 60},
  83         {1920, 1200, RES_1920X1200_60HZ_PIXCLOCK, 60},
  84         {1920, 1440, RES_1920X1440_60HZ_PIXCLOCK, 60},
  85         {1920, 1440, RES_1920X1440_75HZ_PIXCLOCK, 75},
  86         {2048, 1536, RES_2048X1536_60HZ_PIXCLOCK, 60}
  87 };
  88
  89 struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
  90 {VIASR, SR15, 0x02, 0x02},
  91 {VIASR, SR16, 0xBF, 0x08},
  92 {VIASR, SR17, 0xFF, 0x1F},
  93 {VIASR, SR18, 0xFF, 0x4E},
  94 {VIASR, SR1A, 0xFB, 0x08},
  95 {VIASR, SR1E, 0x0F, 0x01},
  96 {VIASR, SR2A, 0xFF, 0x00},
  97 {VIACR, CR0A, 0xFF, 0x1E},      /* Cursor Start                        */
  98 {VIACR, CR0B, 0xFF, 0x00},      /* Cursor End                          */
  99 {VIACR, CR0E, 0xFF, 0x00},      /* Cursor Location High                */
 100 {VIACR, CR0F, 0xFF, 0x00},      /* Cursor Localtion Low                */
 101 {VIACR, CR32, 0xFF, 0x00},
 102 {VIACR, CR33, 0xFF, 0x00},
 103 {VIACR, CR35, 0xFF, 0x00},
 104 {VIACR, CR36, 0x08, 0x00},
 105 {VIACR, CR69, 0xFF, 0x00},
 106 {VIACR, CR6A, 0xFF, 0x40},
 107 {VIACR, CR6B, 0xFF, 0x00},
 108 {VIACR, CR6C, 0xFF, 0x00},
 109 {VIACR, CR7A, 0xFF, 0x01},      /* LCD Scaling Parameter 1             */
 110 {VIACR, CR7B, 0xFF, 0x02},      /* LCD Scaling Parameter 2             */
 111 {VIACR, CR7C, 0xFF, 0x03},      /* LCD Scaling Parameter 3             */
 112 {VIACR, CR7D, 0xFF, 0x04},      /* LCD Scaling Parameter 4             */
 113 {VIACR, CR7E, 0xFF, 0x07},      /* LCD Scaling Parameter 5             */
 114 {VIACR, CR7F, 0xFF, 0x0A},      /* LCD Scaling Parameter 6             */
 115 {VIACR, CR80, 0xFF, 0x0D},      /* LCD Scaling Parameter 7             */
 116 {VIACR, CR81, 0xFF, 0x13},      /* LCD Scaling Parameter 8             */
 117 {VIACR, CR82, 0xFF, 0x16},      /* LCD Scaling Parameter 9             */
 118 {VIACR, CR83, 0xFF, 0x19},      /* LCD Scaling Parameter 10            */
 119 {VIACR, CR84, 0xFF, 0x1C},      /* LCD Scaling Parameter 11            */
 120 {VIACR, CR85, 0xFF, 0x1D},      /* LCD Scaling Parameter 12            */
 121 {VIACR, CR86, 0xFF, 0x1E},      /* LCD Scaling Parameter 13            */
 122 {VIACR, CR87, 0xFF, 0x1F},      /* LCD Scaling Parameter 14            */
 123 {VIACR, CR88, 0xFF, 0x40},      /* LCD Panel Type                      */
 124 {VIACR, CR89, 0xFF, 0x00},      /* LCD Timing Control 0                */
 125 {VIACR, CR8A, 0xFF, 0x88},      /* LCD Timing Control 1                */
 126 {VIACR, CR8B, 0xFF, 0x69},      /* LCD Power Sequence Control 0        */
 127 {VIACR, CR8C, 0xFF, 0x57},      /* LCD Power Sequence Control 1        */
 128 {VIACR, CR8D, 0xFF, 0x00},      /* LCD Power Sequence Control 2        */
 129 {VIACR, CR8E, 0xFF, 0x7B},      /* LCD Power Sequence Control 3        */
 130 {VIACR, CR8F, 0xFF, 0x03},      /* LCD Power Sequence Control 4        */
 131 {VIACR, CR90, 0xFF, 0x30},      /* LCD Power Sequence Control 5        */
 132 {VIACR, CR91, 0xFF, 0xA0},      /* 24/12 bit LVDS Data off             */
 133 {VIACR, CR96, 0xFF, 0x00},
 134 {VIACR, CR97, 0xFF, 0x00},
 135 {VIACR, CR99, 0xFF, 0x00},
 136 {VIACR, CR9B, 0xFF, 0x00}
 137 };
 138
 139 /* Video Mode Table for VT3314 chipset*/
 140 /* Common Setting for Video Mode */
 141 struct io_reg CN700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
 142 {VIASR, SR15, 0x02, 0x02},
 143 {VIASR, SR16, 0xBF, 0x08},
 144 {VIASR, SR17, 0xFF, 0x1F},
 145 {VIASR, SR18, 0xFF, 0x4E},
 146 {VIASR, SR1A, 0xFB, 0x82},
 147 {VIASR, SR1B, 0xFF, 0xF0},
 148 {VIASR, SR1F, 0xFF, 0x00},
 149 {VIASR, SR1E, 0xFF, 0x01},
 150 {VIASR, SR22, 0xFF, 0x1F},
 151 {VIASR, SR2A, 0x0F, 0x00},
 152 {VIASR, SR2E, 0xFF, 0xFF},
 153 {VIASR, SR3F, 0xFF, 0xFF},
 154 {VIASR, SR40, 0xF7, 0x00},
 155 {VIASR, CR30, 0xFF, 0x04},
 156 {VIACR, CR32, 0xFF, 0x00},
 157 {VIACR, CR33, 0x7F, 0x00},
 158 {VIACR, CR35, 0xFF, 0x00},
 159 {VIACR, CR36, 0xFF, 0x31},
 160 {VIACR, CR41, 0xFF, 0x80},
 161 {VIACR, CR42, 0xFF, 0x00},
 162 {VIACR, CR55, 0x80, 0x00},
 163 {VIACR, CR5D, 0x80, 0x00},      /*Horizontal Retrace Start bit[11] should be 0*/
 164 {VIACR, CR68, 0xFF, 0x67},      /* Default FIFO For IGA2 */
 165 {VIACR, CR69, 0xFF, 0x00},
 166 {VIACR, CR6A, 0xFD, 0x40},
 167 {VIACR, CR6B, 0xFF, 0x00},
 168 {VIACR, CR6C, 0xFF, 0x00},
 169 {VIACR, CR77, 0xFF, 0x00},      /* LCD scaling Factor */
 170 {VIACR, CR78, 0xFF, 0x00},      /* LCD scaling Factor */
 171 {VIACR, CR79, 0xFF, 0x00},      /* LCD scaling Factor */
 172 {VIACR, CR9F, 0x03, 0x00},      /* LCD scaling Factor */
 173 {VIACR, CR7A, 0xFF, 0x01},      /* LCD Scaling Parameter 1 */
 174 {VIACR, CR7B, 0xFF, 0x02},      /* LCD Scaling Parameter 2 */
 175 {VIACR, CR7C, 0xFF, 0x03},      /* LCD Scaling Parameter 3 */
 176 {VIACR, CR7D, 0xFF, 0x04},      /* LCD Scaling Parameter 4 */
 177 {VIACR, CR7E, 0xFF, 0x07},      /* LCD Scaling Parameter 5 */
 178 {VIACR, CR7F, 0xFF, 0x0A},      /* LCD Scaling Parameter 6 */
 179 {VIACR, CR80, 0xFF, 0x0D},      /* LCD Scaling Parameter 7 */
 180 {VIACR, CR81, 0xFF, 0x13},      /* LCD Scaling Parameter 8 */
 181 {VIACR, CR82, 0xFF, 0x16},      /* LCD Scaling Parameter 9 */
 182 {VIACR, CR83, 0xFF, 0x19},      /* LCD Scaling Parameter 10 */
 183 {VIACR, CR84, 0xFF, 0x1C},      /* LCD Scaling Parameter 11 */
 184 {VIACR, CR85, 0xFF, 0x1D},      /* LCD Scaling Parameter 12 */
 185 {VIACR, CR86, 0xFF, 0x1E},      /* LCD Scaling Parameter 13 */
 186 {VIACR, CR87, 0xFF, 0x1F},      /* LCD Scaling Parameter 14 */
 187 {VIACR, CR88, 0xFF, 0x40},      /* LCD Panel Type */
 188 {VIACR, CR89, 0xFF, 0x00},      /* LCD Timing Control 0 */
 189 {VIACR, CR8A, 0xFF, 0x88},      /* LCD Timing Control 1 */
 190 {VIACR, CR8B, 0xFF, 0x5D},      /* LCD Power Sequence Control 0 */
 191 {VIACR, CR8C, 0xFF, 0x2B},      /* LCD Power Sequence Control 1 */
 192 {VIACR, CR8D, 0xFF, 0x6F},      /* LCD Power Sequence Control 2 */
 193 {VIACR, CR8E, 0xFF, 0x2B},      /* LCD Power Sequence Control 3 */
 194 {VIACR, CR8F, 0xFF, 0x01},      /* LCD Power Sequence Control 4 */
 195 {VIACR, CR90, 0xFF, 0x01},      /* LCD Power Sequence Control 5 */
 196 {VIACR, CR91, 0xFF, 0xA0},      /* 24/12 bit LVDS Data off */
 197 {VIACR, CR96, 0xFF, 0x00},
 198 {VIACR, CR97, 0xFF, 0x00},
 199 {VIACR, CR99, 0xFF, 0x00},
 200 {VIACR, CR9B, 0xFF, 0x00},
 201 {VIACR, CR9D, 0xFF, 0x80},
 202 {VIACR, CR9E, 0xFF, 0x80}
 203 };
 204
 205 struct io_reg KM400_ModeXregs[] = {
 206         {VIASR, SR10, 0xFF, 0x01},      /* Unlock Register                 */
 207         {VIASR, SR16, 0xFF, 0x08},      /* Display FIFO threshold Control  */
 208         {VIASR, SR17, 0xFF, 0x1F},      /* Display FIFO Control            */
 209         {VIASR, SR18, 0xFF, 0x4E},      /* GFX PREQ threshold              */
 210         {VIASR, SR1A, 0xFF, 0x0a},      /* GFX PREQ threshold              */
 211         {VIASR, SR1F, 0xFF, 0x00},      /* Memory Control 0                */
 212         {VIASR, SR1B, 0xFF, 0xF0},      /* Power Management Control 0      */
 213         {VIASR, SR1E, 0xFF, 0x01},      /* Power Management Control        */
 214         {VIASR, SR20, 0xFF, 0x00},      /* Sequencer Arbiter Control 0     */
 215         {VIASR, SR21, 0xFF, 0x00},      /* Sequencer Arbiter Control 1     */
 216         {VIASR, SR22, 0xFF, 0x1F},      /* Display Arbiter Control 1       */
 217         {VIASR, SR2A, 0xFF, 0x00},      /* Power Management Control 5      */
 218         {VIASR, SR2D, 0xFF, 0xFF},      /* Power Management Control 1      */
 219         {VIASR, SR2E, 0xFF, 0xFF},      /* Power Management Control 2      */
 220         {VIACR, CR0A, 0xFF, 0x1E},      /* Cursor Start                    */
 221         {VIACR, CR0B, 0xFF, 0x00},      /* Cursor End                      */
 222         {VIACR, CR0E, 0xFF, 0x00},      /* Cursor Location High            */
 223         {VIACR, CR0F, 0xFF, 0x00},      /* Cursor Localtion Low            */
 224         {VIACR, CR33, 0xFF, 0x00},
 225         {VIACR, CR55, 0x80, 0x00},
 226         {VIACR, CR5D, 0x80, 0x00},
 227         {VIACR, CR36, 0xFF, 0x01},      /* Power Mangement 3                  */
 228         {VIACR, CR68, 0xFF, 0x67},      /* Default FIFO For IGA2              */
 229         {VIACR, CR6A, 0x20, 0x20},      /* Extended FIFO On                   */
 230         {VIACR, CR7A, 0xFF, 0x01},      /* LCD Scaling Parameter 1            */
 231         {VIACR, CR7B, 0xFF, 0x02},      /* LCD Scaling Parameter 2            */
 232         {VIACR, CR7C, 0xFF, 0x03},      /* LCD Scaling Parameter 3            */
 233         {VIACR, CR7D, 0xFF, 0x04},      /* LCD Scaling Parameter 4            */
 234         {VIACR, CR7E, 0xFF, 0x07},      /* LCD Scaling Parameter 5            */
 235         {VIACR, CR7F, 0xFF, 0x0A},      /* LCD Scaling Parameter 6            */
 236         {VIACR, CR80, 0xFF, 0x0D},      /* LCD Scaling Parameter 7            */
 237         {VIACR, CR81, 0xFF, 0x13},      /* LCD Scaling Parameter 8            */
 238         {VIACR, CR82, 0xFF, 0x16},      /* LCD Scaling Parameter 9            */
 239         {VIACR, CR83, 0xFF, 0x19},      /* LCD Scaling Parameter 10           */
 240         {VIACR, CR84, 0xFF, 0x1C},      /* LCD Scaling Parameter 11           */
 241         {VIACR, CR85, 0xFF, 0x1D},      /* LCD Scaling Parameter 12           */
 242         {VIACR, CR86, 0xFF, 0x1E},      /* LCD Scaling Parameter 13           */
 243         {VIACR, CR87, 0xFF, 0x1F},      /* LCD Scaling Parameter 14           */
 244         {VIACR, CR88, 0xFF, 0x40},      /* LCD Panel Type                     */
 245         {VIACR, CR89, 0xFF, 0x00},      /* LCD Timing Control 0               */
 246         {VIACR, CR8A, 0xFF, 0x88},      /* LCD Timing Control 1               */
 247         {VIACR, CR8B, 0xFF, 0x2D},      /* LCD Power Sequence Control 0       */
 248         {VIACR, CR8C, 0xFF, 0x2D},      /* LCD Power Sequence Control 1       */
 249         {VIACR, CR8D, 0xFF, 0xC8},      /* LCD Power Sequence Control 2       */
 250         {VIACR, CR8E, 0xFF, 0x36},      /* LCD Power Sequence Control 3       */
 251         {VIACR, CR8F, 0xFF, 0x00},      /* LCD Power Sequence Control 4       */
 252         {VIACR, CR90, 0xFF, 0x10},      /* LCD Power Sequence Control 5       */
 253         {VIACR, CR91, 0xFF, 0xA0},      /* 24/12 bit LVDS Data off            */
 254         {VIACR, CR96, 0xFF, 0x03},      /* DVP0        ; DVP0 Clock Skew */
 255         {VIACR, CR97, 0xFF, 0x03},      /* DFP high    ; DFPH Clock Skew */
 256         {VIACR, CR99, 0xFF, 0x03},      /* DFP low           ; DFPL Clock Skew*/
 257         {VIACR, CR9B, 0xFF, 0x07}       /* DVI on DVP1       ; DVP1 Clock Skew*/
 258 };
 259
 260 /* For VT3324: Common Setting for Video Mode */
 261 struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
 262 {VIASR, SR15, 0x02, 0x02},
 263 {VIASR, SR16, 0xBF, 0x08},
 264 {VIASR, SR17, 0xFF, 0x1F},
 265 {VIASR, SR18, 0xFF, 0x4E},
 266 {VIASR, SR1A, 0xFB, 0x08},
 267 {VIASR, SR1B, 0xFF, 0xF0},
 268 {VIASR, SR1E, 0xFF, 0x01},
 269 {VIASR, SR2A, 0xFF, 0x00},
 270 {VIASR, SR2D, 0xFF, 0xFF},      /* VCK and LCK PLL power on.           */
 271 {VIACR, CR0A, 0xFF, 0x1E},      /* Cursor Start                        */
 272 {VIACR, CR0B, 0xFF, 0x00},      /* Cursor End                          */
 273 {VIACR, CR0E, 0xFF, 0x00},      /* Cursor Location High                */
 274 {VIACR, CR0F, 0xFF, 0x00},      /* Cursor Localtion Low                */
 275 {VIACR, CR32, 0xFF, 0x00},
 276 {VIACR, CR33, 0xFF, 0x00},
 277 {VIACR, CR35, 0xFF, 0x00},
 278 {VIACR, CR36, 0x08, 0x00},
 279 {VIACR, CR47, 0xC8, 0x00},      /* Clear VCK Plus. */
 280 {VIACR, CR69, 0xFF, 0x00},
 281 {VIACR, CR6A, 0xFF, 0x40},
 282 {VIACR, CR6B, 0xFF, 0x00},
 283 {VIACR, CR6C, 0xFF, 0x00},
 284 {VIACR, CR7A, 0xFF, 0x01},      /* LCD Scaling Parameter 1             */
 285 {VIACR, CR7B, 0xFF, 0x02},      /* LCD Scaling Parameter 2             */
 286 {VIACR, CR7C, 0xFF, 0x03},      /* LCD Scaling Parameter 3             */
 287 {VIACR, CR7D, 0xFF, 0x04},      /* LCD Scaling Parameter 4             */
 288 {VIACR, CR7E, 0xFF, 0x07},      /* LCD Scaling Parameter 5             */
 289 {VIACR, CR7F, 0xFF, 0x0A},      /* LCD Scaling Parameter 6             */
 290 {VIACR, CR80, 0xFF, 0x0D},      /* LCD Scaling Parameter 7             */
 291 {VIACR, CR81, 0xFF, 0x13},      /* LCD Scaling Parameter 8             */
 292 {VIACR, CR82, 0xFF, 0x16},      /* LCD Scaling Parameter 9             */
 293 {VIACR, CR83, 0xFF, 0x19},      /* LCD Scaling Parameter 10            */
 294 {VIACR, CR84, 0xFF, 0x1C},      /* LCD Scaling Parameter 11            */
 295 {VIACR, CR85, 0xFF, 0x1D},      /* LCD Scaling Parameter 12            */
 296 {VIACR, CR86, 0xFF, 0x1E},      /* LCD Scaling Parameter 13            */
 297 {VIACR, CR87, 0xFF, 0x1F},      /* LCD Scaling Parameter 14            */
 298 {VIACR, CR88, 0xFF, 0x40},      /* LCD Panel Type                      */
 299 {VIACR, CR89, 0xFF, 0x00},      /* LCD Timing Control 0                */
 300 {VIACR, CR8A, 0xFF, 0x88},      /* LCD Timing Control 1                */
 301 {VIACR, CRD4, 0xFF, 0x81},      /* Second power sequence control       */
 302 {VIACR, CR8B, 0xFF, 0x5D},      /* LCD Power Sequence Control 0        */
 303 {VIACR, CR8C, 0xFF, 0x2B},      /* LCD Power Sequence Control 1        */
 304 {VIACR, CR8D, 0xFF, 0x6F},      /* LCD Power Sequence Control 2        */
 305 {VIACR, CR8E, 0xFF, 0x2B},      /* LCD Power Sequence Control 3        */
 306 {VIACR, CR8F, 0xFF, 0x01},      /* LCD Power Sequence Control 4        */
 307 {VIACR, CR90, 0xFF, 0x01},      /* LCD Power Sequence Control 5        */
 308 {VIACR, CR91, 0xFF, 0x80},      /* 24/12 bit LVDS Data off             */
 309 {VIACR, CR96, 0xFF, 0x00},
 310 {VIACR, CR97, 0xFF, 0x00},
 311 {VIACR, CR99, 0xFF, 0x00},
 312 {VIACR, CR9B, 0xFF, 0x00}
 313 };
 314
 315 struct io_reg VX855_ModeXregs[] = {
 316 {VIASR, SR10, 0xFF, 0x01},
 317 {VIASR, SR15, 0x02, 0x02},
 318 {VIASR, SR16, 0xBF, 0x08},
 319 {VIASR, SR17, 0xFF, 0x1F},
 320 {VIASR, SR18, 0xFF, 0x4E},
 321 {VIASR, SR1A, 0xFB, 0x08},
 322 {VIASR, SR1B, 0xFF, 0xF0},
 323 {VIASR, SR1E, 0x07, 0x01},
 324 {VIASR, SR2A, 0xF0, 0x00},
 325 {VIASR, SR58, 0xFF, 0x00},
 326 {VIASR, SR59, 0xFF, 0x00},
 327 {VIASR, SR2D, 0xFF, 0xFF},      /* VCK and LCK PLL power on.           */
 328 {VIACR, CR09, 0xFF, 0x00},      /* Initial CR09=0*/
 329 {VIACR, CR11, 0x8F, 0x00},      /* IGA1 initial  Vertical end       */
 330 {VIACR, CR17, 0x7F, 0x00},      /* IGA1 CRT Mode control init   */
 331 {VIACR, CR0A, 0xFF, 0x1E},      /* Cursor Start                        */
 332 {VIACR, CR0B, 0xFF, 0x00},      /* Cursor End                          */
 333 {VIACR, CR0E, 0xFF, 0x00},      /* Cursor Location High                */
 334 {VIACR, CR0F, 0xFF, 0x00},      /* Cursor Localtion Low                */
 335 {VIACR, CR32, 0xFF, 0x00},
 336 {VIACR, CR33, 0x7F, 0x00},
 337 {VIACR, CR35, 0xFF, 0x00},
 338 {VIACR, CR36, 0x08, 0x00},
 339 {VIACR, CR69, 0xFF, 0x00},
 340 {VIACR, CR6A, 0xFD, 0x60},
 341 {VIACR, CR6B, 0xFF, 0x00},
 342 {VIACR, CR6C, 0xFF, 0x00},
 343 {VIACR, CR7A, 0xFF, 0x01},          /* LCD Scaling Parameter 1             */
 344 {VIACR, CR7B, 0xFF, 0x02},          /* LCD Scaling Parameter 2             */
 345 {VIACR, CR7C, 0xFF, 0x03},          /* LCD Scaling Parameter 3             */
 346 {VIACR, CR7D, 0xFF, 0x04},          /* LCD Scaling Parameter 4             */
 347 {VIACR, CR7E, 0xFF, 0x07},          /* LCD Scaling Parameter 5             */
 348 {VIACR, CR7F, 0xFF, 0x0A},          /* LCD Scaling Parameter 6             */
 349 {VIACR, CR80, 0xFF, 0x0D},          /* LCD Scaling Parameter 7             */
 350 {VIACR, CR81, 0xFF, 0x13},          /* LCD Scaling Parameter 8             */
 351 {VIACR, CR82, 0xFF, 0x16},          /* LCD Scaling Parameter 9             */
 352 {VIACR, CR83, 0xFF, 0x19},          /* LCD Scaling Parameter 10            */
 353 {VIACR, CR84, 0xFF, 0x1C},          /* LCD Scaling Parameter 11            */
 354 {VIACR, CR85, 0xFF, 0x1D},          /* LCD Scaling Parameter 12            */
 355 {VIACR, CR86, 0xFF, 0x1E},          /* LCD Scaling Parameter 13            */
 356 {VIACR, CR87, 0xFF, 0x1F},          /* LCD Scaling Parameter 14            */
 357 {VIACR, CR88, 0xFF, 0x40},          /* LCD Panel Type                      */
 358 {VIACR, CR89, 0xFF, 0x00},          /* LCD Timing Control 0                */
 359 {VIACR, CR8A, 0xFF, 0x88},          /* LCD Timing Control 1                */
 360 {VIACR, CRD4, 0xFF, 0x81},          /* Second power sequence control       */
 361 {VIACR, CR91, 0xFF, 0x80},          /* 24/12 bit LVDS Data off             */
 362 {VIACR, CR96, 0xFF, 0x00},
 363 {VIACR, CR97, 0xFF, 0x00},
 364 {VIACR, CR99, 0xFF, 0x00},
 365 {VIACR, CR9B, 0xFF, 0x00},
 366 {VIACR, CRD2, 0xFF, 0xFF}           /* TMDS/LVDS control register.         */
 367 };
 368
 369 /* Video Mode Table */
 370 /* Common Setting for Video Mode */
 371 struct io_reg CLE266_ModeXregs[] = { {VIASR, SR1E, 0xF0, 0x00},
 372 {VIASR, SR2A, 0x0F, 0x00},
 373 {VIASR, SR15, 0x02, 0x02},
 374 {VIASR, SR16, 0xBF, 0x08},
 375 {VIASR, SR17, 0xFF, 0x1F},
 376 {VIASR, SR18, 0xFF, 0x4E},
 377 {VIASR, SR1A, 0xFB, 0x08},
 378
 379 {VIACR, CR32, 0xFF, 0x00},
 380 {VIACR, CR35, 0xFF, 0x00},
 381 {VIACR, CR36, 0x08, 0x00},
 382 {VIACR, CR6A, 0xFF, 0x80},
 383 {VIACR, CR6A, 0xFF, 0xC0},
 384
 385 {VIACR, CR55, 0x80, 0x00},
 386 {VIACR, CR5D, 0x80, 0x00},
 387
 388 {VIAGR, GR20, 0xFF, 0x00},
 389 {VIAGR, GR21, 0xFF, 0x00},
 390 {VIAGR, GR22, 0xFF, 0x00},
 391         /* LCD Parameters */
 392 {VIACR, CR7A, 0xFF, 0x01},      /* LCD Parameter 1 */
 393 {VIACR, CR7B, 0xFF, 0x02},      /* LCD Parameter 2 */
 394 {VIACR, CR7C, 0xFF, 0x03},      /* LCD Parameter 3 */
 395 {VIACR, CR7D, 0xFF, 0x04},      /* LCD Parameter 4 */
 396 {VIACR, CR7E, 0xFF, 0x07},      /* LCD Parameter 5 */
 397 {VIACR, CR7F, 0xFF, 0x0A},      /* LCD Parameter 6 */
 398 {VIACR, CR80, 0xFF, 0x0D},      /* LCD Parameter 7 */
 399 {VIACR, CR81, 0xFF, 0x13},      /* LCD Parameter 8 */
 400 {VIACR, CR82, 0xFF, 0x16},      /* LCD Parameter 9 */
 401 {VIACR, CR83, 0xFF, 0x19},      /* LCD Parameter 10 */
 402 {VIACR, CR84, 0xFF, 0x1C},      /* LCD Parameter 11 */
 403 {VIACR, CR85, 0xFF, 0x1D},      /* LCD Parameter 12 */
 404 {VIACR, CR86, 0xFF, 0x1E},      /* LCD Parameter 13 */
 405 {VIACR, CR87, 0xFF, 0x1F},      /* LCD Parameter 14 */
 406
 407 };
 408
 409 /* Mode:1024X768 */
 410 struct io_reg PM1024x768[] = { {VIASR, 0x16, 0xBF, 0x0C},
 411 {VIASR, 0x18, 0xFF, 0x4C}
 412 };
 413
 414 struct patch_table res_patch_table[] = {
 415         {VIA_RES_1024X768, ARRAY_SIZE(PM1024x768), PM1024x768}
 416 };
 417
 418 /* struct VPITTable {
 419         unsigned char  Misc;
 420         unsigned char  SR[StdSR];
 421         unsigned char  CR[StdCR];
 422         unsigned char  GR[StdGR];
 423         unsigned char  AR[StdAR];
 424  };*/
 425
 426 struct VPITTable VPIT = {
 427         /* Msic */
 428         0xC7,
 429         /* Sequencer */
 430         {0x01, 0x0F, 0x00, 0x0E},
 431         /* Graphic Controller */
 432         {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0F, 0xFF},
 433         /* Attribute Controller */
 434         {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
 435          0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
 436          0x01, 0x00, 0x0F, 0x00}
 437 };
 438
 439 /********************/
 440 /* Mode Table       */
 441 /********************/
 442
 443 /* 480x640 */
 444 struct crt_mode_table CRTM480x640[] = {
 445         /* r_rate,          vclk,              hsp,             vsp   */
 446         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 447         {REFRESH_60, CLK_25_175M, M480X640_R60_HSP, M480X640_R60_VSP,
 448          {624, 480, 480, 144, 504, 48, 663, 640, 640, 23, 641, 3} }     /* GTF*/
 449 };
 450
 451 /* 640x480*/
 452 struct crt_mode_table CRTM640x480[] = {
 453         /*r_rate,vclk,hsp,vsp */
 454         /*HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 455         {REFRESH_60, CLK_25_175M, M640X480_R60_HSP, M640X480_R60_VSP,
 456          {800, 640, 648, 144, 656, 96, 525, 480, 480, 45, 490, 2} },
 457         {REFRESH_75, CLK_31_500M, M640X480_R75_HSP, M640X480_R75_VSP,
 458          {840, 640, 640, 200, 656, 64, 500, 480, 480, 20, 481, 3} },
 459         {REFRESH_85, CLK_36_000M, M640X480_R85_HSP, M640X480_R85_VSP,
 460          {832, 640, 640, 192, 696, 56, 509, 480, 480, 29, 481, 3} },
 461         {REFRESH_100, CLK_43_163M, M640X480_R100_HSP, M640X480_R100_VSP,
 462          {848, 640, 640, 208, 680, 64, 509, 480, 480, 29, 481, 3} }, /*GTF*/
 463             {REFRESH_120, CLK_52_406M, M640X480_R120_HSP,
 464              M640X480_R120_VSP,
 465              {848, 640, 640, 208, 680, 64, 515, 480, 480, 35, 481,
 466               3} } /*GTF*/
 467 };
 468
 469 /*720x480 (GTF)*/
 470 struct crt_mode_table CRTM720x480[] = {
 471         /*r_rate,vclk,hsp,vsp      */
 472         /*HT, HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 473         {REFRESH_60, CLK_26_880M, M720X480_R60_HSP, M720X480_R60_VSP,
 474          {896, 720, 720, 176, 736, 72, 497, 480, 480, 17, 481, 3} }
 475
 476 };
 477
 478 /*720x576 (GTF)*/
 479 struct crt_mode_table CRTM720x576[] = {
 480         /*r_rate,vclk,hsp,vsp */
 481         /*HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 482         {REFRESH_60, CLK_32_668M, M720X576_R60_HSP, M720X576_R60_VSP,
 483          {912, 720, 720, 192, 744, 72, 597, 576, 576, 21, 577, 3} }
 484 };
 485
 486 /* 800x480 (CVT) */
 487 struct crt_mode_table CRTM800x480[] = {
 488         /* r_rate,          vclk,              hsp,             vsp   */
 489         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 490         {REFRESH_60, CLK_29_581M, M800X480_R60_HSP, M800X480_R60_VSP,
 491          {992, 800, 800, 192, 824, 72, 500, 480, 480, 20, 483, 7} }
 492 };
 493
 494 /* 800x600*/
 495 struct crt_mode_table CRTM800x600[] = {
 496         /*r_rate,vclk,hsp,vsp     */
 497         /*HT,   HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 498         {REFRESH_60, CLK_40_000M, M800X600_R60_HSP, M800X600_R60_VSP,
 499          {1056, 800, 800, 256, 840, 128, 628, 600, 600, 28, 601, 4} },
 500         {REFRESH_75, CLK_49_500M, M800X600_R75_HSP, M800X600_R75_VSP,
 501          {1056, 800, 800, 256, 816, 80, 625, 600, 600, 25, 601, 3} },
 502         {REFRESH_85, CLK_56_250M, M800X600_R85_HSP, M800X600_R85_VSP,
 503          {1048, 800, 800, 248, 832, 64, 631, 600, 600, 31, 601, 3} },
 504         {REFRESH_100, CLK_68_179M, M800X600_R100_HSP, M800X600_R100_VSP,
 505          {1072, 800, 800, 272, 848, 88, 636, 600, 600, 36, 601, 3} },
 506         {REFRESH_120, CLK_83_950M, M800X600_R120_HSP,
 507                   M800X600_R120_VSP,
 508                   {1088, 800, 800, 288, 856, 88, 643, 600, 600, 43, 601,
 509                    3} }
 510 };
 511
 512 /* 848x480 (CVT) */
 513 struct crt_mode_table CRTM848x480[] = {
 514         /* r_rate,          vclk,              hsp,             vsp   */
 515         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 516         {REFRESH_60, CLK_31_500M, M848X480_R60_HSP, M848X480_R60_VSP,
 517          {1056, 848, 848, 208, 872, 80, 500, 480, 480, 20, 483, 5} }
 518 };
 519
 520 /*856x480 (GTF) convert to 852x480*/
 521 struct crt_mode_table CRTM852x480[] = {
 522         /*r_rate,vclk,hsp,vsp     */
 523         /*HT,   HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 524         {REFRESH_60, CLK_31_728M, M852X480_R60_HSP, M852X480_R60_VSP,
 525         {1064, 856, 856, 208, 872, 88, 497, 480, 480, 17, 481, 3} }
 526 };
 527
 528 /*1024x512 (GTF)*/
 529 struct crt_mode_table CRTM1024x512[] = {
 530         /*r_rate,vclk,hsp,vsp     */
 531         /*HT,   HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 532         {REFRESH_60, CLK_41_291M, M1024X512_R60_HSP, M1024X512_R60_VSP,
 533          {1296, 1024, 1024, 272, 1056, 104, 531, 512, 512, 19, 513, 3} }
 534
 535 };
 536
 537 /* 1024x600*/
 538 struct crt_mode_table CRTM1024x600[] = {
 539         /*r_rate,vclk,hsp,vsp */
 540         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 541         {REFRESH_60, CLK_48_875M, M1024X600_R60_HSP, M1024X600_R60_VSP,
 542          {1312, 1024, 1024, 288, 1064, 104, 622, 600, 600, 22, 601, 3} },
 543 };
 544
 545 /* 1024x768*/
 546 struct crt_mode_table CRTM1024x768[] = {
 547         /*r_rate,vclk,hsp,vsp */
 548         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 549         {REFRESH_60, CLK_65_000M, M1024X768_R60_HSP, M1024X768_R60_VSP,
 550         {1344, 1024, 1024, 320, 1048, 136, 806, 768, 768, 38, 771, 6} },
 551         {REFRESH_75, CLK_78_750M, M1024X768_R75_HSP, M1024X768_R75_VSP,
 552         {1312, 1024, 1024, 288, 1040, 96, 800, 768, 768, 32, 769, 3} },
 553         {REFRESH_85, CLK_94_500M, M1024X768_R85_HSP, M1024X768_R85_VSP,
 554         {1376, 1024, 1024, 352, 1072, 96, 808, 768, 768, 40, 769, 3} },
 555         {REFRESH_100, CLK_113_309M, M1024X768_R100_HSP, M1024X768_R100_VSP,
 556         {1392, 1024, 1024, 368, 1096, 112, 814, 768, 768, 46, 769, 3} }
 557 };
 558
 559 /* 1152x864*/
 560 struct crt_mode_table CRTM1152x864[] = {
 561         /*r_rate,vclk,hsp,vsp      */
 562         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 563         {REFRESH_75, CLK_108_000M, M1152X864_R75_HSP, M1152X864_R75_VSP,
 564          {1600, 1152, 1152, 448, 1216, 128, 900, 864, 864, 36, 865, 3} }
 565
 566 };
 567
 568 /* 1280x720 (HDMI 720P)*/
 569 struct crt_mode_table CRTM1280x720[] = {
 570         /*r_rate,vclk,hsp,vsp */
 571         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE      */
 572         {REFRESH_60, CLK_74_481M, M1280X720_R60_HSP, M1280X720_R60_VSP,
 573          {1648, 1280, 1280, 368, 1392, 40, 750, 720, 720, 30, 725, 5} },
 574         {REFRESH_50, CLK_60_466M, M1280X720_R50_HSP, M1280X720_R50_VSP,
 575          {1632, 1280, 1280, 352, 1328, 128, 741, 720, 720, 21, 721, 3} }
 576 };
 577
 578 /*1280x768 (GTF)*/
 579 struct crt_mode_table CRTM1280x768[] = {
 580         /*r_rate,vclk,hsp,vsp     */
 581         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 582         {REFRESH_60, CLK_80_136M, M1280X768_R60_HSP, M1280X768_R60_VSP,
 583          {1680, 1280, 1280, 400, 1344, 136, 795, 768, 768, 27, 769, 3} },
 584         {REFRESH_50, CLK_65_178M, M1280X768_R50_HSP, M1280X768_R50_VSP,
 585          {1648, 1280, 1280, 368, 1336, 128, 791, 768, 768, 23, 769, 3} }
 586 };
 587
 588 /* 1280x800 (CVT) */
 589 struct crt_mode_table CRTM1280x800[] = {
 590         /* r_rate,          vclk,              hsp,             vsp   */
 591         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 592         {REFRESH_60, CLK_83_375M, M1280X800_R60_HSP, M1280X800_R60_VSP,
 593          {1680, 1280, 1280, 400, 1352, 128, 831, 800, 800, 31, 803, 6} }
 594 };
 595
 596 /*1280x960*/
 597 struct crt_mode_table CRTM1280x960[] = {
 598         /*r_rate,vclk,hsp,vsp */
 599         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 600         {REFRESH_60, CLK_108_000M, M1280X960_R60_HSP, M1280X960_R60_VSP,
 601          {1800, 1280, 1280, 520, 1376, 112, 1000, 960, 960, 40, 961, 3} }
 602 };
 603
 604 /* 1280x1024*/
 605 struct crt_mode_table CRTM1280x1024[] = {
 606         /*r_rate,vclk,,hsp,vsp */
 607         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 608         {REFRESH_60, CLK_108_000M, M1280X1024_R60_HSP, M1280X1024_R60_VSP,
 609          {1688, 1280, 1280, 408, 1328, 112, 1066, 1024, 1024, 42, 1025,
 610           3} },
 611         {REFRESH_75, CLK_135_000M, M1280X1024_R75_HSP, M1280X1024_R75_VSP,
 612          {1688, 1280, 1280, 408, 1296, 144, 1066, 1024, 1024, 42, 1025,
 613           3} },
 614         {REFRESH_85, CLK_157_500M, M1280X1024_R85_HSP, M1280X1024_R85_VSP,
 615          {1728, 1280, 1280, 448, 1344, 160, 1072, 1024, 1024, 48, 1025, 3} }
 616 };
 617
 618 /* 1368x768 (GTF) */
 619 struct crt_mode_table CRTM1368x768[] = {
 620         /* r_rate,  vclk, hsp, vsp */
 621         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 622         {REFRESH_60, CLK_85_860M, M1368X768_R60_HSP, M1368X768_R60_VSP,
 623          {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} }
 624 };
 625
 626 /*1440x1050 (GTF)*/
 627 struct crt_mode_table CRTM1440x1050[] = {
 628         /*r_rate,vclk,hsp,vsp      */
 629         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 630         {REFRESH_60, CLK_125_104M, M1440X1050_R60_HSP, M1440X1050_R60_VSP,
 631          {1936, 1440, 1440, 496, 1536, 152, 1077, 1040, 1040, 37, 1041, 3} }
 632 };
 633
 634 /* 1600x1200*/
 635 struct crt_mode_table CRTM1600x1200[] = {
 636         /*r_rate,vclk,hsp,vsp */
 637         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 638         {REFRESH_60, CLK_162_000M, M1600X1200_R60_HSP, M1600X1200_R60_VSP,
 639          {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201,
 640           3} },
 641         {REFRESH_75, CLK_202_500M, M1600X1200_R75_HSP, M1600X1200_R75_VSP,
 642          {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201, 3} }
 643
 644 };
 645
 646 /* 1680x1050 (CVT) */
 647 struct crt_mode_table CRTM1680x1050[] = {
 648         /* r_rate,          vclk,              hsp,             vsp  */
 649         /* HT,  HA,  HBS, HBE, HSS, HSE,    VT,  VA,  VBS, VBE,  VSS, VSE */
 650         {REFRESH_60, CLK_146_760M, M1680x1050_R60_HSP, M1680x1050_R60_VSP,
 651          {2240, 1680, 1680, 560, 1784, 176, 1089, 1050, 1050, 39, 1053,
 652           6} },
 653         {REFRESH_75, CLK_187_000M, M1680x1050_R75_HSP, M1680x1050_R75_VSP,
 654          {2272, 1680, 1680, 592, 1800, 176, 1099, 1050, 1050, 49, 1053, 6} }
 655 };
 656
 657 /* 1680x1050 (CVT Reduce Blanking) */
 658 struct crt_mode_table CRTM1680x1050_RB[] = {
 659         /* r_rate,          vclk,              hsp,             vsp   */
 660         /* HT,  HA,  HBS, HBE, HSS, HSE,    VT,  VA,  VBS, VBE,  VSS, VSE */
 661         {REFRESH_60, CLK_119_000M, M1680x1050_RB_R60_HSP,
 662          M1680x1050_RB_R60_VSP,
 663          {1840, 1680, 1680, 160, 1728, 32, 1080, 1050, 1050, 30, 1053, 6} }
 664 };
 665
 666 /* 1920x1080 (CVT)*/
 667 struct crt_mode_table CRTM1920x1080[] = {
 668         /*r_rate,vclk,hsp,vsp */
 669         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 670         {REFRESH_60, CLK_172_798M, M1920X1080_R60_HSP, M1920X1080_R60_VSP,
 671          {2576, 1920, 1920, 656, 2048, 200, 1120, 1080, 1080, 40, 1083, 5} }
 672 };
 673
 674 /* 1920x1080 (CVT with Reduce Blanking) */
 675 struct crt_mode_table CRTM1920x1080_RB[] = {
 676         /* r_rate,          vclk,              hsp,             vsp   */
 677         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 678         {REFRESH_60, CLK_138_400M, M1920X1080_RB_R60_HSP,
 679          M1920X1080_RB_R60_VSP,
 680          {2080, 1920, 1920, 160, 1968, 32, 1111, 1080, 1080, 31, 1083, 5} }
 681 };
 682
 683 /* 1920x1440*/
 684 struct crt_mode_table CRTM1920x1440[] = {
 685         /*r_rate,vclk,hsp,vsp */
 686         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 687         {REFRESH_60, CLK_234_000M, M1920X1440_R60_HSP, M1920X1440_R60_VSP,
 688          {2600, 1920, 1920, 680, 2048, 208, 1500, 1440, 1440, 60, 1441,
 689           3} },
 690         {REFRESH_75, CLK_297_500M, M1920X1440_R75_HSP, M1920X1440_R75_VSP,
 691          {2640, 1920, 1920, 720, 2064, 224, 1500, 1440, 1440, 60, 1441, 3} }
 692 };
 693
 694 /* 1400x1050 (CVT) */
 695 struct crt_mode_table CRTM1400x1050[] = {
 696         /* r_rate,          vclk,              hsp,             vsp   */
 697         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
 698         {REFRESH_60, CLK_121_750M, M1400X1050_R60_HSP, M1400X1050_R60_VSP,
 699          {1864, 1400, 1400, 464, 1488, 144, 1089, 1050, 1050, 39, 1053,
 700           4} },
 701         {REFRESH_75, CLK_156_000M, M1400X1050_R75_HSP, M1400X1050_R75_VSP,
 702          {1896, 1400, 1400, 496, 1504, 144, 1099, 1050, 1050, 49, 1053, 4} }
 703 };
 704
 705 /* 1400x1050 (CVT Reduce Blanking) */
 706 struct crt_mode_table CRTM1400x1050_RB[] = {
 707         /* r_rate,          vclk,              hsp,             vsp   */
 708         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
 709         {REFRESH_60, CLK_101_000M, M1400X1050_RB_R60_HSP,
 710          M1400X1050_RB_R60_VSP,
 711          {1560, 1400, 1400, 160, 1448, 32, 1080, 1050, 1050, 30, 1053, 4} }
 712 };
 713
 714 /* 960x600 (CVT) */
 715 struct crt_mode_table CRTM960x600[] = {
 716         /* r_rate,          vclk,              hsp,             vsp   */
 717         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 718         {REFRESH_60, CLK_45_250M, M960X600_R60_HSP, M960X600_R60_VSP,
 719          {1216, 960, 960, 256, 992, 96, 624, 600, 600, 24, 603, 6} }
 720 };
 721
 722 /* 1000x600 (GTF) */
 723 struct crt_mode_table CRTM1000x600[] = {
 724         /* r_rate,          vclk,              hsp,             vsp   */
 725         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 726         {REFRESH_60, CLK_48_000M, M1000X600_R60_HSP, M1000X600_R60_VSP,
 727          {1288, 1000, 1000, 288, 1040, 104, 622, 600, 600, 22, 601, 3} }
 728 };
 729
 730 /* 1024x576 (GTF) */
 731 struct crt_mode_table CRTM1024x576[] = {
 732         /* r_rate,          vclk,              hsp,             vsp   */
 733         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 734         {REFRESH_60, CLK_46_996M, M1024X576_R60_HSP, M1024X576_R60_VSP,
 735          {1312, 1024, 1024, 288, 1064, 104, 597, 576, 576, 21, 577, 3} }
 736 };
 737
 738 /* 1088x612 (CVT) */
 739 struct crt_mode_table CRTM1088x612[] = {
 740         /* r_rate,          vclk,              hsp,             vsp   */
 741         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 742         {REFRESH_60, CLK_52_977M, M1088X612_R60_HSP, M1088X612_R60_VSP,
 743          {1392, 1088, 1088, 304, 1136, 104, 636, 612, 612, 24, 615, 5} }
 744 };
 745
 746 /* 1152x720 (CVT) */
 747 struct crt_mode_table CRTM1152x720[] = {
 748         /* r_rate,          vclk,              hsp,             vsp   */
 749         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 750         {REFRESH_60, CLK_66_750M, M1152X720_R60_HSP, M1152X720_R60_VSP,
 751          {1488, 1152, 1152, 336, 1208, 112, 748, 720, 720, 28, 723, 6} }
 752 };
 753
 754 /* 1200x720 (GTF) */
 755 struct crt_mode_table CRTM1200x720[] = {
 756         /* r_rate,          vclk,              hsp,             vsp   */
 757         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 758         {REFRESH_60, CLK_70_159M, M1200X720_R60_HSP, M1200X720_R60_VSP,
 759          {1568, 1200, 1200, 368, 1256, 128, 746, 720, 720, 26, 721, 3} }
 760 };
 761
 762 /* 1280x600 (GTF) */
 763 struct crt_mode_table CRTM1280x600[] = {
 764         /* r_rate,          vclk,              hsp,             vsp   */
 765         /* HT,  HA,  HBS, HBE,  HSS, HSE, VT,  VA,  VBS, VBE,  VSS, VSE */
 766         {REFRESH_60, CLK_61_500M, M1280x600_R60_HSP, M1280x600_R60_VSP,
 767          {1648, 1280, 1280, 368, 1336, 128, 622, 600, 600, 22, 601, 3} }
 768 };
 769
 770 /* 1360x768 (CVT) */
 771 struct crt_mode_table CRTM1360x768[] = {
 772         /* r_rate,          vclk,              hsp,             vsp   */
 773         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 774         {REFRESH_60, CLK_84_750M, M1360X768_R60_HSP, M1360X768_R60_VSP,
 775          {1776, 1360, 1360, 416, 1432, 136, 798, 768, 768, 30, 771, 5} }
 776 };
 777
 778 /* 1360x768 (CVT Reduce Blanking) */
 779 struct crt_mode_table CRTM1360x768_RB[] = {
 780         /* r_rate,          vclk,              hsp,             vsp   */
 781         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 782         {REFRESH_60, CLK_72_000M, M1360X768_RB_R60_HSP,
 783          M1360X768_RB_R60_VSP,
 784          {1520, 1360, 1360, 160, 1408, 32, 790, 768, 768, 22, 771, 5} }
 785 };
 786
 787 /* 1366x768 (GTF) */
 788 struct crt_mode_table CRTM1366x768[] = {
 789         /* r_rate,          vclk,              hsp,             vsp   */
 790         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 791         {REFRESH_60, CLK_85_860M, M1368X768_R60_HSP, M1368X768_R60_VSP,
 792          {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} },
 793         {REFRESH_50, CLK_69_924M, M1368X768_R50_HSP, M1368X768_R50_VSP,
 794          {1768, 1368, 1368, 400, 1424, 144, 791, 768, 768, 23, 769, 3} }
 795 };
 796
 797 /* 1440x900 (CVT) */
 798 struct crt_mode_table CRTM1440x900[] = {
 799         /* r_rate,          vclk,              hsp,             vsp   */
 800         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 801         {REFRESH_60, CLK_106_500M, M1440X900_R60_HSP, M1440X900_R60_VSP,
 802          {1904, 1440, 1440, 464, 1520, 152, 934, 900, 900, 34, 903, 6} },
 803         {REFRESH_75, CLK_136_700M, M1440X900_R75_HSP, M1440X900_R75_VSP,
 804          {1936, 1440, 1440, 496, 1536, 152, 942, 900, 900, 42, 903, 6} }
 805 };
 806
 807 /* 1440x900 (CVT Reduce Blanking) */
 808 struct crt_mode_table CRTM1440x900_RB[] = {
 809         /* r_rate,          vclk,              hsp,             vsp   */
 810         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 811         {REFRESH_60, CLK_88_750M, M1440X900_RB_R60_HSP,
 812          M1440X900_RB_R60_VSP,
 813          {1600, 1440, 1440, 160, 1488, 32, 926, 900, 900, 26, 903, 6} }
 814 };
 815
 816 /* 1600x900 (CVT) */
 817 struct crt_mode_table CRTM1600x900[] = {
 818         /* r_rate,          vclk,              hsp,             vsp   */
 819         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 820         {REFRESH_60, CLK_118_840M, M1600X900_R60_HSP, M1600X900_R60_VSP,
 821          {2112, 1600, 1600, 512, 1688, 168, 934, 900, 900, 34, 903, 5} }
 822 };
 823
 824 /* 1600x900 (CVT Reduce Blanking) */
 825 struct crt_mode_table CRTM1600x900_RB[] = {
 826         /* r_rate,        vclk,           hsp,        vsp   */
 827         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 828         {REFRESH_60, CLK_97_750M, M1600X900_RB_R60_HSP,
 829          M1600X900_RB_R60_VSP,
 830          {1760, 1600, 1600, 160, 1648, 32, 926, 900, 900, 26, 903, 5} }
 831 };
 832
 833 /* 1600x1024 (GTF) */
 834 struct crt_mode_table CRTM1600x1024[] = {
 835         /* r_rate,          vclk,              hsp,             vsp   */
 836         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
 837         {REFRESH_60, CLK_136_700M, M1600X1024_R60_HSP, M1600X1024_R60_VSP,
 838          {2144, 1600, 1600, 544, 1704, 168, 1060, 1024, 1024, 36, 1025, 3} }
 839 };
 840
 841 /* 1792x1344 (DMT) */
 842 struct crt_mode_table CRTM1792x1344[] = {
 843         /* r_rate,          vclk,              hsp,             vsp   */
 844         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
 845         {REFRESH_60, CLK_204_000M, M1792x1344_R60_HSP, M1792x1344_R60_VSP,
 846          {2448, 1792, 1792, 656, 1920, 200, 1394, 1344, 1344, 50, 1345, 3} }
 847 };
 848
 849 /* 1856x1392 (DMT) */
 850 struct crt_mode_table CRTM1856x1392[] = {
 851         /* r_rate,          vclk,              hsp,             vsp   */
 852         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
 853         {REFRESH_60, CLK_218_500M, M1856x1392_R60_HSP, M1856x1392_R60_VSP,
 854          {2528, 1856, 1856, 672, 1952, 224, 1439, 1392, 1392, 47, 1393, 3} }
 855 };
 856
 857 /* 1920x1200 (CVT) */
 858 struct crt_mode_table CRTM1920x1200[] = {
 859         /* r_rate,          vclk,              hsp,             vsp   */
 860         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 861         {REFRESH_60, CLK_193_295M, M1920X1200_R60_HSP, M1920X1200_R60_VSP,
 862          {2592, 1920, 1920, 672, 2056, 200, 1245, 1200, 1200, 45, 1203, 6} }
 863 };
 864
 865 /* 1920x1200 (CVT with Reduce Blanking) */
 866 struct crt_mode_table CRTM1920x1200_RB[] = {
 867         /* r_rate,          vclk,              hsp,             vsp   */
 868         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 869         {REFRESH_60, CLK_153_920M, M1920X1200_RB_R60_HSP,
 870          M1920X1200_RB_R60_VSP,
 871          {2080, 1920, 1920, 160, 1968, 32, 1235, 1200, 1200, 35, 1203, 6} }
 872 };
 873
 874 /* 2048x1536 (CVT) */
 875 struct crt_mode_table CRTM2048x1536[] = {
 876         /* r_rate,          vclk,              hsp,             vsp   */
 877         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
 878         {REFRESH_60, CLK_267_250M, M2048x1536_R60_HSP, M2048x1536_R60_VSP,
 879          {2800, 2048, 2048, 752, 2200, 224, 1592, 1536, 1536, 56, 1539, 4} }
 880 };
 881
 882 /* Video Mode Table */
 883 /* struct VideoModeTable {*/
 884 /*  int                               ModeIndex;*/
 885 /*  struct crt_mode_table             *crtc;*/
 886 /*  int                               mode_array;*/
 887 /* };*/
 888 struct VideoModeTable CLE266Modes[] = {
 889         /* Display : 480x640 (GTF) */
 890         {VIA_RES_480X640, CRTM480x640, ARRAY_SIZE(CRTM480x640)},
 891
 892         /* Display : 640x480 */
 893         {VIA_RES_640X480, CRTM640x480, ARRAY_SIZE(CRTM640x480)},
 894
 895         /* Display : 720x480 (GTF) */
 896         {VIA_RES_720X480, CRTM720x480, ARRAY_SIZE(CRTM720x480)},
 897
 898         /* Display : 720x576 (GTF) */
 899         {VIA_RES_720X576, CRTM720x576, ARRAY_SIZE(CRTM720x576)},
 900
 901         /* Display : 800x600 */
 902         {VIA_RES_800X600, CRTM800x600, ARRAY_SIZE(CRTM800x600)},
 903
 904         /* Display : 800x480 (CVT) */
 905         {VIA_RES_800X480, CRTM800x480, ARRAY_SIZE(CRTM800x480)},
 906
 907         /* Display : 848x480 (CVT) */
 908         {VIA_RES_848X480, CRTM848x480, ARRAY_SIZE(CRTM848x480)},
 909
 910         /* Display : 852x480 (GTF) */
 911         {VIA_RES_856X480, CRTM852x480, ARRAY_SIZE(CRTM852x480)},
 912
 913         /* Display : 1024x512 (GTF) */
 914         {VIA_RES_1024X512, CRTM1024x512, ARRAY_SIZE(CRTM1024x512)},
 915
 916         /* Display : 1024x600 */
 917         {VIA_RES_1024X600, CRTM1024x600, ARRAY_SIZE(CRTM1024x600)},
 918
 919         /* Display : 1024x576 (GTF) */
 920         /*{ VIA_RES_1024X576, CRTM1024x576, ARRAY_SIZE(CRTM1024x576)}, */
 921
 922         /* Display : 1024x768 */
 923         {VIA_RES_1024X768, CRTM1024x768, ARRAY_SIZE(CRTM1024x768)},
 924
 925         /* Display : 1152x864 */
 926         {VIA_RES_1152X864, CRTM1152x864, ARRAY_SIZE(CRTM1152x864)},
 927
 928         /* Display : 1280x768 (GTF) */
 929         {VIA_RES_1280X768, CRTM1280x768, ARRAY_SIZE(CRTM1280x768)},
 930
 931         /* Display : 960x600 (CVT) */
 932         {VIA_RES_960X600, CRTM960x600, ARRAY_SIZE(CRTM960x600)},
 933
 934         /* Display : 1000x600 (GTF) */
 935         {VIA_RES_1000X600, CRTM1000x600, ARRAY_SIZE(CRTM1000x600)},
 936
 937         /* Display : 1024x576 (GTF) */
 938         {VIA_RES_1024X576, CRTM1024x576, ARRAY_SIZE(CRTM1024x576)},
 939
 940         /* Display : 1088x612 (GTF) */
 941         {VIA_RES_1088X612, CRTM1088x612, ARRAY_SIZE(CRTM1088x612)},
 942
 943         /* Display : 1152x720 (CVT) */
 944         {VIA_RES_1152X720, CRTM1152x720, ARRAY_SIZE(CRTM1152x720)},
 945
 946         /* Display : 1200x720 (GTF) */
 947         {VIA_RES_1200X720, CRTM1200x720, ARRAY_SIZE(CRTM1200x720)},
 948
 949         /* Display : 1280x600 (GTF) */
 950         {VIA_RES_1280X600, CRTM1280x600, ARRAY_SIZE(CRTM1280x600)},
 951
 952         /* Display : 1280x800 (CVT) */
 953         {VIA_RES_1280X800, CRTM1280x800, ARRAY_SIZE(CRTM1280x800)},
 954
 955         /* Display : 1280x800 (GTF) */
 956         /*{ M1280x800, CRTM1280x800, ARRAY_SIZE(CRTM1280x800)}, */
 957
 958         /* Display : 1280x960 */
 959         {VIA_RES_1280X960, CRTM1280x960, ARRAY_SIZE(CRTM1280x960)},
 960
 961         /* Display : 1280x1024 */
 962         {VIA_RES_1280X1024, CRTM1280x1024, ARRAY_SIZE(CRTM1280x1024)},
 963
 964         /* Display : 1360x768 (CVT) */
 965         {VIA_RES_1360X768, CRTM1360x768, ARRAY_SIZE(CRTM1360x768)},
 966
 967         /* Display : 1360x768 (CVT Reduce Blanking) */
 968         {VIA_RES_1360X768_RB, CRTM1360x768_RB,
 969          ARRAY_SIZE(CRTM1360x768_RB)},
 970
 971         /* Display : 1366x768 */
 972         {VIA_RES_1366X768, CRTM1366x768, ARRAY_SIZE(CRTM1366x768)},
 973
 974         /* Display : 1368x768 (GTF) */
 975         /*{ M1368x768,CRTM1368x768,ARRAY_SIZE(CRTM1368x768)}, */
 976         /* Display : 1368x768 (GTF) */
 977         {VIA_RES_1368X768, CRTM1368x768, ARRAY_SIZE(CRTM1368x768)},
 978
 979         /* Display : 1440x900 (CVT) */
 980         {VIA_RES_1440X900, CRTM1440x900, ARRAY_SIZE(CRTM1440x900)},
 981
 982         /* Display : 1440x900 (CVT Reduce Blanking) */
 983         {VIA_RES_1440X900_RB, CRTM1440x900_RB,
 984          ARRAY_SIZE(CRTM1440x900_RB)},
 985
 986         /* Display : 1440x1050 (GTF) */
 987         {VIA_RES_1440X1050, CRTM1440x1050, ARRAY_SIZE(CRTM1440x1050)},
 988
 989         /* Display : 1400x1050 (CVT Reduce Blanking) */
 990         {VIA_RES_1400X1050_RB, CRTM1400x1050_RB,
 991          ARRAY_SIZE(CRTM1400x1050_RB)},
 992
 993         /* Display : 1600x900 (CVT) */
 994         {VIA_RES_1600X900, CRTM1600x900, ARRAY_SIZE(CRTM1600x900)},
 995
 996         /* Display : 1600x900 (CVT Reduce Blanking) */
 997         {VIA_RES_1600X900_RB, CRTM1600x900_RB,
 998          ARRAY_SIZE(CRTM1600x900_RB)},
 999
1000         /* Display : 1600x1024 (GTF) */
1001         {VIA_RES_1600X1024, CRTM1600x1024, ARRAY_SIZE(CRTM1600x1024)},
1002
1003         /* Display : 1600x1200 */
1004         {VIA_RES_1600X1200, CRTM1600x1200, ARRAY_SIZE(CRTM1600x1200)},
1005
1006         /* Display : 1680x1050 (CVT) */
1007         {VIA_RES_1680X1050, CRTM1680x1050, ARRAY_SIZE(CRTM1680x1050)},
1008
1009         /* Display : 1680x1050 (CVT Reduce Blanking) */
1010         {VIA_RES_1680X1050_RB, CRTM1680x1050_RB,
1011          ARRAY_SIZE(CRTM1680x1050_RB)},
1012
1013         /* Display : 1792x1344 (DMT) */
1014         {VIA_RES_1792X1344, CRTM1792x1344, ARRAY_SIZE(CRTM1792x1344)},
1015
1016         /* Display : 1856x1392 (DMT) */
1017         {VIA_RES_1856X1392, CRTM1856x1392, ARRAY_SIZE(CRTM1856x1392)},
1018
1019         /* Display : 1920x1440 */
1020         {VIA_RES_1920X1440, CRTM1920x1440, ARRAY_SIZE(CRTM1920x1440)},
1021
1022         /* Display : 2048x1536 */
1023         {VIA_RES_2048X1536, CRTM2048x1536, ARRAY_SIZE(CRTM2048x1536)},
1024
1025         /* Display : 1280x720 */
1026         {VIA_RES_1280X720, CRTM1280x720, ARRAY_SIZE(CRTM1280x720)},
1027
1028         /* Display : 1920x1080 (CVT) */
1029         {VIA_RES_1920X1080, CRTM1920x1080, ARRAY_SIZE(CRTM1920x1080)},
1030
1031         /* Display : 1920x1080 (CVT Reduce Blanking) */
1032         {VIA_RES_1920X1080_RB, CRTM1920x1080_RB,
1033          ARRAY_SIZE(CRTM1920x1080_RB)},
1034
1035         /* Display : 1920x1200 (CVT) */
1036         {VIA_RES_1920X1200, CRTM1920x1200, ARRAY_SIZE(CRTM1920x1200)},
1037
1038         /* Display : 1920x1200 (CVT Reduce Blanking) */
1039         {VIA_RES_1920X1200_RB, CRTM1920x1200_RB,
1040          ARRAY_SIZE(CRTM1920x1200_RB)},
1041
1042         /* Display : 1400x1050 (CVT) */
1043         {VIA_RES_1400X1050, CRTM1400x1050, ARRAY_SIZE(CRTM1400x1050)}
1044 };
1045 struct crt_mode_table CEAM1280x720[] = {
1046         {REFRESH_60, CLK_74_270M, M1280X720_CEA_R60_HSP,
1047          M1280X720_CEA_R60_VSP,
1048          /* HT,    HA,   HBS,  HBE,  HSS, HSE,  VT,   VA,  VBS, VBE, VSS, VSE */
1049          {1650, 1280, 1280, 370, 1390, 40, 750, 720, 720, 30, 725, 5} }
1050 };
1051 struct crt_mode_table CEAM1920x1080[] = {
1052         {REFRESH_60, CLK_148_500M, M1920X1080_CEA_R60_HSP,
1053          M1920X1080_CEA_R60_VSP,
1054          /* HT,    HA,   HBS,  HBE,  HSS, HSE,  VT,  VA, VBS, VBE,  VSS, VSE */
1055          {2200, 1920, 1920, 300, 2008, 44, 1125, 1080, 1080, 45, 1084, 5} }
1056 };
1057 struct VideoModeTable CEA_HDMI_Modes[] = {
1058         /* Display : 1280x720 */
1059         {VIA_RES_1280X720, CEAM1280x720, ARRAY_SIZE(CEAM1280x720)},
1060         {VIA_RES_1920X1080, CEAM1920x1080, ARRAY_SIZE(CEAM1920x1080)}
1061 };
1062
1063 int NUM_TOTAL_RES_MAP_REFRESH = ARRAY_SIZE(res_map_refresh_tbl);
1064 int NUM_TOTAL_CEA_MODES = ARRAY_SIZE(CEA_HDMI_Modes);
1065 int NUM_TOTAL_CN400_ModeXregs = ARRAY_SIZE(CN400_ModeXregs);
1066 int NUM_TOTAL_CN700_ModeXregs = ARRAY_SIZE(CN700_ModeXregs);
1067 int NUM_TOTAL_KM400_ModeXregs = ARRAY_SIZE(KM400_ModeXregs);
1068 int NUM_TOTAL_CX700_ModeXregs = ARRAY_SIZE(CX700_ModeXregs);
1069 int NUM_TOTAL_VX855_ModeXregs = ARRAY_SIZE(VX855_ModeXregs);
1070 int NUM_TOTAL_CLE266_ModeXregs = ARRAY_SIZE(CLE266_ModeXregs);
1071 int NUM_TOTAL_PATCH_MODE = ARRAY_SIZE(res_patch_table);
1072 int NUM_TOTAL_MODETABLE = ARRAY_SIZE(CLE266Modes);