5 * wm9081.c -- WM9081 ALSA SoC Audio driver
9 * Copyright 2009 Wolfson Microelectronics plc
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <sound/soc.h>
18 extern struct snd_soc_dai wm9081_dai
;
19 extern struct snd_soc_codec_device soc_codec_dev_wm9081
;
24 #define WM9081_SYSCLK_MCLK 1 /* Use MCLK without FLL */
25 #define WM9081_SYSCLK_FLL_MCLK 2 /* Use MCLK, enabling FLL if required */
30 #define WM9081_SOFTWARE_RESET 0x00
31 #define WM9081_ANALOGUE_LINEOUT 0x02
32 #define WM9081_ANALOGUE_SPEAKER_PGA 0x03
33 #define WM9081_VMID_CONTROL 0x04
34 #define WM9081_BIAS_CONTROL_1 0x05
35 #define WM9081_ANALOGUE_MIXER 0x07
36 #define WM9081_ANTI_POP_CONTROL 0x08
37 #define WM9081_ANALOGUE_SPEAKER_1 0x09
38 #define WM9081_ANALOGUE_SPEAKER_2 0x0A
39 #define WM9081_POWER_MANAGEMENT 0x0B
40 #define WM9081_CLOCK_CONTROL_1 0x0C
41 #define WM9081_CLOCK_CONTROL_2 0x0D
42 #define WM9081_CLOCK_CONTROL_3 0x0E
43 #define WM9081_FLL_CONTROL_1 0x10
44 #define WM9081_FLL_CONTROL_2 0x11
45 #define WM9081_FLL_CONTROL_3 0x12
46 #define WM9081_FLL_CONTROL_4 0x13
47 #define WM9081_FLL_CONTROL_5 0x14
48 #define WM9081_AUDIO_INTERFACE_1 0x16
49 #define WM9081_AUDIO_INTERFACE_2 0x17
50 #define WM9081_AUDIO_INTERFACE_3 0x18
51 #define WM9081_AUDIO_INTERFACE_4 0x19
52 #define WM9081_INTERRUPT_STATUS 0x1A
53 #define WM9081_INTERRUPT_STATUS_MASK 0x1B
54 #define WM9081_INTERRUPT_POLARITY 0x1C
55 #define WM9081_INTERRUPT_CONTROL 0x1D
56 #define WM9081_DAC_DIGITAL_1 0x1E
57 #define WM9081_DAC_DIGITAL_2 0x1F
58 #define WM9081_DRC_1 0x20
59 #define WM9081_DRC_2 0x21
60 #define WM9081_DRC_3 0x22
61 #define WM9081_DRC_4 0x23
62 #define WM9081_WRITE_SEQUENCER_1 0x26
63 #define WM9081_WRITE_SEQUENCER_2 0x27
64 #define WM9081_MW_SLAVE_1 0x28
65 #define WM9081_EQ_1 0x2A
66 #define WM9081_EQ_2 0x2B
67 #define WM9081_EQ_3 0x2C
68 #define WM9081_EQ_4 0x2D
69 #define WM9081_EQ_5 0x2E
70 #define WM9081_EQ_6 0x2F
71 #define WM9081_EQ_7 0x30
72 #define WM9081_EQ_8 0x31
73 #define WM9081_EQ_9 0x32
74 #define WM9081_EQ_10 0x33
75 #define WM9081_EQ_11 0x34
76 #define WM9081_EQ_12 0x35
77 #define WM9081_EQ_13 0x36
78 #define WM9081_EQ_14 0x37
79 #define WM9081_EQ_15 0x38
80 #define WM9081_EQ_16 0x39
81 #define WM9081_EQ_17 0x3A
82 #define WM9081_EQ_18 0x3B
83 #define WM9081_EQ_19 0x3C
84 #define WM9081_EQ_20 0x3D
86 #define WM9081_REGISTER_COUNT 55
87 #define WM9081_MAX_REGISTER 0x3D
94 * R0 (0x00) - Software Reset
96 #define WM9081_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */
97 #define WM9081_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */
98 #define WM9081_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */
101 * R2 (0x02) - Analogue Lineout
103 #define WM9081_LINEOUT_MUTE 0x0080 /* LINEOUT_MUTE */
104 #define WM9081_LINEOUT_MUTE_MASK 0x0080 /* LINEOUT_MUTE */
105 #define WM9081_LINEOUT_MUTE_SHIFT 7 /* LINEOUT_MUTE */
106 #define WM9081_LINEOUT_MUTE_WIDTH 1 /* LINEOUT_MUTE */
107 #define WM9081_LINEOUTZC 0x0040 /* LINEOUTZC */
108 #define WM9081_LINEOUTZC_MASK 0x0040 /* LINEOUTZC */
109 #define WM9081_LINEOUTZC_SHIFT 6 /* LINEOUTZC */
110 #define WM9081_LINEOUTZC_WIDTH 1 /* LINEOUTZC */
111 #define WM9081_LINEOUT_VOL_MASK 0x003F /* LINEOUT_VOL - [5:0] */
112 #define WM9081_LINEOUT_VOL_SHIFT 0 /* LINEOUT_VOL - [5:0] */
113 #define WM9081_LINEOUT_VOL_WIDTH 6 /* LINEOUT_VOL - [5:0] */
116 * R3 (0x03) - Analogue Speaker PGA
118 #define WM9081_SPKPGA_MUTE 0x0080 /* SPKPGA_MUTE */
119 #define WM9081_SPKPGA_MUTE_MASK 0x0080 /* SPKPGA_MUTE */
120 #define WM9081_SPKPGA_MUTE_SHIFT 7 /* SPKPGA_MUTE */
121 #define WM9081_SPKPGA_MUTE_WIDTH 1 /* SPKPGA_MUTE */
122 #define WM9081_SPKPGAZC 0x0040 /* SPKPGAZC */
123 #define WM9081_SPKPGAZC_MASK 0x0040 /* SPKPGAZC */
124 #define WM9081_SPKPGAZC_SHIFT 6 /* SPKPGAZC */
125 #define WM9081_SPKPGAZC_WIDTH 1 /* SPKPGAZC */
126 #define WM9081_SPKPGA_VOL_MASK 0x003F /* SPKPGA_VOL - [5:0] */
127 #define WM9081_SPKPGA_VOL_SHIFT 0 /* SPKPGA_VOL - [5:0] */
128 #define WM9081_SPKPGA_VOL_WIDTH 6 /* SPKPGA_VOL - [5:0] */
131 * R4 (0x04) - VMID Control
133 #define WM9081_VMID_BUF_ENA 0x0020 /* VMID_BUF_ENA */
134 #define WM9081_VMID_BUF_ENA_MASK 0x0020 /* VMID_BUF_ENA */
135 #define WM9081_VMID_BUF_ENA_SHIFT 5 /* VMID_BUF_ENA */
136 #define WM9081_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */
137 #define WM9081_VMID_RAMP 0x0008 /* VMID_RAMP */
138 #define WM9081_VMID_RAMP_MASK 0x0008 /* VMID_RAMP */
139 #define WM9081_VMID_RAMP_SHIFT 3 /* VMID_RAMP */
140 #define WM9081_VMID_RAMP_WIDTH 1 /* VMID_RAMP */
141 #define WM9081_VMID_SEL_MASK 0x0006 /* VMID_SEL - [2:1] */
142 #define WM9081_VMID_SEL_SHIFT 1 /* VMID_SEL - [2:1] */
143 #define WM9081_VMID_SEL_WIDTH 2 /* VMID_SEL - [2:1] */
144 #define WM9081_VMID_FAST_ST 0x0001 /* VMID_FAST_ST */
145 #define WM9081_VMID_FAST_ST_MASK 0x0001 /* VMID_FAST_ST */
146 #define WM9081_VMID_FAST_ST_SHIFT 0 /* VMID_FAST_ST */
147 #define WM9081_VMID_FAST_ST_WIDTH 1 /* VMID_FAST_ST */
150 * R5 (0x05) - Bias Control 1
152 #define WM9081_BIAS_SRC 0x0040 /* BIAS_SRC */
153 #define WM9081_BIAS_SRC_MASK 0x0040 /* BIAS_SRC */
154 #define WM9081_BIAS_SRC_SHIFT 6 /* BIAS_SRC */
155 #define WM9081_BIAS_SRC_WIDTH 1 /* BIAS_SRC */
156 #define WM9081_STBY_BIAS_LVL 0x0020 /* STBY_BIAS_LVL */
157 #define WM9081_STBY_BIAS_LVL_MASK 0x0020 /* STBY_BIAS_LVL */
158 #define WM9081_STBY_BIAS_LVL_SHIFT 5 /* STBY_BIAS_LVL */
159 #define WM9081_STBY_BIAS_LVL_WIDTH 1 /* STBY_BIAS_LVL */
160 #define WM9081_STBY_BIAS_ENA 0x0010 /* STBY_BIAS_ENA */
161 #define WM9081_STBY_BIAS_ENA_MASK 0x0010 /* STBY_BIAS_ENA */
162 #define WM9081_STBY_BIAS_ENA_SHIFT 4 /* STBY_BIAS_ENA */
163 #define WM9081_STBY_BIAS_ENA_WIDTH 1 /* STBY_BIAS_ENA */
164 #define WM9081_BIAS_LVL_MASK 0x000C /* BIAS_LVL - [3:2] */
165 #define WM9081_BIAS_LVL_SHIFT 2 /* BIAS_LVL - [3:2] */
166 #define WM9081_BIAS_LVL_WIDTH 2 /* BIAS_LVL - [3:2] */
167 #define WM9081_BIAS_ENA 0x0002 /* BIAS_ENA */
168 #define WM9081_BIAS_ENA_MASK 0x0002 /* BIAS_ENA */
169 #define WM9081_BIAS_ENA_SHIFT 1 /* BIAS_ENA */
170 #define WM9081_BIAS_ENA_WIDTH 1 /* BIAS_ENA */
171 #define WM9081_STARTUP_BIAS_ENA 0x0001 /* STARTUP_BIAS_ENA */
172 #define WM9081_STARTUP_BIAS_ENA_MASK 0x0001 /* STARTUP_BIAS_ENA */
173 #define WM9081_STARTUP_BIAS_ENA_SHIFT 0 /* STARTUP_BIAS_ENA */
174 #define WM9081_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */
177 * R7 (0x07) - Analogue Mixer
179 #define WM9081_DAC_SEL 0x0010 /* DAC_SEL */
180 #define WM9081_DAC_SEL_MASK 0x0010 /* DAC_SEL */
181 #define WM9081_DAC_SEL_SHIFT 4 /* DAC_SEL */
182 #define WM9081_DAC_SEL_WIDTH 1 /* DAC_SEL */
183 #define WM9081_IN2_VOL 0x0008 /* IN2_VOL */
184 #define WM9081_IN2_VOL_MASK 0x0008 /* IN2_VOL */
185 #define WM9081_IN2_VOL_SHIFT 3 /* IN2_VOL */
186 #define WM9081_IN2_VOL_WIDTH 1 /* IN2_VOL */
187 #define WM9081_IN2_ENA 0x0004 /* IN2_ENA */
188 #define WM9081_IN2_ENA_MASK 0x0004 /* IN2_ENA */
189 #define WM9081_IN2_ENA_SHIFT 2 /* IN2_ENA */
190 #define WM9081_IN2_ENA_WIDTH 1 /* IN2_ENA */
191 #define WM9081_IN1_VOL 0x0002 /* IN1_VOL */
192 #define WM9081_IN1_VOL_MASK 0x0002 /* IN1_VOL */
193 #define WM9081_IN1_VOL_SHIFT 1 /* IN1_VOL */
194 #define WM9081_IN1_VOL_WIDTH 1 /* IN1_VOL */
195 #define WM9081_IN1_ENA 0x0001 /* IN1_ENA */
196 #define WM9081_IN1_ENA_MASK 0x0001 /* IN1_ENA */
197 #define WM9081_IN1_ENA_SHIFT 0 /* IN1_ENA */
198 #define WM9081_IN1_ENA_WIDTH 1 /* IN1_ENA */
201 * R8 (0x08) - Anti Pop Control
203 #define WM9081_LINEOUT_DISCH 0x0004 /* LINEOUT_DISCH */
204 #define WM9081_LINEOUT_DISCH_MASK 0x0004 /* LINEOUT_DISCH */
205 #define WM9081_LINEOUT_DISCH_SHIFT 2 /* LINEOUT_DISCH */
206 #define WM9081_LINEOUT_DISCH_WIDTH 1 /* LINEOUT_DISCH */
207 #define WM9081_LINEOUT_VROI 0x0002 /* LINEOUT_VROI */
208 #define WM9081_LINEOUT_VROI_MASK 0x0002 /* LINEOUT_VROI */
209 #define WM9081_LINEOUT_VROI_SHIFT 1 /* LINEOUT_VROI */
210 #define WM9081_LINEOUT_VROI_WIDTH 1 /* LINEOUT_VROI */
211 #define WM9081_LINEOUT_CLAMP 0x0001 /* LINEOUT_CLAMP */
212 #define WM9081_LINEOUT_CLAMP_MASK 0x0001 /* LINEOUT_CLAMP */
213 #define WM9081_LINEOUT_CLAMP_SHIFT 0 /* LINEOUT_CLAMP */
214 #define WM9081_LINEOUT_CLAMP_WIDTH 1 /* LINEOUT_CLAMP */
217 * R9 (0x09) - Analogue Speaker 1
219 #define WM9081_SPK_DCGAIN_MASK 0x0038 /* SPK_DCGAIN - [5:3] */
220 #define WM9081_SPK_DCGAIN_SHIFT 3 /* SPK_DCGAIN - [5:3] */
221 #define WM9081_SPK_DCGAIN_WIDTH 3 /* SPK_DCGAIN - [5:3] */
222 #define WM9081_SPK_ACGAIN_MASK 0x0007 /* SPK_ACGAIN - [2:0] */
223 #define WM9081_SPK_ACGAIN_SHIFT 0 /* SPK_ACGAIN - [2:0] */
224 #define WM9081_SPK_ACGAIN_WIDTH 3 /* SPK_ACGAIN - [2:0] */
227 * R10 (0x0A) - Analogue Speaker 2
229 #define WM9081_SPK_MODE 0x0040 /* SPK_MODE */
230 #define WM9081_SPK_MODE_MASK 0x0040 /* SPK_MODE */
231 #define WM9081_SPK_MODE_SHIFT 6 /* SPK_MODE */
232 #define WM9081_SPK_MODE_WIDTH 1 /* SPK_MODE */
233 #define WM9081_SPK_INV_MUTE 0x0010 /* SPK_INV_MUTE */
234 #define WM9081_SPK_INV_MUTE_MASK 0x0010 /* SPK_INV_MUTE */
235 #define WM9081_SPK_INV_MUTE_SHIFT 4 /* SPK_INV_MUTE */
236 #define WM9081_SPK_INV_MUTE_WIDTH 1 /* SPK_INV_MUTE */
237 #define WM9081_OUT_SPK_CTRL 0x0008 /* OUT_SPK_CTRL */
238 #define WM9081_OUT_SPK_CTRL_MASK 0x0008 /* OUT_SPK_CTRL */
239 #define WM9081_OUT_SPK_CTRL_SHIFT 3 /* OUT_SPK_CTRL */
240 #define WM9081_OUT_SPK_CTRL_WIDTH 1 /* OUT_SPK_CTRL */
243 * R11 (0x0B) - Power Management
245 #define WM9081_TSHUT_ENA 0x0100 /* TSHUT_ENA */
246 #define WM9081_TSHUT_ENA_MASK 0x0100 /* TSHUT_ENA */
247 #define WM9081_TSHUT_ENA_SHIFT 8 /* TSHUT_ENA */
248 #define WM9081_TSHUT_ENA_WIDTH 1 /* TSHUT_ENA */
249 #define WM9081_TSENSE_ENA 0x0080 /* TSENSE_ENA */
250 #define WM9081_TSENSE_ENA_MASK 0x0080 /* TSENSE_ENA */
251 #define WM9081_TSENSE_ENA_SHIFT 7 /* TSENSE_ENA */
252 #define WM9081_TSENSE_ENA_WIDTH 1 /* TSENSE_ENA */
253 #define WM9081_TEMP_SHUT 0x0040 /* TEMP_SHUT */
254 #define WM9081_TEMP_SHUT_MASK 0x0040 /* TEMP_SHUT */
255 #define WM9081_TEMP_SHUT_SHIFT 6 /* TEMP_SHUT */
256 #define WM9081_TEMP_SHUT_WIDTH 1 /* TEMP_SHUT */
257 #define WM9081_LINEOUT_ENA 0x0010 /* LINEOUT_ENA */
258 #define WM9081_LINEOUT_ENA_MASK 0x0010 /* LINEOUT_ENA */
259 #define WM9081_LINEOUT_ENA_SHIFT 4 /* LINEOUT_ENA */
260 #define WM9081_LINEOUT_ENA_WIDTH 1 /* LINEOUT_ENA */
261 #define WM9081_SPKPGA_ENA 0x0004 /* SPKPGA_ENA */
262 #define WM9081_SPKPGA_ENA_MASK 0x0004 /* SPKPGA_ENA */
263 #define WM9081_SPKPGA_ENA_SHIFT 2 /* SPKPGA_ENA */
264 #define WM9081_SPKPGA_ENA_WIDTH 1 /* SPKPGA_ENA */
265 #define WM9081_SPK_ENA 0x0002 /* SPK_ENA */
266 #define WM9081_SPK_ENA_MASK 0x0002 /* SPK_ENA */
267 #define WM9081_SPK_ENA_SHIFT 1 /* SPK_ENA */
268 #define WM9081_SPK_ENA_WIDTH 1 /* SPK_ENA */
269 #define WM9081_DAC_ENA 0x0001 /* DAC_ENA */
270 #define WM9081_DAC_ENA_MASK 0x0001 /* DAC_ENA */
271 #define WM9081_DAC_ENA_SHIFT 0 /* DAC_ENA */
272 #define WM9081_DAC_ENA_WIDTH 1 /* DAC_ENA */
275 * R12 (0x0C) - Clock Control 1
277 #define WM9081_CLK_OP_DIV_MASK 0x1C00 /* CLK_OP_DIV - [12:10] */
278 #define WM9081_CLK_OP_DIV_SHIFT 10 /* CLK_OP_DIV - [12:10] */
279 #define WM9081_CLK_OP_DIV_WIDTH 3 /* CLK_OP_DIV - [12:10] */
280 #define WM9081_CLK_TO_DIV_MASK 0x0300 /* CLK_TO_DIV - [9:8] */
281 #define WM9081_CLK_TO_DIV_SHIFT 8 /* CLK_TO_DIV - [9:8] */
282 #define WM9081_CLK_TO_DIV_WIDTH 2 /* CLK_TO_DIV - [9:8] */
283 #define WM9081_MCLKDIV2 0x0080 /* MCLKDIV2 */
284 #define WM9081_MCLKDIV2_MASK 0x0080 /* MCLKDIV2 */
285 #define WM9081_MCLKDIV2_SHIFT 7 /* MCLKDIV2 */
286 #define WM9081_MCLKDIV2_WIDTH 1 /* MCLKDIV2 */
289 * R13 (0x0D) - Clock Control 2
291 #define WM9081_CLK_SYS_RATE_MASK 0x00F0 /* CLK_SYS_RATE - [7:4] */
292 #define WM9081_CLK_SYS_RATE_SHIFT 4 /* CLK_SYS_RATE - [7:4] */
293 #define WM9081_CLK_SYS_RATE_WIDTH 4 /* CLK_SYS_RATE - [7:4] */
294 #define WM9081_SAMPLE_RATE_MASK 0x000F /* SAMPLE_RATE - [3:0] */
295 #define WM9081_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [3:0] */
296 #define WM9081_SAMPLE_RATE_WIDTH 4 /* SAMPLE_RATE - [3:0] */
299 * R14 (0x0E) - Clock Control 3
301 #define WM9081_CLK_SRC_SEL 0x2000 /* CLK_SRC_SEL */
302 #define WM9081_CLK_SRC_SEL_MASK 0x2000 /* CLK_SRC_SEL */
303 #define WM9081_CLK_SRC_SEL_SHIFT 13 /* CLK_SRC_SEL */
304 #define WM9081_CLK_SRC_SEL_WIDTH 1 /* CLK_SRC_SEL */
305 #define WM9081_CLK_OP_ENA 0x0020 /* CLK_OP_ENA */
306 #define WM9081_CLK_OP_ENA_MASK 0x0020 /* CLK_OP_ENA */
307 #define WM9081_CLK_OP_ENA_SHIFT 5 /* CLK_OP_ENA */
308 #define WM9081_CLK_OP_ENA_WIDTH 1 /* CLK_OP_ENA */
309 #define WM9081_CLK_TO_ENA 0x0004 /* CLK_TO_ENA */
310 #define WM9081_CLK_TO_ENA_MASK 0x0004 /* CLK_TO_ENA */
311 #define WM9081_CLK_TO_ENA_SHIFT 2 /* CLK_TO_ENA */
312 #define WM9081_CLK_TO_ENA_WIDTH 1 /* CLK_TO_ENA */
313 #define WM9081_CLK_DSP_ENA 0x0002 /* CLK_DSP_ENA */
314 #define WM9081_CLK_DSP_ENA_MASK 0x0002 /* CLK_DSP_ENA */
315 #define WM9081_CLK_DSP_ENA_SHIFT 1 /* CLK_DSP_ENA */
316 #define WM9081_CLK_DSP_ENA_WIDTH 1 /* CLK_DSP_ENA */
317 #define WM9081_CLK_SYS_ENA 0x0001 /* CLK_SYS_ENA */
318 #define WM9081_CLK_SYS_ENA_MASK 0x0001 /* CLK_SYS_ENA */
319 #define WM9081_CLK_SYS_ENA_SHIFT 0 /* CLK_SYS_ENA */
320 #define WM9081_CLK_SYS_ENA_WIDTH 1 /* CLK_SYS_ENA */
323 * R16 (0x10) - FLL Control 1
325 #define WM9081_FLL_HOLD 0x0008 /* FLL_HOLD */
326 #define WM9081_FLL_HOLD_MASK 0x0008 /* FLL_HOLD */
327 #define WM9081_FLL_HOLD_SHIFT 3 /* FLL_HOLD */
328 #define WM9081_FLL_HOLD_WIDTH 1 /* FLL_HOLD */
329 #define WM9081_FLL_FRAC 0x0004 /* FLL_FRAC */
330 #define WM9081_FLL_FRAC_MASK 0x0004 /* FLL_FRAC */
331 #define WM9081_FLL_FRAC_SHIFT 2 /* FLL_FRAC */
332 #define WM9081_FLL_FRAC_WIDTH 1 /* FLL_FRAC */
333 #define WM9081_FLL_ENA 0x0001 /* FLL_ENA */
334 #define WM9081_FLL_ENA_MASK 0x0001 /* FLL_ENA */
335 #define WM9081_FLL_ENA_SHIFT 0 /* FLL_ENA */
336 #define WM9081_FLL_ENA_WIDTH 1 /* FLL_ENA */
339 * R17 (0x11) - FLL Control 2
341 #define WM9081_FLL_OUTDIV_MASK 0x0700 /* FLL_OUTDIV - [10:8] */
342 #define WM9081_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [10:8] */
343 #define WM9081_FLL_OUTDIV_WIDTH 3 /* FLL_OUTDIV - [10:8] */
344 #define WM9081_FLL_CTRL_RATE_MASK 0x0070 /* FLL_CTRL_RATE - [6:4] */
345 #define WM9081_FLL_CTRL_RATE_SHIFT 4 /* FLL_CTRL_RATE - [6:4] */
346 #define WM9081_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [6:4] */
347 #define WM9081_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */
348 #define WM9081_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */
349 #define WM9081_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */
352 * R18 (0x12) - FLL Control 3
354 #define WM9081_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */
355 #define WM9081_FLL_K_SHIFT 0 /* FLL_K - [15:0] */
356 #define WM9081_FLL_K_WIDTH 16 /* FLL_K - [15:0] */
359 * R19 (0x13) - FLL Control 4
361 #define WM9081_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */
362 #define WM9081_FLL_N_SHIFT 5 /* FLL_N - [14:5] */
363 #define WM9081_FLL_N_WIDTH 10 /* FLL_N - [14:5] */
364 #define WM9081_FLL_GAIN_MASK 0x000F /* FLL_GAIN - [3:0] */
365 #define WM9081_FLL_GAIN_SHIFT 0 /* FLL_GAIN - [3:0] */
366 #define WM9081_FLL_GAIN_WIDTH 4 /* FLL_GAIN - [3:0] */
369 * R20 (0x14) - FLL Control 5
371 #define WM9081_FLL_CLK_REF_DIV_MASK 0x0018 /* FLL_CLK_REF_DIV - [4:3] */
372 #define WM9081_FLL_CLK_REF_DIV_SHIFT 3 /* FLL_CLK_REF_DIV - [4:3] */
373 #define WM9081_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [4:3] */
374 #define WM9081_FLL_CLK_SRC_MASK 0x0003 /* FLL_CLK_SRC - [1:0] */
375 #define WM9081_FLL_CLK_SRC_SHIFT 0 /* FLL_CLK_SRC - [1:0] */
376 #define WM9081_FLL_CLK_SRC_WIDTH 2 /* FLL_CLK_SRC - [1:0] */
379 * R22 (0x16) - Audio Interface 1
381 #define WM9081_AIFDAC_CHAN 0x0040 /* AIFDAC_CHAN */
382 #define WM9081_AIFDAC_CHAN_MASK 0x0040 /* AIFDAC_CHAN */
383 #define WM9081_AIFDAC_CHAN_SHIFT 6 /* AIFDAC_CHAN */
384 #define WM9081_AIFDAC_CHAN_WIDTH 1 /* AIFDAC_CHAN */
385 #define WM9081_AIFDAC_TDM_SLOT_MASK 0x0030 /* AIFDAC_TDM_SLOT - [5:4] */
386 #define WM9081_AIFDAC_TDM_SLOT_SHIFT 4 /* AIFDAC_TDM_SLOT - [5:4] */
387 #define WM9081_AIFDAC_TDM_SLOT_WIDTH 2 /* AIFDAC_TDM_SLOT - [5:4] */
388 #define WM9081_AIFDAC_TDM_MODE_MASK 0x000C /* AIFDAC_TDM_MODE - [3:2] */
389 #define WM9081_AIFDAC_TDM_MODE_SHIFT 2 /* AIFDAC_TDM_MODE - [3:2] */
390 #define WM9081_AIFDAC_TDM_MODE_WIDTH 2 /* AIFDAC_TDM_MODE - [3:2] */
391 #define WM9081_DAC_COMP 0x0002 /* DAC_COMP */
392 #define WM9081_DAC_COMP_MASK 0x0002 /* DAC_COMP */
393 #define WM9081_DAC_COMP_SHIFT 1 /* DAC_COMP */
394 #define WM9081_DAC_COMP_WIDTH 1 /* DAC_COMP */
395 #define WM9081_DAC_COMPMODE 0x0001 /* DAC_COMPMODE */
396 #define WM9081_DAC_COMPMODE_MASK 0x0001 /* DAC_COMPMODE */
397 #define WM9081_DAC_COMPMODE_SHIFT 0 /* DAC_COMPMODE */
398 #define WM9081_DAC_COMPMODE_WIDTH 1 /* DAC_COMPMODE */
401 * R23 (0x17) - Audio Interface 2
403 #define WM9081_AIF_TRIS 0x0200 /* AIF_TRIS */
404 #define WM9081_AIF_TRIS_MASK 0x0200 /* AIF_TRIS */
405 #define WM9081_AIF_TRIS_SHIFT 9 /* AIF_TRIS */
406 #define WM9081_AIF_TRIS_WIDTH 1 /* AIF_TRIS */
407 #define WM9081_DAC_DAT_INV 0x0100 /* DAC_DAT_INV */
408 #define WM9081_DAC_DAT_INV_MASK 0x0100 /* DAC_DAT_INV */
409 #define WM9081_DAC_DAT_INV_SHIFT 8 /* DAC_DAT_INV */
410 #define WM9081_DAC_DAT_INV_WIDTH 1 /* DAC_DAT_INV */
411 #define WM9081_AIF_BCLK_INV 0x0080 /* AIF_BCLK_INV */
412 #define WM9081_AIF_BCLK_INV_MASK 0x0080 /* AIF_BCLK_INV */
413 #define WM9081_AIF_BCLK_INV_SHIFT 7 /* AIF_BCLK_INV */
414 #define WM9081_AIF_BCLK_INV_WIDTH 1 /* AIF_BCLK_INV */
415 #define WM9081_BCLK_DIR 0x0040 /* BCLK_DIR */
416 #define WM9081_BCLK_DIR_MASK 0x0040 /* BCLK_DIR */
417 #define WM9081_BCLK_DIR_SHIFT 6 /* BCLK_DIR */
418 #define WM9081_BCLK_DIR_WIDTH 1 /* BCLK_DIR */
419 #define WM9081_LRCLK_DIR 0x0020 /* LRCLK_DIR */
420 #define WM9081_LRCLK_DIR_MASK 0x0020 /* LRCLK_DIR */
421 #define WM9081_LRCLK_DIR_SHIFT 5 /* LRCLK_DIR */
422 #define WM9081_LRCLK_DIR_WIDTH 1 /* LRCLK_DIR */
423 #define WM9081_AIF_LRCLK_INV 0x0010 /* AIF_LRCLK_INV */
424 #define WM9081_AIF_LRCLK_INV_MASK 0x0010 /* AIF_LRCLK_INV */
425 #define WM9081_AIF_LRCLK_INV_SHIFT 4 /* AIF_LRCLK_INV */
426 #define WM9081_AIF_LRCLK_INV_WIDTH 1 /* AIF_LRCLK_INV */
427 #define WM9081_AIF_WL_MASK 0x000C /* AIF_WL - [3:2] */
428 #define WM9081_AIF_WL_SHIFT 2 /* AIF_WL - [3:2] */
429 #define WM9081_AIF_WL_WIDTH 2 /* AIF_WL - [3:2] */
430 #define WM9081_AIF_FMT_MASK 0x0003 /* AIF_FMT - [1:0] */
431 #define WM9081_AIF_FMT_SHIFT 0 /* AIF_FMT - [1:0] */
432 #define WM9081_AIF_FMT_WIDTH 2 /* AIF_FMT - [1:0] */
435 * R24 (0x18) - Audio Interface 3
437 #define WM9081_BCLK_DIV_MASK 0x001F /* BCLK_DIV - [4:0] */
438 #define WM9081_BCLK_DIV_SHIFT 0 /* BCLK_DIV - [4:0] */
439 #define WM9081_BCLK_DIV_WIDTH 5 /* BCLK_DIV - [4:0] */
442 * R25 (0x19) - Audio Interface 4
444 #define WM9081_LRCLK_RATE_MASK 0x07FF /* LRCLK_RATE - [10:0] */
445 #define WM9081_LRCLK_RATE_SHIFT 0 /* LRCLK_RATE - [10:0] */
446 #define WM9081_LRCLK_RATE_WIDTH 11 /* LRCLK_RATE - [10:0] */
449 * R26 (0x1A) - Interrupt Status
451 #define WM9081_WSEQ_BUSY_EINT 0x0004 /* WSEQ_BUSY_EINT */
452 #define WM9081_WSEQ_BUSY_EINT_MASK 0x0004 /* WSEQ_BUSY_EINT */
453 #define WM9081_WSEQ_BUSY_EINT_SHIFT 2 /* WSEQ_BUSY_EINT */
454 #define WM9081_WSEQ_BUSY_EINT_WIDTH 1 /* WSEQ_BUSY_EINT */
455 #define WM9081_TSHUT_EINT 0x0001 /* TSHUT_EINT */
456 #define WM9081_TSHUT_EINT_MASK 0x0001 /* TSHUT_EINT */
457 #define WM9081_TSHUT_EINT_SHIFT 0 /* TSHUT_EINT */
458 #define WM9081_TSHUT_EINT_WIDTH 1 /* TSHUT_EINT */
461 * R27 (0x1B) - Interrupt Status Mask
463 #define WM9081_IM_WSEQ_BUSY_EINT 0x0004 /* IM_WSEQ_BUSY_EINT */
464 #define WM9081_IM_WSEQ_BUSY_EINT_MASK 0x0004 /* IM_WSEQ_BUSY_EINT */
465 #define WM9081_IM_WSEQ_BUSY_EINT_SHIFT 2 /* IM_WSEQ_BUSY_EINT */
466 #define WM9081_IM_WSEQ_BUSY_EINT_WIDTH 1 /* IM_WSEQ_BUSY_EINT */
467 #define WM9081_IM_TSHUT_EINT 0x0001 /* IM_TSHUT_EINT */
468 #define WM9081_IM_TSHUT_EINT_MASK 0x0001 /* IM_TSHUT_EINT */
469 #define WM9081_IM_TSHUT_EINT_SHIFT 0 /* IM_TSHUT_EINT */
470 #define WM9081_IM_TSHUT_EINT_WIDTH 1 /* IM_TSHUT_EINT */
473 * R28 (0x1C) - Interrupt Polarity
475 #define WM9081_TSHUT_INV 0x0001 /* TSHUT_INV */
476 #define WM9081_TSHUT_INV_MASK 0x0001 /* TSHUT_INV */
477 #define WM9081_TSHUT_INV_SHIFT 0 /* TSHUT_INV */
478 #define WM9081_TSHUT_INV_WIDTH 1 /* TSHUT_INV */
481 * R29 (0x1D) - Interrupt Control
483 #define WM9081_IRQ_POL 0x8000 /* IRQ_POL */
484 #define WM9081_IRQ_POL_MASK 0x8000 /* IRQ_POL */
485 #define WM9081_IRQ_POL_SHIFT 15 /* IRQ_POL */
486 #define WM9081_IRQ_POL_WIDTH 1 /* IRQ_POL */
487 #define WM9081_IRQ_OP_CTRL 0x0001 /* IRQ_OP_CTRL */
488 #define WM9081_IRQ_OP_CTRL_MASK 0x0001 /* IRQ_OP_CTRL */
489 #define WM9081_IRQ_OP_CTRL_SHIFT 0 /* IRQ_OP_CTRL */
490 #define WM9081_IRQ_OP_CTRL_WIDTH 1 /* IRQ_OP_CTRL */
493 * R30 (0x1E) - DAC Digital 1
495 #define WM9081_DAC_VOL_MASK 0x00FF /* DAC_VOL - [7:0] */
496 #define WM9081_DAC_VOL_SHIFT 0 /* DAC_VOL - [7:0] */
497 #define WM9081_DAC_VOL_WIDTH 8 /* DAC_VOL - [7:0] */
500 * R31 (0x1F) - DAC Digital 2
502 #define WM9081_DAC_MUTERATE 0x0400 /* DAC_MUTERATE */
503 #define WM9081_DAC_MUTERATE_MASK 0x0400 /* DAC_MUTERATE */
504 #define WM9081_DAC_MUTERATE_SHIFT 10 /* DAC_MUTERATE */
505 #define WM9081_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */
506 #define WM9081_DAC_MUTEMODE 0x0200 /* DAC_MUTEMODE */
507 #define WM9081_DAC_MUTEMODE_MASK 0x0200 /* DAC_MUTEMODE */
508 #define WM9081_DAC_MUTEMODE_SHIFT 9 /* DAC_MUTEMODE */
509 #define WM9081_DAC_MUTEMODE_WIDTH 1 /* DAC_MUTEMODE */
510 #define WM9081_DAC_MUTE 0x0008 /* DAC_MUTE */
511 #define WM9081_DAC_MUTE_MASK 0x0008 /* DAC_MUTE */
512 #define WM9081_DAC_MUTE_SHIFT 3 /* DAC_MUTE */
513 #define WM9081_DAC_MUTE_WIDTH 1 /* DAC_MUTE */
514 #define WM9081_DEEMPH_MASK 0x0006 /* DEEMPH - [2:1] */
515 #define WM9081_DEEMPH_SHIFT 1 /* DEEMPH - [2:1] */
516 #define WM9081_DEEMPH_WIDTH 2 /* DEEMPH - [2:1] */
521 #define WM9081_DRC_ENA 0x8000 /* DRC_ENA */
522 #define WM9081_DRC_ENA_MASK 0x8000 /* DRC_ENA */
523 #define WM9081_DRC_ENA_SHIFT 15 /* DRC_ENA */
524 #define WM9081_DRC_ENA_WIDTH 1 /* DRC_ENA */
525 #define WM9081_DRC_STARTUP_GAIN_MASK 0x07C0 /* DRC_STARTUP_GAIN - [10:6] */
526 #define WM9081_DRC_STARTUP_GAIN_SHIFT 6 /* DRC_STARTUP_GAIN - [10:6] */
527 #define WM9081_DRC_STARTUP_GAIN_WIDTH 5 /* DRC_STARTUP_GAIN - [10:6] */
528 #define WM9081_DRC_FF_DLY 0x0020 /* DRC_FF_DLY */
529 #define WM9081_DRC_FF_DLY_MASK 0x0020 /* DRC_FF_DLY */
530 #define WM9081_DRC_FF_DLY_SHIFT 5 /* DRC_FF_DLY */
531 #define WM9081_DRC_FF_DLY_WIDTH 1 /* DRC_FF_DLY */
532 #define WM9081_DRC_QR 0x0004 /* DRC_QR */
533 #define WM9081_DRC_QR_MASK 0x0004 /* DRC_QR */
534 #define WM9081_DRC_QR_SHIFT 2 /* DRC_QR */
535 #define WM9081_DRC_QR_WIDTH 1 /* DRC_QR */
536 #define WM9081_DRC_ANTICLIP 0x0002 /* DRC_ANTICLIP */
537 #define WM9081_DRC_ANTICLIP_MASK 0x0002 /* DRC_ANTICLIP */
538 #define WM9081_DRC_ANTICLIP_SHIFT 1 /* DRC_ANTICLIP */
539 #define WM9081_DRC_ANTICLIP_WIDTH 1 /* DRC_ANTICLIP */
544 #define WM9081_DRC_ATK_MASK 0xF000 /* DRC_ATK - [15:12] */
545 #define WM9081_DRC_ATK_SHIFT 12 /* DRC_ATK - [15:12] */
546 #define WM9081_DRC_ATK_WIDTH 4 /* DRC_ATK - [15:12] */
547 #define WM9081_DRC_DCY_MASK 0x0F00 /* DRC_DCY - [11:8] */
548 #define WM9081_DRC_DCY_SHIFT 8 /* DRC_DCY - [11:8] */
549 #define WM9081_DRC_DCY_WIDTH 4 /* DRC_DCY - [11:8] */
550 #define WM9081_DRC_QR_THR_MASK 0x00C0 /* DRC_QR_THR - [7:6] */
551 #define WM9081_DRC_QR_THR_SHIFT 6 /* DRC_QR_THR - [7:6] */
552 #define WM9081_DRC_QR_THR_WIDTH 2 /* DRC_QR_THR - [7:6] */
553 #define WM9081_DRC_QR_DCY_MASK 0x0030 /* DRC_QR_DCY - [5:4] */
554 #define WM9081_DRC_QR_DCY_SHIFT 4 /* DRC_QR_DCY - [5:4] */
555 #define WM9081_DRC_QR_DCY_WIDTH 2 /* DRC_QR_DCY - [5:4] */
556 #define WM9081_DRC_MINGAIN_MASK 0x000C /* DRC_MINGAIN - [3:2] */
557 #define WM9081_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [3:2] */
558 #define WM9081_DRC_MINGAIN_WIDTH 2 /* DRC_MINGAIN - [3:2] */
559 #define WM9081_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */
560 #define WM9081_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */
561 #define WM9081_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */
566 #define WM9081_DRC_HI_COMP_MASK 0x0038 /* DRC_HI_COMP - [5:3] */
567 #define WM9081_DRC_HI_COMP_SHIFT 3 /* DRC_HI_COMP - [5:3] */
568 #define WM9081_DRC_HI_COMP_WIDTH 3 /* DRC_HI_COMP - [5:3] */
569 #define WM9081_DRC_LO_COMP_MASK 0x0007 /* DRC_LO_COMP - [2:0] */
570 #define WM9081_DRC_LO_COMP_SHIFT 0 /* DRC_LO_COMP - [2:0] */
571 #define WM9081_DRC_LO_COMP_WIDTH 3 /* DRC_LO_COMP - [2:0] */
576 #define WM9081_DRC_KNEE_IP_MASK 0x07E0 /* DRC_KNEE_IP - [10:5] */
577 #define WM9081_DRC_KNEE_IP_SHIFT 5 /* DRC_KNEE_IP - [10:5] */
578 #define WM9081_DRC_KNEE_IP_WIDTH 6 /* DRC_KNEE_IP - [10:5] */
579 #define WM9081_DRC_KNEE_OP_MASK 0x001F /* DRC_KNEE_OP - [4:0] */
580 #define WM9081_DRC_KNEE_OP_SHIFT 0 /* DRC_KNEE_OP - [4:0] */
581 #define WM9081_DRC_KNEE_OP_WIDTH 5 /* DRC_KNEE_OP - [4:0] */
584 * R38 (0x26) - Write Sequencer 1
586 #define WM9081_WSEQ_ENA 0x8000 /* WSEQ_ENA */
587 #define WM9081_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */
588 #define WM9081_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */
589 #define WM9081_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
590 #define WM9081_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */
591 #define WM9081_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */
592 #define WM9081_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */
593 #define WM9081_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
594 #define WM9081_WSEQ_START 0x0100 /* WSEQ_START */
595 #define WM9081_WSEQ_START_MASK 0x0100 /* WSEQ_START */
596 #define WM9081_WSEQ_START_SHIFT 8 /* WSEQ_START */
597 #define WM9081_WSEQ_START_WIDTH 1 /* WSEQ_START */
598 #define WM9081_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */
599 #define WM9081_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */
600 #define WM9081_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */
603 * R39 (0x27) - Write Sequencer 2
605 #define WM9081_WSEQ_CURRENT_INDEX_MASK 0x07F0 /* WSEQ_CURRENT_INDEX - [10:4] */
606 #define WM9081_WSEQ_CURRENT_INDEX_SHIFT 4 /* WSEQ_CURRENT_INDEX - [10:4] */
607 #define WM9081_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [10:4] */
608 #define WM9081_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */
609 #define WM9081_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */
610 #define WM9081_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */
611 #define WM9081_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
614 * R40 (0x28) - MW Slave 1
616 #define WM9081_SPI_CFG 0x0020 /* SPI_CFG */
617 #define WM9081_SPI_CFG_MASK 0x0020 /* SPI_CFG */
618 #define WM9081_SPI_CFG_SHIFT 5 /* SPI_CFG */
619 #define WM9081_SPI_CFG_WIDTH 1 /* SPI_CFG */
620 #define WM9081_SPI_4WIRE 0x0010 /* SPI_4WIRE */
621 #define WM9081_SPI_4WIRE_MASK 0x0010 /* SPI_4WIRE */
622 #define WM9081_SPI_4WIRE_SHIFT 4 /* SPI_4WIRE */
623 #define WM9081_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */
624 #define WM9081_ARA_ENA 0x0008 /* ARA_ENA */
625 #define WM9081_ARA_ENA_MASK 0x0008 /* ARA_ENA */
626 #define WM9081_ARA_ENA_SHIFT 3 /* ARA_ENA */
627 #define WM9081_ARA_ENA_WIDTH 1 /* ARA_ENA */
628 #define WM9081_AUTO_INC 0x0002 /* AUTO_INC */
629 #define WM9081_AUTO_INC_MASK 0x0002 /* AUTO_INC */
630 #define WM9081_AUTO_INC_SHIFT 1 /* AUTO_INC */
631 #define WM9081_AUTO_INC_WIDTH 1 /* AUTO_INC */
636 #define WM9081_EQ_B1_GAIN_MASK 0xF800 /* EQ_B1_GAIN - [15:11] */
637 #define WM9081_EQ_B1_GAIN_SHIFT 11 /* EQ_B1_GAIN - [15:11] */
638 #define WM9081_EQ_B1_GAIN_WIDTH 5 /* EQ_B1_GAIN - [15:11] */
639 #define WM9081_EQ_B2_GAIN_MASK 0x07C0 /* EQ_B2_GAIN - [10:6] */
640 #define WM9081_EQ_B2_GAIN_SHIFT 6 /* EQ_B2_GAIN - [10:6] */
641 #define WM9081_EQ_B2_GAIN_WIDTH 5 /* EQ_B2_GAIN - [10:6] */
642 #define WM9081_EQ_B4_GAIN_MASK 0x003E /* EQ_B4_GAIN - [5:1] */
643 #define WM9081_EQ_B4_GAIN_SHIFT 1 /* EQ_B4_GAIN - [5:1] */
644 #define WM9081_EQ_B4_GAIN_WIDTH 5 /* EQ_B4_GAIN - [5:1] */
645 #define WM9081_EQ_ENA 0x0001 /* EQ_ENA */
646 #define WM9081_EQ_ENA_MASK 0x0001 /* EQ_ENA */
647 #define WM9081_EQ_ENA_SHIFT 0 /* EQ_ENA */
648 #define WM9081_EQ_ENA_WIDTH 1 /* EQ_ENA */
653 #define WM9081_EQ_B3_GAIN_MASK 0xF800 /* EQ_B3_GAIN - [15:11] */
654 #define WM9081_EQ_B3_GAIN_SHIFT 11 /* EQ_B3_GAIN - [15:11] */
655 #define WM9081_EQ_B3_GAIN_WIDTH 5 /* EQ_B3_GAIN - [15:11] */
656 #define WM9081_EQ_B5_GAIN_MASK 0x07C0 /* EQ_B5_GAIN - [10:6] */
657 #define WM9081_EQ_B5_GAIN_SHIFT 6 /* EQ_B5_GAIN - [10:6] */
658 #define WM9081_EQ_B5_GAIN_WIDTH 5 /* EQ_B5_GAIN - [10:6] */
663 #define WM9081_EQ_B1_A_MASK 0xFFFF /* EQ_B1_A - [15:0] */
664 #define WM9081_EQ_B1_A_SHIFT 0 /* EQ_B1_A - [15:0] */
665 #define WM9081_EQ_B1_A_WIDTH 16 /* EQ_B1_A - [15:0] */
670 #define WM9081_EQ_B1_B_MASK 0xFFFF /* EQ_B1_B - [15:0] */
671 #define WM9081_EQ_B1_B_SHIFT 0 /* EQ_B1_B - [15:0] */
672 #define WM9081_EQ_B1_B_WIDTH 16 /* EQ_B1_B - [15:0] */
677 #define WM9081_EQ_B1_PG_MASK 0xFFFF /* EQ_B1_PG - [15:0] */
678 #define WM9081_EQ_B1_PG_SHIFT 0 /* EQ_B1_PG - [15:0] */
679 #define WM9081_EQ_B1_PG_WIDTH 16 /* EQ_B1_PG - [15:0] */
684 #define WM9081_EQ_B2_A_MASK 0xFFFF /* EQ_B2_A - [15:0] */
685 #define WM9081_EQ_B2_A_SHIFT 0 /* EQ_B2_A - [15:0] */
686 #define WM9081_EQ_B2_A_WIDTH 16 /* EQ_B2_A - [15:0] */
691 #define WM9081_EQ_B2_B_MASK 0xFFFF /* EQ_B2_B - [15:0] */
692 #define WM9081_EQ_B2_B_SHIFT 0 /* EQ_B2_B - [15:0] */
693 #define WM9081_EQ_B2_B_WIDTH 16 /* EQ_B2_B - [15:0] */
698 #define WM9081_EQ_B2_C_MASK 0xFFFF /* EQ_B2_C - [15:0] */
699 #define WM9081_EQ_B2_C_SHIFT 0 /* EQ_B2_C - [15:0] */
700 #define WM9081_EQ_B2_C_WIDTH 16 /* EQ_B2_C - [15:0] */
705 #define WM9081_EQ_B2_PG_MASK 0xFFFF /* EQ_B2_PG - [15:0] */
706 #define WM9081_EQ_B2_PG_SHIFT 0 /* EQ_B2_PG - [15:0] */
707 #define WM9081_EQ_B2_PG_WIDTH 16 /* EQ_B2_PG - [15:0] */
712 #define WM9081_EQ_B4_A_MASK 0xFFFF /* EQ_B4_A - [15:0] */
713 #define WM9081_EQ_B4_A_SHIFT 0 /* EQ_B4_A - [15:0] */
714 #define WM9081_EQ_B4_A_WIDTH 16 /* EQ_B4_A - [15:0] */
719 #define WM9081_EQ_B4_B_MASK 0xFFFF /* EQ_B4_B - [15:0] */
720 #define WM9081_EQ_B4_B_SHIFT 0 /* EQ_B4_B - [15:0] */
721 #define WM9081_EQ_B4_B_WIDTH 16 /* EQ_B4_B - [15:0] */
726 #define WM9081_EQ_B4_C_MASK 0xFFFF /* EQ_B4_C - [15:0] */
727 #define WM9081_EQ_B4_C_SHIFT 0 /* EQ_B4_C - [15:0] */
728 #define WM9081_EQ_B4_C_WIDTH 16 /* EQ_B4_C - [15:0] */
733 #define WM9081_EQ_B4_PG_MASK 0xFFFF /* EQ_B4_PG - [15:0] */
734 #define WM9081_EQ_B4_PG_SHIFT 0 /* EQ_B4_PG - [15:0] */
735 #define WM9081_EQ_B4_PG_WIDTH 16 /* EQ_B4_PG - [15:0] */
740 #define WM9081_EQ_B3_A_MASK 0xFFFF /* EQ_B3_A - [15:0] */
741 #define WM9081_EQ_B3_A_SHIFT 0 /* EQ_B3_A - [15:0] */
742 #define WM9081_EQ_B3_A_WIDTH 16 /* EQ_B3_A - [15:0] */
747 #define WM9081_EQ_B3_B_MASK 0xFFFF /* EQ_B3_B - [15:0] */
748 #define WM9081_EQ_B3_B_SHIFT 0 /* EQ_B3_B - [15:0] */
749 #define WM9081_EQ_B3_B_WIDTH 16 /* EQ_B3_B - [15:0] */
754 #define WM9081_EQ_B3_C_MASK 0xFFFF /* EQ_B3_C - [15:0] */
755 #define WM9081_EQ_B3_C_SHIFT 0 /* EQ_B3_C - [15:0] */
756 #define WM9081_EQ_B3_C_WIDTH 16 /* EQ_B3_C - [15:0] */
761 #define WM9081_EQ_B3_PG_MASK 0xFFFF /* EQ_B3_PG - [15:0] */
762 #define WM9081_EQ_B3_PG_SHIFT 0 /* EQ_B3_PG - [15:0] */
763 #define WM9081_EQ_B3_PG_WIDTH 16 /* EQ_B3_PG - [15:0] */
768 #define WM9081_EQ_B5_A_MASK 0xFFFF /* EQ_B5_A - [15:0] */
769 #define WM9081_EQ_B5_A_SHIFT 0 /* EQ_B5_A - [15:0] */
770 #define WM9081_EQ_B5_A_WIDTH 16 /* EQ_B5_A - [15:0] */
775 #define WM9081_EQ_B5_B_MASK 0xFFFF /* EQ_B5_B - [15:0] */
776 #define WM9081_EQ_B5_B_SHIFT 0 /* EQ_B5_B - [15:0] */
777 #define WM9081_EQ_B5_B_WIDTH 16 /* EQ_B5_B - [15:0] */
782 #define WM9081_EQ_B5_PG_MASK 0xFFFF /* EQ_B5_PG - [15:0] */
783 #define WM9081_EQ_B5_PG_SHIFT 0 /* EQ_B5_PG - [15:0] */
784 #define WM9081_EQ_B5_PG_WIDTH 16 /* EQ_B5_PG - [15:0] */
