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Full support for Ginger Console
[linux-ginger.git] / sound / soc / omap / omap-mcbsp.c
blob89173843b385212f47d854a272b6399d9473a839
1 /*
2 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
3 *
4 * Copyright (C) 2008 Nokia Corporation
5 *
6 * Contact: Jarkko Nikula <jhnikula@gmail.com>
7 * Peter Ujfalusi <peter.ujfalusi@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/device.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/initval.h>
32 #include <sound/soc.h>
33
34 #include <plat/control.h>
35 #include <plat/dma.h>
36 #include <plat/mcbsp.h>
37 #include "omap-mcbsp.h"
38 #include "omap-pcm.h"
39
40 #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
41
42 struct omap_mcbsp_data {
43 unsigned int bus_id;
44 struct omap_mcbsp_reg_cfg regs;
45 unsigned int fmt;
46 /*
47 * Flags indicating is the bus already activated and configured by
48 * another substream
49 */
50 int active;
51 int configured;
52 };
53
54 #define to_mcbsp(priv) container_of((priv), struct omap_mcbsp_data, bus_id)
55
56 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
57
58 /*
59 * Stream DMA parameters. DMA request line and port address are set runtime
60 * since they are different between OMAP1 and later OMAPs
61 */
62 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
63
64 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
65 static const int omap1_dma_reqs[][2] = {
66 { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
67 { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
68 { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
69 };
70 static const unsigned long omap1_mcbsp_port[][2] = {
71 { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
72 OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
73 { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
74 OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
75 { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
76 OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
77 };
78 #else
79 static const int omap1_dma_reqs[][2] = {};
80 static const unsigned long omap1_mcbsp_port[][2] = {};
81 #endif
82
83 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
84 static const int omap24xx_dma_reqs[][2] = {
85 { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
86 { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
87 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
88 { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
89 { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
90 { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
91 #endif
92 };
93 #else
94 static const int omap24xx_dma_reqs[][2] = {};
95 #endif
96
97 #if defined(CONFIG_ARCH_OMAP2420)
98 static const unsigned long omap2420_mcbsp_port[][2] = {
99 { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
100 OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
101 { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
102 OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
103 };
104 #else
105 static const unsigned long omap2420_mcbsp_port[][2] = {};
106 #endif
107
108 #if defined(CONFIG_ARCH_OMAP2430)
109 static const unsigned long omap2430_mcbsp_port[][2] = {
110 { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
111 OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
112 { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
113 OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
114 { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
115 OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
116 { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
117 OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
118 { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
119 OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
120 };
121 #else
122 static const unsigned long omap2430_mcbsp_port[][2] = {};
123 #endif
124
125 #if defined(CONFIG_ARCH_OMAP34XX)
126 static const unsigned long omap34xx_mcbsp_port[][2] = {
127 { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
128 OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
129 { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
130 OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
131 { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
132 OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
133 { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
134 OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
135 { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
136 OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
137 };
138 #else
139 static const unsigned long omap34xx_mcbsp_port[][2] = {};
140 #endif
141
142 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
143 {
144 struct snd_soc_pcm_runtime *rtd = substream->private_data;
145 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
146 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
147 int dma_op_mode = omap_mcbsp_get_dma_op_mode(mcbsp_data->bus_id);
148 int samples;
149
150 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
151 if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
152 samples = snd_pcm_lib_period_bytes(substream) >> 1;
153 else
154 samples = 1;
155
156 /* Configure McBSP internal buffer usage */
157 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
158 omap_mcbsp_set_tx_threshold(mcbsp_data->bus_id, samples - 1);
159 else
160 omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, samples - 1);
161 }
162
163 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
164 struct snd_soc_dai *dai)
165 {
166 struct snd_soc_pcm_runtime *rtd = substream->private_data;
167 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
168 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
169 int bus_id = mcbsp_data->bus_id;
170 int err = 0;
171
172 if (!cpu_dai->active)
173 err = omap_mcbsp_request(bus_id);
174
175 if (cpu_is_omap343x()) {
176 int dma_op_mode = omap_mcbsp_get_dma_op_mode(bus_id);
177 int max_period;
178
179 /*
180 * McBSP2 in OMAP3 has 1024 * 32-bit internal audio buffer.
181 * Set constraint for minimum buffer size to the same than FIFO
182 * size in order to avoid underruns in playback startup because
183 * HW is keeping the DMA request active until FIFO is filled.
184 */
185 if (bus_id == 1)
186 snd_pcm_hw_constraint_minmax(substream->runtime,
187 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
188 4096, UINT_MAX);
189
190 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
191 max_period = omap_mcbsp_get_max_tx_threshold(bus_id);
192 else
193 max_period = omap_mcbsp_get_max_rx_threshold(bus_id);
194
195 max_period++;
196 max_period <<= 1;
197
198 if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
199 snd_pcm_hw_constraint_minmax(substream->runtime,
200 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
201 32, max_period);
202 }
203
204 return err;
205 }
206
207 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
208 struct snd_soc_dai *dai)
209 {
210 struct snd_soc_pcm_runtime *rtd = substream->private_data;
211 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
212 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
213
214 if (!cpu_dai->active) {
215 omap_mcbsp_free(mcbsp_data->bus_id);
216 mcbsp_data->configured = 0;
217 }
218 }
219
220 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
221 struct snd_soc_dai *dai)
222 {
223 struct snd_soc_pcm_runtime *rtd = substream->private_data;
224 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
225 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
226 int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
227
228 switch (cmd) {
229 case SNDRV_PCM_TRIGGER_START:
230 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
231 mcbsp_data->active++;
232 omap_mcbsp_start(mcbsp_data->bus_id, play, !play);
233 break;
234 case SNDRV_PCM_TRIGGER_RESUME:
235 mcbsp_data->active++;
236 omap_mcbsp_enable_clks(mcbsp_data->bus_id);
237 omap_mcbsp_config(mcbsp_data->bus_id,
238 &mcbsp_data->regs);
239 omap_mcbsp_start(mcbsp_data->bus_id, play, !play);
240 break;
241
242 case SNDRV_PCM_TRIGGER_STOP:
243 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
244 omap_mcbsp_stop(mcbsp_data->bus_id, play, !play);
245 mcbsp_data->active--;
246 break;
247 case SNDRV_PCM_TRIGGER_SUSPEND:
248 omap_mcbsp_stop(mcbsp_data->bus_id, play, !play);
249 omap_mcbsp_disable_clks(mcbsp_data->bus_id);
250 mcbsp_data->active--;
251 break;
252 default:
253 err = -EINVAL;
254 }
255
256 return err;
257 }
258
259 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
260 struct snd_pcm_hw_params *params,
261 struct snd_soc_dai *dai)
262 {
263 struct snd_soc_pcm_runtime *rtd = substream->private_data;
264 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
265 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
266 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
267 int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
268 int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
269 unsigned long port;
270 unsigned int format;
271
272 if (cpu_class_is_omap1()) {
273 dma = omap1_dma_reqs[bus_id][substream->stream];
274 port = omap1_mcbsp_port[bus_id][substream->stream];
275 } else if (cpu_is_omap2420()) {
276 dma = omap24xx_dma_reqs[bus_id][substream->stream];
277 port = omap2420_mcbsp_port[bus_id][substream->stream];
278 } else if (cpu_is_omap2430()) {
279 dma = omap24xx_dma_reqs[bus_id][substream->stream];
280 port = omap2430_mcbsp_port[bus_id][substream->stream];
281 } else if (cpu_is_omap343x()) {
282 dma = omap24xx_dma_reqs[bus_id][substream->stream];
283 port = omap34xx_mcbsp_port[bus_id][substream->stream];
284 omap_mcbsp_dai_dma_params[id][substream->stream].set_threshold =
285 omap_mcbsp_set_threshold;
286 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
287 if (omap_mcbsp_get_dma_op_mode(bus_id) ==
288 MCBSP_DMA_MODE_THRESHOLD)
289 sync_mode = OMAP_DMA_SYNC_FRAME;
290 } else {
291 return -ENODEV;
292 }
293 omap_mcbsp_dai_dma_params[id][substream->stream].name =
294 substream->stream ? "Audio Capture" : "Audio Playback";
295 omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
296 omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
297 omap_mcbsp_dai_dma_params[id][substream->stream].sync_mode = sync_mode;
298 cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
299
300 if (mcbsp_data->configured) {
301 /* McBSP already configured by another stream */
302 return 0;
303 }
304
305 format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
306 wpf = channels = params_channels(params);
307 switch (channels) {
308 case 2:
309 if (format == SND_SOC_DAIFMT_I2S) {
310 /* Use dual-phase frames */
311 regs->rcr2 |= RPHASE;
312 regs->xcr2 |= XPHASE;
313 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
314 wpf--;
315 regs->rcr2 |= RFRLEN2(wpf - 1);
316 regs->xcr2 |= XFRLEN2(wpf - 1);
317 }
318 case 1:
319 case 4:
320 /* Set word per (McBSP) frame for phase1 */
321 regs->rcr1 |= RFRLEN1(wpf - 1);
322 regs->xcr1 |= XFRLEN1(wpf - 1);
323 break;
324 default:
325 /* Unsupported number of channels */
326 return -EINVAL;
327 }
328
329 switch (params_format(params)) {
330 case SNDRV_PCM_FORMAT_S16_LE:
331 /* Set word lengths */
332 wlen = 16;
333 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
334 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
335 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
336 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
337 break;
338 default:
339 /* Unsupported PCM format */
340 return -EINVAL;
341 }
342
343 /* Set FS period and length in terms of bit clock periods */
344 switch (format) {
345 case SND_SOC_DAIFMT_I2S:
346 regs->srgr2 |= FPER(wlen * channels - 1);
347 regs->srgr1 |= FWID(wlen - 1);
348 break;
349 case SND_SOC_DAIFMT_DSP_A:
350 case SND_SOC_DAIFMT_DSP_B:
351 regs->srgr2 |= FPER(wlen * channels - 1);
352 regs->srgr1 |= FWID(0);
353 break;
354 }
355
356 omap_mcbsp_config(bus_id, &mcbsp_data->regs);
357 mcbsp_data->configured = 1;
358
359 return 0;
360 }
361
362 /*
363 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
364 * cache is initialized here
365 */
366 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
367 unsigned int fmt)
368 {
369 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
370 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
371 unsigned int temp_fmt = fmt;
372
373 if (mcbsp_data->configured)
374 return 0;
375
376 mcbsp_data->fmt = fmt;
377 memset(regs, 0, sizeof(*regs));
378 /* Generic McBSP register settings */
379 regs->spcr2 |= XINTM(3) | FREE;
380 regs->spcr1 |= RINTM(3);
381 /* RFIG and XFIG are not defined in 34xx */
382 if (!cpu_is_omap34xx()) {
383 regs->rcr2 |= RFIG;
384 regs->xcr2 |= XFIG;
385 }
386 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
387 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
388 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
389 }
390
391 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
392 case SND_SOC_DAIFMT_I2S:
393 /* 1-bit data delay */
394 regs->rcr2 |= RDATDLY(1);
395 regs->xcr2 |= XDATDLY(1);
396 break;
397 case SND_SOC_DAIFMT_DSP_A:
398 /* 1-bit data delay */
399 regs->rcr2 |= RDATDLY(1);
400 regs->xcr2 |= XDATDLY(1);
401 /* Invert FS polarity configuration */
402 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
403 break;
404 case SND_SOC_DAIFMT_DSP_B:
405 /* 0-bit data delay */
406 regs->rcr2 |= RDATDLY(0);
407 regs->xcr2 |= XDATDLY(0);
408 /* Invert FS polarity configuration */
409 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
410 break;
411 default:
412 /* Unsupported data format */
413 return -EINVAL;
414 }
415
416 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
417 case SND_SOC_DAIFMT_CBS_CFS:
418 /* McBSP master. Set FS and bit clocks as outputs */
419 regs->pcr0 |= FSXM | FSRM |
420 CLKXM | CLKRM;
421 /* Sample rate generator drives the FS */
422 regs->srgr2 |= FSGM;
423 break;
424 case SND_SOC_DAIFMT_CBM_CFM:
425 /* McBSP slave */
426 break;
427 default:
428 /* Unsupported master/slave configuration */
429 return -EINVAL;
430 }
431
432 /* Set bit clock (CLKX/CLKR) and FS polarities */
433 switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
434 case SND_SOC_DAIFMT_NB_NF:
435 /*
436 * Normal BCLK + FS.
437 * FS active low. TX data driven on falling edge of bit clock
438 * and RX data sampled on rising edge of bit clock.
439 */
440 regs->pcr0 |= FSXP | FSRP |
441 CLKXP | CLKRP;
442 break;
443 case SND_SOC_DAIFMT_NB_IF:
444 regs->pcr0 |= CLKXP | CLKRP;
445 break;
446 case SND_SOC_DAIFMT_IB_NF:
447 regs->pcr0 |= FSXP | FSRP;
448 break;
449 case SND_SOC_DAIFMT_IB_IF:
450 break;
451 default:
452 return -EINVAL;
453 }
454
455 return 0;
456 }
457
458 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
459 int div_id, int div)
460 {
461 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
462 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
463
464 if (div_id != OMAP_MCBSP_CLKGDV)
465 return -ENODEV;
466
467 regs->srgr1 |= CLKGDV(div - 1);
468
469 return 0;
470 }
471
472 static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
473 int clk_id)
474 {
475 int sel_bit;
476 u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
477
478 if (cpu_class_is_omap1()) {
479 /* OMAP1's can use only external source clock */
480 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
481 return -EINVAL;
482 else
483 return 0;
484 }
485
486 if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
487 return -EINVAL;
488
489 if (cpu_is_omap343x())
490 reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
491
492 switch (mcbsp_data->bus_id) {
493 case 0:
494 reg = OMAP2_CONTROL_DEVCONF0;
495 sel_bit = 2;
496 break;
497 case 1:
498 reg = OMAP2_CONTROL_DEVCONF0;
499 sel_bit = 6;
500 break;
501 case 2:
502 reg = reg_devconf1;
503 sel_bit = 0;
504 break;
505 case 3:
506 reg = reg_devconf1;
507 sel_bit = 2;
508 break;
509 case 4:
510 reg = reg_devconf1;
511 sel_bit = 4;
512 break;
513 default:
514 return -EINVAL;
515 }
516
517 if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
518 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
519 else
520 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
521
522 return 0;
523 }
524
525 static int omap_mcbsp_dai_set_rcvr_src(struct omap_mcbsp_data *mcbsp_data,
526 int clk_id)
527 {
528 int sel_bit, set = 0;
529 u16 reg = OMAP2_CONTROL_DEVCONF0;
530
531 if (cpu_class_is_omap1())
532 return -EINVAL; /* TODO: Can this be implemented for OMAP1? */
533 if (mcbsp_data->bus_id != 0)
534 return -EINVAL;
535
536 switch (clk_id) {
537 case OMAP_MCBSP_CLKR_SRC_CLKX:
538 set = 1;
539 case OMAP_MCBSP_CLKR_SRC_CLKR:
540 sel_bit = 3;
541 break;
542 case OMAP_MCBSP_FSR_SRC_FSX:
543 set = 1;
544 case OMAP_MCBSP_FSR_SRC_FSR:
545 sel_bit = 4;
546 break;
547 default:
548 return -EINVAL;
549 }
550
551 if (set)
552 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
553 else
554 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
555
556 return 0;
557 }
558
559 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
560 int clk_id, unsigned int freq,
561 int dir)
562 {
563 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
564 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
565 int err = 0;
566
567 switch (clk_id) {
568 case OMAP_MCBSP_SYSCLK_CLK:
569 regs->srgr2 |= CLKSM;
570 break;
571 case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
572 case OMAP_MCBSP_SYSCLK_CLKS_EXT:
573 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
574 break;
575
576 case OMAP_MCBSP_SYSCLK_CLKX_EXT:
577 regs->srgr2 |= CLKSM;
578 case OMAP_MCBSP_SYSCLK_CLKR_EXT:
579 regs->pcr0 |= SCLKME;
580 break;
581
582 case OMAP_MCBSP_CLKR_SRC_CLKR:
583 case OMAP_MCBSP_CLKR_SRC_CLKX:
584 case OMAP_MCBSP_FSR_SRC_FSR:
585 case OMAP_MCBSP_FSR_SRC_FSX:
586 err = omap_mcbsp_dai_set_rcvr_src(mcbsp_data, clk_id);
587 break;
588 default:
589 err = -ENODEV;
590 }
591
592 return err;
593 }
594
595 static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
596 .startup = omap_mcbsp_dai_startup,
597 .shutdown = omap_mcbsp_dai_shutdown,
598 .trigger = omap_mcbsp_dai_trigger,
599 .hw_params = omap_mcbsp_dai_hw_params,
600 .set_fmt = omap_mcbsp_dai_set_dai_fmt,
601 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,
602 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
603 };
604
605 #define OMAP_MCBSP_DAI_BUILDER(link_id) \
606 { \
607 .name = "omap-mcbsp-dai-"#link_id, \
608 .id = (link_id), \
609 .playback = { \
610 .channels_min = 1, \
611 .channels_max = 4, \
612 .rates = OMAP_MCBSP_RATES, \
613 .formats = SNDRV_PCM_FMTBIT_S16_LE, \
614 }, \
615 .capture = { \
616 .channels_min = 1, \
617 .channels_max = 4, \
618 .rates = OMAP_MCBSP_RATES, \
619 .formats = SNDRV_PCM_FMTBIT_S16_LE, \
620 }, \
621 .ops = &omap_mcbsp_dai_ops, \
622 .private_data = &mcbsp_data[(link_id)].bus_id, \
623 }
624
625 struct snd_soc_dai omap_mcbsp_dai[] = {
626 OMAP_MCBSP_DAI_BUILDER(0),
627 OMAP_MCBSP_DAI_BUILDER(1),
628 #if NUM_LINKS >= 3
629 OMAP_MCBSP_DAI_BUILDER(2),
630 #endif
631 #if NUM_LINKS == 5
632 OMAP_MCBSP_DAI_BUILDER(3),
633 OMAP_MCBSP_DAI_BUILDER(4),
634 #endif
635 };
636
637 EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
638
639 static int __init snd_omap_mcbsp_init(void)
640 {
641 return snd_soc_register_dais(omap_mcbsp_dai,
642 ARRAY_SIZE(omap_mcbsp_dai));
643 }
644 module_init(snd_omap_mcbsp_init);
645
646 static void __exit snd_omap_mcbsp_exit(void)
647 {
648 snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
649 }
650 module_exit(snd_omap_mcbsp_exit);
651
652 MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
653 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
654 MODULE_LICENSE("GPL");
Linux for Ginger Game Console