2 Driver for STV0297 demodulator
4 Copyright (C) 2004 Andrew de Quincey <adq_dvb@lidskialf.net>
5 Copyright (C) 2003-2004 Dennis Noermann <dennis.noermann@noernet.de>
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <linux/init.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/delay.h>
27 #include <linux/jiffies.h>
28 #include <linux/slab.h>
30 #include "dvb_frontend.h"
33 struct stv0297_state
{
34 struct i2c_adapter
*i2c
;
35 const struct stv0297_config
*config
;
36 struct dvb_frontend frontend
;
38 unsigned long last_ber
;
39 unsigned long base_freq
;
43 #define dprintk(x...) printk(x)
48 #define STV0297_CLOCK_KHZ 28900
51 static int stv0297_writereg(struct stv0297_state
*state
, u8 reg
, u8 data
)
54 u8 buf
[] = { reg
, data
};
55 struct i2c_msg msg
= {.addr
= state
->config
->demod_address
,.flags
= 0,.buf
= buf
,.len
= 2 };
57 ret
= i2c_transfer(state
->i2c
, &msg
, 1);
60 dprintk("%s: writereg error (reg == 0x%02x, val == 0x%02x, "
61 "ret == %i)\n", __func__
, reg
, data
, ret
);
63 return (ret
!= 1) ? -1 : 0;
66 static int stv0297_readreg(struct stv0297_state
*state
, u8 reg
)
71 struct i2c_msg msg
[] = { {.addr
= state
->config
->demod_address
,.flags
= 0,.buf
= b0
,.len
= 1},
72 {.addr
= state
->config
->demod_address
,.flags
= I2C_M_RD
,.buf
= b1
,.len
= 1}
75 // this device needs a STOP between the register and data
76 if (state
->config
->stop_during_read
) {
77 if ((ret
= i2c_transfer(state
->i2c
, &msg
[0], 1)) != 1) {
78 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__
, reg
, ret
);
81 if ((ret
= i2c_transfer(state
->i2c
, &msg
[1], 1)) != 1) {
82 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__
, reg
, ret
);
86 if ((ret
= i2c_transfer(state
->i2c
, msg
, 2)) != 2) {
87 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__
, reg
, ret
);
95 static int stv0297_writereg_mask(struct stv0297_state
*state
, u8 reg
, u8 mask
, u8 data
)
99 val
= stv0297_readreg(state
, reg
);
101 val
|= (data
& mask
);
102 stv0297_writereg(state
, reg
, val
);
107 static int stv0297_readregs(struct stv0297_state
*state
, u8 reg1
, u8
* b
, u8 len
)
110 struct i2c_msg msg
[] = { {.addr
= state
->config
->demod_address
,.flags
= 0,.buf
=
112 {.addr
= state
->config
->demod_address
,.flags
= I2C_M_RD
,.buf
= b
,.len
= len
}
115 // this device needs a STOP between the register and data
116 if (state
->config
->stop_during_read
) {
117 if ((ret
= i2c_transfer(state
->i2c
, &msg
[0], 1)) != 1) {
118 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__
, reg1
, ret
);
121 if ((ret
= i2c_transfer(state
->i2c
, &msg
[1], 1)) != 1) {
122 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__
, reg1
, ret
);
126 if ((ret
= i2c_transfer(state
->i2c
, msg
, 2)) != 2) {
127 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__
, reg1
, ret
);
135 static u32
stv0297_get_symbolrate(struct stv0297_state
*state
)
139 tmp
= stv0297_readreg(state
, 0x55);
140 tmp
|= stv0297_readreg(state
, 0x56) << 8;
141 tmp
|= stv0297_readreg(state
, 0x57) << 16;
142 tmp
|= stv0297_readreg(state
, 0x58) << 24;
144 tmp
*= STV0297_CLOCK_KHZ
;
150 static void stv0297_set_symbolrate(struct stv0297_state
*state
, u32 srate
)
154 tmp
= 131072L * srate
; /* 131072 = 2^17 */
155 tmp
= tmp
/ (STV0297_CLOCK_KHZ
/ 4); /* 1/4 = 2^-2 */
156 tmp
= tmp
* 8192L; /* 8192 = 2^13 */
158 stv0297_writereg(state
, 0x55, (unsigned char) (tmp
& 0xFF));
159 stv0297_writereg(state
, 0x56, (unsigned char) (tmp
>> 8));
160 stv0297_writereg(state
, 0x57, (unsigned char) (tmp
>> 16));
161 stv0297_writereg(state
, 0x58, (unsigned char) (tmp
>> 24));
164 static void stv0297_set_sweeprate(struct stv0297_state
*state
, short fshift
, long symrate
)
168 tmp
= (long) fshift
*262144L; /* 262144 = 2*18 */
170 tmp
*= 1024; /* 1024 = 2*10 */
180 stv0297_writereg(state
, 0x60, tmp
& 0xFF);
181 stv0297_writereg_mask(state
, 0x69, 0xF0, (tmp
>> 4) & 0xf0);
184 static void stv0297_set_carrieroffset(struct stv0297_state
*state
, long offset
)
188 /* symrate is hardcoded to 10000 */
189 tmp
= offset
* 26844L; /* (2**28)/10000 */
194 stv0297_writereg(state
, 0x66, (unsigned char) (tmp
& 0xFF));
195 stv0297_writereg(state
, 0x67, (unsigned char) (tmp
>> 8));
196 stv0297_writereg(state
, 0x68, (unsigned char) (tmp
>> 16));
197 stv0297_writereg_mask(state
, 0x69, 0x0F, (tmp
>> 24) & 0x0f);
201 static long stv0297_get_carrieroffset(struct stv0297_state *state)
205 stv0297_writereg(state, 0x6B, 0x00);
207 tmp = stv0297_readreg(state, 0x66);
208 tmp |= (stv0297_readreg(state, 0x67) << 8);
209 tmp |= (stv0297_readreg(state, 0x68) << 16);
210 tmp |= (stv0297_readreg(state, 0x69) & 0x0F) << 24;
212 tmp *= stv0297_get_symbolrate(state);
219 static void stv0297_set_initialdemodfreq(struct stv0297_state
*state
, long freq
)
224 freq
-= STV0297_CLOCK_KHZ
;
226 tmp
= (STV0297_CLOCK_KHZ
* 1000) / (1 << 16);
227 tmp
= (freq
* 1000) / tmp
;
231 stv0297_writereg_mask(state
, 0x25, 0x80, 0x80);
232 stv0297_writereg(state
, 0x21, tmp
>> 8);
233 stv0297_writereg(state
, 0x20, tmp
);
236 static int stv0297_set_qam(struct stv0297_state
*state
, fe_modulation_t modulation
)
240 switch (modulation
) {
265 stv0297_writereg_mask(state
, 0x00, 0x70, val
<< 4);
270 static int stv0297_set_inversion(struct stv0297_state
*state
, fe_spectral_inversion_t inversion
)
287 stv0297_writereg_mask(state
, 0x83, 0x08, val
<< 3);
292 static int stv0297_i2c_gate_ctrl(struct dvb_frontend
*fe
, int enable
)
294 struct stv0297_state
*state
= fe
->demodulator_priv
;
297 stv0297_writereg(state
, 0x87, 0x78);
298 stv0297_writereg(state
, 0x86, 0xc8);
304 static int stv0297_init(struct dvb_frontend
*fe
)
306 struct stv0297_state
*state
= fe
->demodulator_priv
;
309 /* load init table */
310 for (i
=0; !(state
->config
->inittab
[i
] == 0xff && state
->config
->inittab
[i
+1] == 0xff); i
+=2)
311 stv0297_writereg(state
, state
->config
->inittab
[i
], state
->config
->inittab
[i
+1]);
319 static int stv0297_sleep(struct dvb_frontend
*fe
)
321 struct stv0297_state
*state
= fe
->demodulator_priv
;
323 stv0297_writereg_mask(state
, 0x80, 1, 1);
328 static int stv0297_read_status(struct dvb_frontend
*fe
, fe_status_t
* status
)
330 struct stv0297_state
*state
= fe
->demodulator_priv
;
332 u8 sync
= stv0297_readreg(state
, 0xDF);
337 FE_HAS_SYNC
| FE_HAS_SIGNAL
| FE_HAS_CARRIER
| FE_HAS_VITERBI
| FE_HAS_LOCK
;
341 static int stv0297_read_ber(struct dvb_frontend
*fe
, u32
* ber
)
343 struct stv0297_state
*state
= fe
->demodulator_priv
;
346 stv0297_readregs(state
, 0xA0, BER
, 3);
347 if (!(BER
[0] & 0x80)) {
348 state
->last_ber
= BER
[2] << 8 | BER
[1];
349 stv0297_writereg_mask(state
, 0xA0, 0x80, 0x80);
352 *ber
= state
->last_ber
;
358 static int stv0297_read_signal_strength(struct dvb_frontend
*fe
, u16
* strength
)
360 struct stv0297_state
*state
= fe
->demodulator_priv
;
364 stv0297_readregs(state
, 0x41, STRENGTH
, 3);
365 tmp
= (STRENGTH
[1] & 0x03) << 8 | STRENGTH
[0];
366 if (STRENGTH
[2] & 0x20) {
377 *strength
= (tmp
<< 7) | (tmp
>> 2);
381 static int stv0297_read_snr(struct dvb_frontend
*fe
, u16
* snr
)
383 struct stv0297_state
*state
= fe
->demodulator_priv
;
386 stv0297_readregs(state
, 0x07, SNR
, 2);
387 *snr
= SNR
[1] << 8 | SNR
[0];
392 static int stv0297_read_ucblocks(struct dvb_frontend
*fe
, u32
* ucblocks
)
394 struct stv0297_state
*state
= fe
->demodulator_priv
;
396 stv0297_writereg_mask(state
, 0xDF, 0x03, 0x03); /* freeze the counters */
398 *ucblocks
= (stv0297_readreg(state
, 0xD5) << 8)
399 | stv0297_readreg(state
, 0xD4);
401 stv0297_writereg_mask(state
, 0xDF, 0x03, 0x02); /* clear the counters */
402 stv0297_writereg_mask(state
, 0xDF, 0x03, 0x01); /* re-enable the counters */
407 static int stv0297_set_frontend(struct dvb_frontend
*fe
, struct dvb_frontend_parameters
*p
)
409 struct stv0297_state
*state
= fe
->demodulator_priv
;
416 unsigned long starttime
;
417 unsigned long timeout
;
418 fe_spectral_inversion_t inversion
;
420 switch (p
->u
.qam
.modulation
) {
438 // determine inversion dependant parameters
439 inversion
= p
->inversion
;
440 if (state
->config
->invert
)
441 inversion
= (inversion
== INVERSION_ON
) ? INVERSION_OFF
: INVERSION_ON
;
442 carrieroffset
= -330;
448 sweeprate
= -sweeprate
;
449 carrieroffset
= -carrieroffset
;
457 if (fe
->ops
.tuner_ops
.set_params
) {
458 fe
->ops
.tuner_ops
.set_params(fe
, p
);
459 if (fe
->ops
.i2c_gate_ctrl
) fe
->ops
.i2c_gate_ctrl(fe
, 0);
462 /* clear software interrupts */
463 stv0297_writereg(state
, 0x82, 0x0);
465 /* set initial demodulation frequency */
466 stv0297_set_initialdemodfreq(state
, 7250);
469 stv0297_writereg_mask(state
, 0x43, 0x10, 0x00);
470 stv0297_writereg(state
, 0x41, 0x00);
471 stv0297_writereg_mask(state
, 0x42, 0x03, 0x01);
472 stv0297_writereg_mask(state
, 0x36, 0x60, 0x00);
473 stv0297_writereg_mask(state
, 0x36, 0x18, 0x00);
474 stv0297_writereg_mask(state
, 0x71, 0x80, 0x80);
475 stv0297_writereg(state
, 0x72, 0x00);
476 stv0297_writereg(state
, 0x73, 0x00);
477 stv0297_writereg_mask(state
, 0x74, 0x0F, 0x00);
478 stv0297_writereg_mask(state
, 0x43, 0x08, 0x00);
479 stv0297_writereg_mask(state
, 0x71, 0x80, 0x00);
482 stv0297_writereg_mask(state
, 0x5a, 0x20, 0x20);
483 stv0297_writereg_mask(state
, 0x5b, 0x02, 0x02);
484 stv0297_writereg_mask(state
, 0x5b, 0x02, 0x00);
485 stv0297_writereg_mask(state
, 0x5b, 0x01, 0x00);
486 stv0297_writereg_mask(state
, 0x5a, 0x40, 0x40);
488 /* disable frequency sweep */
489 stv0297_writereg_mask(state
, 0x6a, 0x01, 0x00);
491 /* reset deinterleaver */
492 stv0297_writereg_mask(state
, 0x81, 0x01, 0x01);
493 stv0297_writereg_mask(state
, 0x81, 0x01, 0x00);
496 stv0297_writereg_mask(state
, 0x83, 0x20, 0x20);
497 stv0297_writereg_mask(state
, 0x83, 0x20, 0x00);
499 /* reset equaliser */
500 u_threshold
= stv0297_readreg(state
, 0x00) & 0xf;
501 initial_u
= stv0297_readreg(state
, 0x01) >> 4;
502 blind_u
= stv0297_readreg(state
, 0x01) & 0xf;
503 stv0297_writereg_mask(state
, 0x84, 0x01, 0x01);
504 stv0297_writereg_mask(state
, 0x84, 0x01, 0x00);
505 stv0297_writereg_mask(state
, 0x00, 0x0f, u_threshold
);
506 stv0297_writereg_mask(state
, 0x01, 0xf0, initial_u
<< 4);
507 stv0297_writereg_mask(state
, 0x01, 0x0f, blind_u
);
509 /* data comes from internal A/D */
510 stv0297_writereg_mask(state
, 0x87, 0x80, 0x00);
512 /* clear phase registers */
513 stv0297_writereg(state
, 0x63, 0x00);
514 stv0297_writereg(state
, 0x64, 0x00);
515 stv0297_writereg(state
, 0x65, 0x00);
516 stv0297_writereg(state
, 0x66, 0x00);
517 stv0297_writereg(state
, 0x67, 0x00);
518 stv0297_writereg(state
, 0x68, 0x00);
519 stv0297_writereg_mask(state
, 0x69, 0x0f, 0x00);
522 stv0297_set_qam(state
, p
->u
.qam
.modulation
);
523 stv0297_set_symbolrate(state
, p
->u
.qam
.symbol_rate
/ 1000);
524 stv0297_set_sweeprate(state
, sweeprate
, p
->u
.qam
.symbol_rate
/ 1000);
525 stv0297_set_carrieroffset(state
, carrieroffset
);
526 stv0297_set_inversion(state
, inversion
);
529 /* Disable corner detection for higher QAMs */
530 if (p
->u
.qam
.modulation
== QAM_128
||
531 p
->u
.qam
.modulation
== QAM_256
)
532 stv0297_writereg_mask(state
, 0x88, 0x08, 0x00);
534 stv0297_writereg_mask(state
, 0x88, 0x08, 0x08);
536 stv0297_writereg_mask(state
, 0x5a, 0x20, 0x00);
537 stv0297_writereg_mask(state
, 0x6a, 0x01, 0x01);
538 stv0297_writereg_mask(state
, 0x43, 0x40, 0x40);
539 stv0297_writereg_mask(state
, 0x5b, 0x30, 0x00);
540 stv0297_writereg_mask(state
, 0x03, 0x0c, 0x0c);
541 stv0297_writereg_mask(state
, 0x03, 0x03, 0x03);
542 stv0297_writereg_mask(state
, 0x43, 0x10, 0x10);
544 /* wait for WGAGC lock */
546 timeout
= jiffies
+ msecs_to_jiffies(2000);
547 while (time_before(jiffies
, timeout
)) {
549 if (stv0297_readreg(state
, 0x43) & 0x08)
552 if (time_after(jiffies
, timeout
)) {
557 /* wait for equaliser partial convergence */
558 timeout
= jiffies
+ msecs_to_jiffies(500);
559 while (time_before(jiffies
, timeout
)) {
562 if (stv0297_readreg(state
, 0x82) & 0x04) {
566 if (time_after(jiffies
, timeout
)) {
570 /* wait for equaliser full convergence */
571 timeout
= jiffies
+ msecs_to_jiffies(delay
);
572 while (time_before(jiffies
, timeout
)) {
575 if (stv0297_readreg(state
, 0x82) & 0x08) {
579 if (time_after(jiffies
, timeout
)) {
584 stv0297_writereg_mask(state
, 0x6a, 1, 0);
585 stv0297_writereg_mask(state
, 0x88, 8, 0);
587 /* wait for main lock */
588 timeout
= jiffies
+ msecs_to_jiffies(20);
589 while (time_before(jiffies
, timeout
)) {
592 if (stv0297_readreg(state
, 0xDF) & 0x80) {
596 if (time_after(jiffies
, timeout
)) {
601 /* is it still locked after that delay? */
602 if (!(stv0297_readreg(state
, 0xDF) & 0x80)) {
607 stv0297_writereg_mask(state
, 0x5a, 0x40, 0x00);
608 state
->base_freq
= p
->frequency
;
612 stv0297_writereg_mask(state
, 0x6a, 0x01, 0x00);
616 static int stv0297_get_frontend(struct dvb_frontend
*fe
, struct dvb_frontend_parameters
*p
)
618 struct stv0297_state
*state
= fe
->demodulator_priv
;
621 reg_00
= stv0297_readreg(state
, 0x00);
622 reg_83
= stv0297_readreg(state
, 0x83);
624 p
->frequency
= state
->base_freq
;
625 p
->inversion
= (reg_83
& 0x08) ? INVERSION_ON
: INVERSION_OFF
;
626 if (state
->config
->invert
)
627 p
->inversion
= (p
->inversion
== INVERSION_ON
) ? INVERSION_OFF
: INVERSION_ON
;
628 p
->u
.qam
.symbol_rate
= stv0297_get_symbolrate(state
) * 1000;
629 p
->u
.qam
.fec_inner
= FEC_NONE
;
631 switch ((reg_00
>> 4) & 0x7) {
633 p
->u
.qam
.modulation
= QAM_16
;
636 p
->u
.qam
.modulation
= QAM_32
;
639 p
->u
.qam
.modulation
= QAM_128
;
642 p
->u
.qam
.modulation
= QAM_256
;
645 p
->u
.qam
.modulation
= QAM_64
;
652 static void stv0297_release(struct dvb_frontend
*fe
)
654 struct stv0297_state
*state
= fe
->demodulator_priv
;
658 static struct dvb_frontend_ops stv0297_ops
;
660 struct dvb_frontend
*stv0297_attach(const struct stv0297_config
*config
,
661 struct i2c_adapter
*i2c
)
663 struct stv0297_state
*state
= NULL
;
665 /* allocate memory for the internal state */
666 state
= kmalloc(sizeof(struct stv0297_state
), GFP_KERNEL
);
670 /* setup the state */
671 state
->config
= config
;
674 state
->base_freq
= 0;
676 /* check if the demod is there */
677 if ((stv0297_readreg(state
, 0x80) & 0x70) != 0x20)
680 /* create dvb_frontend */
681 memcpy(&state
->frontend
.ops
, &stv0297_ops
, sizeof(struct dvb_frontend_ops
));
682 state
->frontend
.demodulator_priv
= state
;
683 return &state
->frontend
;
690 static struct dvb_frontend_ops stv0297_ops
= {
693 .name
= "ST STV0297 DVB-C",
695 .frequency_min
= 47000000,
696 .frequency_max
= 862000000,
697 .frequency_stepsize
= 62500,
698 .symbol_rate_min
= 870000,
699 .symbol_rate_max
= 11700000,
700 .caps
= FE_CAN_QAM_16
| FE_CAN_QAM_32
| FE_CAN_QAM_64
|
701 FE_CAN_QAM_128
| FE_CAN_QAM_256
| FE_CAN_FEC_AUTO
},
703 .release
= stv0297_release
,
705 .init
= stv0297_init
,
706 .sleep
= stv0297_sleep
,
707 .i2c_gate_ctrl
= stv0297_i2c_gate_ctrl
,
709 .set_frontend
= stv0297_set_frontend
,
710 .get_frontend
= stv0297_get_frontend
,
712 .read_status
= stv0297_read_status
,
713 .read_ber
= stv0297_read_ber
,
714 .read_signal_strength
= stv0297_read_signal_strength
,
715 .read_snr
= stv0297_read_snr
,
716 .read_ucblocks
= stv0297_read_ucblocks
,
719 MODULE_DESCRIPTION("ST STV0297 DVB-C Demodulator driver");
720 MODULE_AUTHOR("Dennis Noermann and Andrew de Quincey");
721 MODULE_LICENSE("GPL");
723 EXPORT_SYMBOL(stv0297_attach
);