drivers/media/video/cx18/cx18-av-core.h

   1 /*
   2  *  cx18 ADEC header
   3  *
   4  *  Derived from cx25840-core.h
   5  *
   6  *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
   7  *
   8  *  This program is free software; you can redistribute it and/or
   9  *  modify it under the terms of the GNU General Public License
  10  *  as published by the Free Software Foundation; either version 2
  11  *  of the License, or (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful,
  14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *  GNU General Public License for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License
  19  *  along with this program; if not, write to the Free Software
  20  *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  21  *  02110-1301, USA.
  22  */
  23
  24 #ifndef _CX18_AV_CORE_H_
  25 #define _CX18_AV_CORE_H_
  26
  27 struct cx18;
  28
  29 enum cx18_av_video_input {
  30         /* Composite video inputs In1-In8 */
  31         CX18_AV_COMPOSITE1 = 1,
  32         CX18_AV_COMPOSITE2,
  33         CX18_AV_COMPOSITE3,
  34         CX18_AV_COMPOSITE4,
  35         CX18_AV_COMPOSITE5,
  36         CX18_AV_COMPOSITE6,
  37         CX18_AV_COMPOSITE7,
  38         CX18_AV_COMPOSITE8,
  39
  40         /* S-Video inputs consist of one luma input (In1-In4) ORed with one
  41            chroma input (In5-In8) */
  42         CX18_AV_SVIDEO_LUMA1 = 0x10,
  43         CX18_AV_SVIDEO_LUMA2 = 0x20,
  44         CX18_AV_SVIDEO_LUMA3 = 0x30,
  45         CX18_AV_SVIDEO_LUMA4 = 0x40,
  46         CX18_AV_SVIDEO_CHROMA4 = 0x400,
  47         CX18_AV_SVIDEO_CHROMA5 = 0x500,
  48         CX18_AV_SVIDEO_CHROMA6 = 0x600,
  49         CX18_AV_SVIDEO_CHROMA7 = 0x700,
  50         CX18_AV_SVIDEO_CHROMA8 = 0x800,
  51
  52         /* S-Video aliases for common luma/chroma combinations */
  53         CX18_AV_SVIDEO1 = 0x510,
  54         CX18_AV_SVIDEO2 = 0x620,
  55         CX18_AV_SVIDEO3 = 0x730,
  56         CX18_AV_SVIDEO4 = 0x840,
  57 };
  58
  59 enum cx18_av_audio_input {
  60         /* Audio inputs: serial or In4-In8 */
  61         CX18_AV_AUDIO_SERIAL,
  62         CX18_AV_AUDIO4 = 4,
  63         CX18_AV_AUDIO5,
  64         CX18_AV_AUDIO6,
  65         CX18_AV_AUDIO7,
  66         CX18_AV_AUDIO8,
  67 };
  68
  69 struct cx18_av_state {
  70         int radio;
  71         v4l2_std_id std;
  72         enum cx18_av_video_input vid_input;
  73         enum cx18_av_audio_input aud_input;
  74         u32 audclk_freq;
  75         int audmode;
  76         int vbi_line_offset;
  77         u32 id;
  78         u32 rev;
  79         int is_initialized;
  80 };
  81
  82
  83 /* Registers */
  84 #define CXADEC_CHIP_TYPE_TIGER     0x837
  85 #define CXADEC_CHIP_TYPE_MAKO      0x843
  86
  87 #define CXADEC_HOST_REG1           0x000
  88 #define CXADEC_HOST_REG2           0x001
  89
  90 #define CXADEC_CHIP_CTRL           0x100
  91 #define CXADEC_AFE_CTRL            0x104
  92 #define CXADEC_PLL_CTRL1           0x108
  93 #define CXADEC_VID_PLL_FRAC        0x10C
  94 #define CXADEC_AUX_PLL_FRAC        0x110
  95 #define CXADEC_PIN_CTRL1           0x114
  96 #define CXADEC_PIN_CTRL2           0x118
  97 #define CXADEC_PIN_CFG1            0x11C
  98 #define CXADEC_PIN_CFG2            0x120
  99
 100 #define CXADEC_PIN_CFG3            0x124
 101 #define CXADEC_I2S_MCLK            0x127
 102
 103 #define CXADEC_AUD_LOCK1           0x128
 104 #define CXADEC_AUD_LOCK2           0x12C
 105 #define CXADEC_POWER_CTRL          0x130
 106 #define CXADEC_AFE_DIAG_CTRL1      0x134
 107 #define CXADEC_AFE_DIAG_CTRL2      0x138
 108 #define CXADEC_AFE_DIAG_CTRL3      0x13C
 109 #define CXADEC_PLL_DIAG_CTRL       0x140
 110 #define CXADEC_TEST_CTRL1          0x144
 111 #define CXADEC_TEST_CTRL2          0x148
 112 #define CXADEC_BIST_STAT           0x14C
 113 #define CXADEC_DLL1_DIAG_CTRL      0x158
 114 #define CXADEC_DLL2_DIAG_CTRL      0x15C
 115
 116 /* IR registers */
 117 #define CXADEC_IR_CTRL_REG         0x200
 118 #define CXADEC_IR_TXCLK_REG        0x204
 119 #define CXADEC_IR_RXCLK_REG        0x208
 120 #define CXADEC_IR_CDUTY_REG        0x20C
 121 #define CXADEC_IR_STAT_REG         0x210
 122 #define CXADEC_IR_IRQEN_REG        0x214
 123 #define CXADEC_IR_FILTER_REG       0x218
 124 #define CXADEC_IR_FIFO_REG         0x21C
 125
 126 /* Video Registers */
 127 #define CXADEC_MODE_CTRL           0x400
 128 #define CXADEC_OUT_CTRL1           0x404
 129 #define CXADEC_OUT_CTRL2           0x408
 130 #define CXADEC_GEN_STAT            0x40C
 131 #define CXADEC_INT_STAT_MASK       0x410
 132 #define CXADEC_LUMA_CTRL           0x414
 133
 134 #define CXADEC_BRIGHTNESS_CTRL_BYTE 0x414
 135 #define CXADEC_CONTRAST_CTRL_BYTE  0x415
 136 #define CXADEC_LUMA_CTRL_BYTE_3    0x416
 137
 138 #define CXADEC_HSCALE_CTRL         0x418
 139 #define CXADEC_VSCALE_CTRL         0x41C
 140
 141 #define CXADEC_CHROMA_CTRL         0x420
 142
 143 #define CXADEC_USAT_CTRL_BYTE      0x420
 144 #define CXADEC_VSAT_CTRL_BYTE      0x421
 145 #define CXADEC_HUE_CTRL_BYTE       0x422
 146
 147 #define CXADEC_VBI_LINE_CTRL1      0x424
 148 #define CXADEC_VBI_LINE_CTRL2      0x428
 149 #define CXADEC_VBI_LINE_CTRL3      0x42C
 150 #define CXADEC_VBI_LINE_CTRL4      0x430
 151 #define CXADEC_VBI_LINE_CTRL5      0x434
 152 #define CXADEC_VBI_FC_CFG          0x438
 153 #define CXADEC_VBI_MISC_CFG1       0x43C
 154 #define CXADEC_VBI_MISC_CFG2       0x440
 155 #define CXADEC_VBI_PAY1            0x444
 156 #define CXADEC_VBI_PAY2            0x448
 157 #define CXADEC_VBI_CUST1_CFG1      0x44C
 158 #define CXADEC_VBI_CUST1_CFG2      0x450
 159 #define CXADEC_VBI_CUST1_CFG3      0x454
 160 #define CXADEC_VBI_CUST2_CFG1      0x458
 161 #define CXADEC_VBI_CUST2_CFG2      0x45C
 162 #define CXADEC_VBI_CUST2_CFG3      0x460
 163 #define CXADEC_VBI_CUST3_CFG1      0x464
 164 #define CXADEC_VBI_CUST3_CFG2      0x468
 165 #define CXADEC_VBI_CUST3_CFG3      0x46C
 166 #define CXADEC_HORIZ_TIM_CTRL      0x470
 167 #define CXADEC_VERT_TIM_CTRL       0x474
 168 #define CXADEC_SRC_COMB_CFG        0x478
 169 #define CXADEC_CHROMA_VBIOFF_CFG   0x47C
 170 #define CXADEC_FIELD_COUNT         0x480
 171 #define CXADEC_MISC_TIM_CTRL       0x484
 172 #define CXADEC_DFE_CTRL1           0x488
 173 #define CXADEC_DFE_CTRL2           0x48C
 174 #define CXADEC_DFE_CTRL3           0x490
 175 #define CXADEC_PLL_CTRL2           0x494
 176 #define CXADEC_HTL_CTRL            0x498
 177 #define CXADEC_COMB_CTRL           0x49C
 178 #define CXADEC_CRUSH_CTRL          0x4A0
 179 #define CXADEC_SOFT_RST_CTRL       0x4A4
 180 #define CXADEC_MV_DT_CTRL2         0x4A8
 181 #define CXADEC_MV_DT_CTRL3         0x4AC
 182 #define CXADEC_MISC_DIAG_CTRL      0x4B8
 183
 184 #define CXADEC_DL_CTL              0x800
 185 #define CXADEC_DL_CTL_ADDRESS_LOW  0x800   /* Byte 1 in DL_CTL */
 186 #define CXADEC_DL_CTL_ADDRESS_HIGH 0x801   /* Byte 2 in DL_CTL */
 187 #define CXADEC_DL_CTL_DATA         0x802   /* Byte 3 in DL_CTL */
 188 #define CXADEC_DL_CTL_CONTROL      0x803   /* Byte 4 in DL_CTL */
 189
 190 #define CXADEC_STD_DET_STATUS      0x804
 191
 192 #define CXADEC_STD_DET_CTL         0x808
 193 #define CXADEC_STD_DET_CTL_AUD_CTL   0x808 /* Byte 1 in STD_DET_CTL */
 194 #define CXADEC_STD_DET_CTL_PREF_MODE 0x809 /* Byte 2 in STD_DET_CTL */
 195
 196 #define CXADEC_DW8051_INT          0x80C
 197 #define CXADEC_GENERAL_CTL         0x810
 198 #define CXADEC_AAGC_CTL            0x814
 199 #define CXADEC_IF_SRC_CTL          0x818
 200 #define CXADEC_ANLOG_DEMOD_CTL     0x81C
 201 #define CXADEC_ROT_FREQ_CTL        0x820
 202 #define CXADEC_FM1_CTL             0x824
 203 #define CXADEC_PDF_CTL             0x828
 204 #define CXADEC_DFT1_CTL1           0x82C
 205 #define CXADEC_DFT1_CTL2           0x830
 206 #define CXADEC_DFT_STATUS          0x834
 207 #define CXADEC_DFT2_CTL1           0x838
 208 #define CXADEC_DFT2_CTL2           0x83C
 209 #define CXADEC_DFT2_STATUS         0x840
 210 #define CXADEC_DFT3_CTL1           0x844
 211 #define CXADEC_DFT3_CTL2           0x848
 212 #define CXADEC_DFT3_STATUS         0x84C
 213 #define CXADEC_DFT4_CTL1           0x850
 214 #define CXADEC_DFT4_CTL2           0x854
 215 #define CXADEC_DFT4_STATUS         0x858
 216 #define CXADEC_AM_MTS_DET          0x85C
 217 #define CXADEC_ANALOG_MUX_CTL      0x860
 218 #define CXADEC_DIG_PLL_CTL1        0x864
 219 #define CXADEC_DIG_PLL_CTL2        0x868
 220 #define CXADEC_DIG_PLL_CTL3        0x86C
 221 #define CXADEC_DIG_PLL_CTL4        0x870
 222 #define CXADEC_DIG_PLL_CTL5        0x874
 223 #define CXADEC_DEEMPH_GAIN_CTL     0x878
 224 #define CXADEC_DEEMPH_COEF1        0x87C
 225 #define CXADEC_DEEMPH_COEF2        0x880
 226 #define CXADEC_DBX1_CTL1           0x884
 227 #define CXADEC_DBX1_CTL2           0x888
 228 #define CXADEC_DBX1_STATUS         0x88C
 229 #define CXADEC_DBX2_CTL1           0x890
 230 #define CXADEC_DBX2_CTL2           0x894
 231 #define CXADEC_DBX2_STATUS         0x898
 232 #define CXADEC_AM_FM_DIFF          0x89C
 233
 234 /* NICAM registers go here */
 235 #define CXADEC_NICAM_STATUS        0x8C8
 236 #define CXADEC_DEMATRIX_CTL        0x8CC
 237
 238 #define CXADEC_PATH1_CTL1          0x8D0
 239 #define CXADEC_PATH1_VOL_CTL       0x8D4
 240 #define CXADEC_PATH1_EQ_CTL        0x8D8
 241 #define CXADEC_PATH1_SC_CTL        0x8DC
 242
 243 #define CXADEC_PATH2_CTL1          0x8E0
 244 #define CXADEC_PATH2_VOL_CTL       0x8E4
 245 #define CXADEC_PATH2_EQ_CTL        0x8E8
 246 #define CXADEC_PATH2_SC_CTL        0x8EC
 247
 248 #define CXADEC_SRC_CTL             0x8F0
 249 #define CXADEC_SRC_LF_COEF         0x8F4
 250 #define CXADEC_SRC1_CTL            0x8F8
 251 #define CXADEC_SRC2_CTL            0x8FC
 252 #define CXADEC_SRC3_CTL            0x900
 253 #define CXADEC_SRC4_CTL            0x904
 254 #define CXADEC_SRC5_CTL            0x908
 255 #define CXADEC_SRC6_CTL            0x90C
 256
 257 #define CXADEC_BASEBAND_OUT_SEL    0x910
 258 #define CXADEC_I2S_IN_CTL          0x914
 259 #define CXADEC_I2S_OUT_CTL         0x918
 260 #define CXADEC_AC97_CTL            0x91C
 261 #define CXADEC_QAM_PDF             0x920
 262 #define CXADEC_QAM_CONST_DEC       0x924
 263 #define CXADEC_QAM_ROTATOR_FREQ    0x948
 264
 265 /* Bit defintions / settings used in Mako Audio */
 266 #define CXADEC_PREF_MODE_MONO_LANGA        0
 267 #define CXADEC_PREF_MODE_MONO_LANGB        1
 268 #define CXADEC_PREF_MODE_MONO_LANGC        2
 269 #define CXADEC_PREF_MODE_FALLBACK          3
 270 #define CXADEC_PREF_MODE_STEREO            4
 271 #define CXADEC_PREF_MODE_DUAL_LANG_AC      5
 272 #define CXADEC_PREF_MODE_DUAL_LANG_BC      6
 273 #define CXADEC_PREF_MODE_DUAL_LANG_AB      7
 274
 275
 276 #define CXADEC_DETECT_STEREO               1
 277 #define CXADEC_DETECT_DUAL                 2
 278 #define CXADEC_DETECT_TRI                  4
 279 #define CXADEC_DETECT_SAP                  0x10
 280 #define CXADEC_DETECT_NO_SIGNAL            0xFF
 281
 282 #define CXADEC_SELECT_AUDIO_STANDARD_BG    0xF0  /* NICAM BG and A2 BG */
 283 #define CXADEC_SELECT_AUDIO_STANDARD_DK1   0xF1  /* NICAM DK and A2 DK */
 284 #define CXADEC_SELECT_AUDIO_STANDARD_DK2   0xF2
 285 #define CXADEC_SELECT_AUDIO_STANDARD_DK3   0xF3
 286 #define CXADEC_SELECT_AUDIO_STANDARD_I     0xF4  /* NICAM I and A1 */
 287 #define CXADEC_SELECT_AUDIO_STANDARD_L     0xF5  /* NICAM L and System L AM */
 288 #define CXADEC_SELECT_AUDIO_STANDARD_BTSC  0xF6
 289 #define CXADEC_SELECT_AUDIO_STANDARD_EIAJ  0xF7
 290 #define CXADEC_SELECT_AUDIO_STANDARD_A2_M  0xF8  /* A2 M */
 291 #define CXADEC_SELECT_AUDIO_STANDARD_FM    0xF9  /* FM radio */
 292 #define CXADEC_SELECT_AUDIO_STANDARD_AUTO  0xFF  /* Auto detect */
 293
 294 /* ----------------------------------------------------------------------- */
 295 /* cx18_av-core.c                                                          */
 296 int cx18_av_write(struct cx18 *cx, u16 addr, u8 value);
 297 int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value);
 298 u8 cx18_av_read(struct cx18 *cx, u16 addr);
 299 u32 cx18_av_read4(struct cx18 *cx, u16 addr);
 300 int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned mask, u8 value);
 301 int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 mask, u32 value);
 302 int cx18_av_cmd(struct cx18 *cx, unsigned int cmd, void *arg);
 303
 304 /* ----------------------------------------------------------------------- */
 305 /* cx18_av-firmware.c                                                      */
 306 int cx18_av_loadfw(struct cx18 *cx);
 307
 308 /* ----------------------------------------------------------------------- */
 309 /* cx18_av-audio.c                                                         */
 310 int cx18_av_audio(struct cx18 *cx, unsigned int cmd, void *arg);
 311 void cx18_av_audio_set_path(struct cx18 *cx);
 312
 313 /* ----------------------------------------------------------------------- */
 314 /* cx18_av-vbi.c                                                           */
 315 void cx18_av_vbi_setup(struct cx18 *cx);
 316 int cx18_av_vbi(struct cx18 *cx, unsigned int cmd, void *arg);
 317
 318 #endif