drivers/media/video/cx18/cx18-scb.h

   1 /*
   2  *  cx18 System Control Block initialization
   3  *
   4  *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  19  *  02111-1307  USA
  20  */
  21
  22 #ifndef CX18_SCB_H
  23 #define CX18_SCB_H
  24
  25 #include "cx18-mailbox.h"
  26
  27 /* NOTE: All ACK interrupts are in the SW2 register.  All non-ACK interrupts
  28    are in the SW1 register. */
  29
  30 #define IRQ_APU_TO_CPU         0x00000001
  31 #define IRQ_CPU_TO_APU_ACK     0x00000001
  32 #define IRQ_HPU_TO_CPU         0x00000002
  33 #define IRQ_CPU_TO_HPU_ACK     0x00000002
  34 #define IRQ_PPU_TO_CPU         0x00000004
  35 #define IRQ_CPU_TO_PPU_ACK     0x00000004
  36 #define IRQ_EPU_TO_CPU         0x00000008
  37 #define IRQ_CPU_TO_EPU_ACK     0x00000008
  38
  39 #define IRQ_CPU_TO_APU         0x00000010
  40 #define IRQ_APU_TO_CPU_ACK     0x00000010
  41 #define IRQ_HPU_TO_APU         0x00000020
  42 #define IRQ_APU_TO_HPU_ACK     0x00000020
  43 #define IRQ_PPU_TO_APU         0x00000040
  44 #define IRQ_APU_TO_PPU_ACK     0x00000040
  45 #define IRQ_EPU_TO_APU         0x00000080
  46 #define IRQ_APU_TO_EPU_ACK     0x00000080
  47
  48 #define IRQ_CPU_TO_HPU         0x00000100
  49 #define IRQ_HPU_TO_CPU_ACK     0x00000100
  50 #define IRQ_APU_TO_HPU         0x00000200
  51 #define IRQ_HPU_TO_APU_ACK     0x00000200
  52 #define IRQ_PPU_TO_HPU         0x00000400
  53 #define IRQ_HPU_TO_PPU_ACK     0x00000400
  54 #define IRQ_EPU_TO_HPU         0x00000800
  55 #define IRQ_HPU_TO_EPU_ACK     0x00000800
  56
  57 #define IRQ_CPU_TO_PPU         0x00001000
  58 #define IRQ_PPU_TO_CPU_ACK     0x00001000
  59 #define IRQ_APU_TO_PPU         0x00002000
  60 #define IRQ_PPU_TO_APU_ACK     0x00002000
  61 #define IRQ_HPU_TO_PPU         0x00004000
  62 #define IRQ_PPU_TO_HPU_ACK     0x00004000
  63 #define IRQ_EPU_TO_PPU         0x00008000
  64 #define IRQ_PPU_TO_EPU_ACK     0x00008000
  65
  66 #define IRQ_CPU_TO_EPU         0x00010000
  67 #define IRQ_EPU_TO_CPU_ACK     0x00010000
  68 #define IRQ_APU_TO_EPU         0x00020000
  69 #define IRQ_EPU_TO_APU_ACK     0x00020000
  70 #define IRQ_HPU_TO_EPU         0x00040000
  71 #define IRQ_EPU_TO_HPU_ACK     0x00040000
  72 #define IRQ_PPU_TO_EPU         0x00080000
  73 #define IRQ_EPU_TO_PPU_ACK     0x00080000
  74
  75 #define SCB_OFFSET  0xDC0000
  76
  77 /* If Firmware uses fixed memory map, it shall not allocate the area
  78    between SCB_OFFSET and SCB_OFFSET+SCB_RESERVED_SIZE-1 inclusive */
  79 #define SCB_RESERVED_SIZE 0x10000
  80
  81
  82 /* This structure is used by EPU to provide memory descriptors in its memory */
  83 struct cx18_mdl {
  84     u32 paddr;  /* Physical address of a buffer segment */
  85     u32 length; /* Length of the buffer segment */
  86 };
  87
  88 /* This structure is used by CPU to provide completed buffers information */
  89 struct cx18_mdl_ack {
  90     u32 id;        /* ID of a completed MDL */
  91     u32 data_used; /* Total data filled in the MDL for buffer 'id' */
  92 };
  93
  94 struct cx18_scb {
  95         /* These fields form the System Control Block which is used at boot time
  96            for localizing the IPC data as well as the code positions for all
  97            processors. The offsets are from the start of this struct. */
  98
  99         /* Offset where to find the Inter-Processor Communication data */
 100         u32 ipc_offset;
 101         u32 reserved01[7];
 102         /* Offset where to find the start of the CPU code */
 103         u32 cpu_code_offset;
 104         u32 reserved02[3];
 105         /* Offset where to find the start of the APU code */
 106         u32 apu_code_offset;
 107         u32 reserved03[3];
 108         /* Offset where to find the start of the HPU code */
 109         u32 hpu_code_offset;
 110         u32 reserved04[3];
 111         /* Offset where to find the start of the PPU code */
 112         u32 ppu_code_offset;
 113         u32 reserved05[3];
 114
 115         /* These fields form Inter-Processor Communication data which is used
 116            by all processors to locate the information needed for communicating
 117            with other processors */
 118
 119         /* Fields for CPU: */
 120
 121         /* bit 0: 1/0 processor ready/not ready. Set other bits to 0. */
 122         u32 cpu_state;
 123         u32 reserved1[7];
 124         /* Offset to the mailbox used for sending commands from APU to CPU */
 125         u32 apu2cpu_mb_offset;
 126         /* Value to write to register SW1 register set (0xC7003100) after the
 127            command is ready */
 128         u32 apu2cpu_irq;
 129         /* Value to write to register SW2 register set (0xC7003140) after the
 130            command is cleared */
 131         u32 apu2cpu_irq_ack;
 132         u32 reserved2[13];
 133
 134         u32 hpu2cpu_mb_offset;
 135         u32 hpu2cpu_irq;
 136         u32 hpu2cpu_irq_ack;
 137         u32 reserved3[13];
 138
 139         u32 ppu2cpu_mb_offset;
 140         u32 ppu2cpu_irq;
 141         u32 ppu2cpu_irq_ack;
 142         u32 reserved4[13];
 143
 144         u32 epu2cpu_mb_offset;
 145         u32 epu2cpu_irq;
 146         u32 epu2cpu_irq_ack;
 147         u32 reserved5[13];
 148         u32 reserved6[8];
 149
 150         /* Fields for APU: */
 151
 152         u32 apu_state;
 153         u32 reserved11[7];
 154         u32 cpu2apu_mb_offset;
 155         u32 cpu2apu_irq;
 156         u32 cpu2apu_irq_ack;
 157         u32 reserved12[13];
 158
 159         u32 hpu2apu_mb_offset;
 160         u32 hpu2apu_irq;
 161         u32 hpu2apu_irq_ack;
 162         u32 reserved13[13];
 163
 164         u32 ppu2apu_mb_offset;
 165         u32 ppu2apu_irq;
 166         u32 ppu2apu_irq_ack;
 167         u32 reserved14[13];
 168
 169         u32 epu2apu_mb_offset;
 170         u32 epu2apu_irq;
 171         u32 epu2apu_irq_ack;
 172         u32 reserved15[13];
 173         u32 reserved16[8];
 174
 175         /* Fields for HPU: */
 176
 177         u32 hpu_state;
 178         u32 reserved21[7];
 179         u32 cpu2hpu_mb_offset;
 180         u32 cpu2hpu_irq;
 181         u32 cpu2hpu_irq_ack;
 182         u32 reserved22[13];
 183
 184         u32 apu2hpu_mb_offset;
 185         u32 apu2hpu_irq;
 186         u32 apu2hpu_irq_ack;
 187         u32 reserved23[13];
 188
 189         u32 ppu2hpu_mb_offset;
 190         u32 ppu2hpu_irq;
 191         u32 ppu2hpu_irq_ack;
 192         u32 reserved24[13];
 193
 194         u32 epu2hpu_mb_offset;
 195         u32 epu2hpu_irq;
 196         u32 epu2hpu_irq_ack;
 197         u32 reserved25[13];
 198         u32 reserved26[8];
 199
 200         /* Fields for PPU: */
 201
 202         u32 ppu_state;
 203         u32 reserved31[7];
 204         u32 cpu2ppu_mb_offset;
 205         u32 cpu2ppu_irq;
 206         u32 cpu2ppu_irq_ack;
 207         u32 reserved32[13];
 208
 209         u32 apu2ppu_mb_offset;
 210         u32 apu2ppu_irq;
 211         u32 apu2ppu_irq_ack;
 212         u32 reserved33[13];
 213
 214         u32 hpu2ppu_mb_offset;
 215         u32 hpu2ppu_irq;
 216         u32 hpu2ppu_irq_ack;
 217         u32 reserved34[13];
 218
 219         u32 epu2ppu_mb_offset;
 220         u32 epu2ppu_irq;
 221         u32 epu2ppu_irq_ack;
 222         u32 reserved35[13];
 223         u32 reserved36[8];
 224
 225         /* Fields for EPU: */
 226
 227         u32 epu_state;
 228         u32 reserved41[7];
 229         u32 cpu2epu_mb_offset;
 230         u32 cpu2epu_irq;
 231         u32 cpu2epu_irq_ack;
 232         u32 reserved42[13];
 233
 234         u32 apu2epu_mb_offset;
 235         u32 apu2epu_irq;
 236         u32 apu2epu_irq_ack;
 237         u32 reserved43[13];
 238
 239         u32 hpu2epu_mb_offset;
 240         u32 hpu2epu_irq;
 241         u32 hpu2epu_irq_ack;
 242         u32 reserved44[13];
 243
 244         u32 ppu2epu_mb_offset;
 245         u32 ppu2epu_irq;
 246         u32 ppu2epu_irq_ack;
 247         u32 reserved45[13];
 248         u32 reserved46[8];
 249
 250         u32 semaphores[8];  /* Semaphores */
 251
 252         u32 reserved50[32]; /* Reserved for future use */
 253
 254         struct cx18_mailbox  apu2cpu_mb;
 255         struct cx18_mailbox  hpu2cpu_mb;
 256         struct cx18_mailbox  ppu2cpu_mb;
 257         struct cx18_mailbox  epu2cpu_mb;
 258
 259         struct cx18_mailbox  cpu2apu_mb;
 260         struct cx18_mailbox  hpu2apu_mb;
 261         struct cx18_mailbox  ppu2apu_mb;
 262         struct cx18_mailbox  epu2apu_mb;
 263
 264         struct cx18_mailbox  cpu2hpu_mb;
 265         struct cx18_mailbox  apu2hpu_mb;
 266         struct cx18_mailbox  ppu2hpu_mb;
 267         struct cx18_mailbox  epu2hpu_mb;
 268
 269         struct cx18_mailbox  cpu2ppu_mb;
 270         struct cx18_mailbox  apu2ppu_mb;
 271         struct cx18_mailbox  hpu2ppu_mb;
 272         struct cx18_mailbox  epu2ppu_mb;
 273
 274         struct cx18_mailbox  cpu2epu_mb;
 275         struct cx18_mailbox  apu2epu_mb;
 276         struct cx18_mailbox  hpu2epu_mb;
 277         struct cx18_mailbox  ppu2epu_mb;
 278
 279         struct cx18_mdl_ack  cpu_mdl_ack[CX18_MAX_STREAMS][2];
 280         struct cx18_mdl      cpu_mdl[1];
 281 };
 282
 283 void cx18_init_scb(struct cx18 *cx);
 284
 285 #endif