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PRCM: 34XX: Fix wrong shift value used in dpll4_m4x2_ck enable bit
[linux-ginger.git] / drivers / usb / gadget / m66592-udc.c
blobee6b35fa870f9ef6ff9807b2abf33a7400da4861
1 /*
2 * M66592 UDC (USB gadget)
3 *
4 * Copyright (C) 2006-2007 Renesas Solutions Corp.
5 *
6 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 *
21 */
22
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include <linux/io.h>
27 #include <linux/platform_device.h>
28
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
31
32 #include "m66592-udc.h"
33
34
35 MODULE_DESCRIPTION("M66592 USB gadget driver");
36 MODULE_LICENSE("GPL");
37 MODULE_AUTHOR("Yoshihiro Shimoda");
38 MODULE_ALIAS("platform:m66592_udc");
39
40 #define DRIVER_VERSION "18 Oct 2007"
41
42 /* module parameters */
43 #if defined(CONFIG_SUPERH_BUILT_IN_M66592)
44 static unsigned short endian = M66592_LITTLE;
45 module_param(endian, ushort, 0644);
46 MODULE_PARM_DESC(endian, "data endian: big=0, little=0 (default=0)");
47 #else
48 static unsigned short clock = M66592_XTAL24;
49 module_param(clock, ushort, 0644);
50 MODULE_PARM_DESC(clock, "input clock: 48MHz=32768, 24MHz=16384, 12MHz=0 "
51 "(default=16384)");
52
53 static unsigned short vif = M66592_LDRV;
54 module_param(vif, ushort, 0644);
55 MODULE_PARM_DESC(vif, "input VIF: 3.3V=32768, 1.5V=0 (default=32768)");
56
57 static unsigned short endian;
58 module_param(endian, ushort, 0644);
59 MODULE_PARM_DESC(endian, "data endian: big=256, little=0 (default=0)");
60
61 static unsigned short irq_sense = M66592_INTL;
62 module_param(irq_sense, ushort, 0644);
63 MODULE_PARM_DESC(irq_sense, "IRQ sense: low level=2, falling edge=0 "
64 "(default=2)");
65 #endif
66
67 static const char udc_name[] = "m66592_udc";
68 static const char *m66592_ep_name[] = {
69 "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7"
70 };
71
72 static void disable_controller(struct m66592 *m66592);
73 static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req);
74 static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req);
75 static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
76 gfp_t gfp_flags);
77
78 static void transfer_complete(struct m66592_ep *ep,
79 struct m66592_request *req, int status);
80
81 /*-------------------------------------------------------------------------*/
82 static inline u16 get_usb_speed(struct m66592 *m66592)
83 {
84 return (m66592_read(m66592, M66592_DVSTCTR) & M66592_RHST);
85 }
86
87 static void enable_pipe_irq(struct m66592 *m66592, u16 pipenum,
88 unsigned long reg)
89 {
90 u16 tmp;
91
92 tmp = m66592_read(m66592, M66592_INTENB0);
93 m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
94 M66592_INTENB0);
95 m66592_bset(m66592, (1 << pipenum), reg);
96 m66592_write(m66592, tmp, M66592_INTENB0);
97 }
98
99 static void disable_pipe_irq(struct m66592 *m66592, u16 pipenum,
100 unsigned long reg)
101 {
102 u16 tmp;
103
104 tmp = m66592_read(m66592, M66592_INTENB0);
105 m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
106 M66592_INTENB0);
107 m66592_bclr(m66592, (1 << pipenum), reg);
108 m66592_write(m66592, tmp, M66592_INTENB0);
109 }
110
111 static void m66592_usb_connect(struct m66592 *m66592)
112 {
113 m66592_bset(m66592, M66592_CTRE, M66592_INTENB0);
114 m66592_bset(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
115 M66592_INTENB0);
116 m66592_bset(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
117
118 m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG);
119 }
120
121 static void m66592_usb_disconnect(struct m66592 *m66592)
122 __releases(m66592->lock)
123 __acquires(m66592->lock)
124 {
125 m66592_bclr(m66592, M66592_CTRE, M66592_INTENB0);
126 m66592_bclr(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
127 M66592_INTENB0);
128 m66592_bclr(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
129 m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
130
131 m66592->gadget.speed = USB_SPEED_UNKNOWN;
132 spin_unlock(&m66592->lock);
133 m66592->driver->disconnect(&m66592->gadget);
134 spin_lock(&m66592->lock);
135
136 disable_controller(m66592);
137 INIT_LIST_HEAD(&m66592->ep[0].queue);
138 }
139
140 static inline u16 control_reg_get_pid(struct m66592 *m66592, u16 pipenum)
141 {
142 u16 pid = 0;
143 unsigned long offset;
144
145 if (pipenum == 0)
146 pid = m66592_read(m66592, M66592_DCPCTR) & M66592_PID;
147 else if (pipenum < M66592_MAX_NUM_PIPE) {
148 offset = get_pipectr_addr(pipenum);
149 pid = m66592_read(m66592, offset) & M66592_PID;
150 } else
151 pr_err("unexpect pipe num (%d)\n", pipenum);
152
153 return pid;
154 }
155
156 static inline void control_reg_set_pid(struct m66592 *m66592, u16 pipenum,
157 u16 pid)
158 {
159 unsigned long offset;
160
161 if (pipenum == 0)
162 m66592_mdfy(m66592, pid, M66592_PID, M66592_DCPCTR);
163 else if (pipenum < M66592_MAX_NUM_PIPE) {
164 offset = get_pipectr_addr(pipenum);
165 m66592_mdfy(m66592, pid, M66592_PID, offset);
166 } else
167 pr_err("unexpect pipe num (%d)\n", pipenum);
168 }
169
170 static inline void pipe_start(struct m66592 *m66592, u16 pipenum)
171 {
172 control_reg_set_pid(m66592, pipenum, M66592_PID_BUF);
173 }
174
175 static inline void pipe_stop(struct m66592 *m66592, u16 pipenum)
176 {
177 control_reg_set_pid(m66592, pipenum, M66592_PID_NAK);
178 }
179
180 static inline void pipe_stall(struct m66592 *m66592, u16 pipenum)
181 {
182 control_reg_set_pid(m66592, pipenum, M66592_PID_STALL);
183 }
184
185 static inline u16 control_reg_get(struct m66592 *m66592, u16 pipenum)
186 {
187 u16 ret = 0;
188 unsigned long offset;
189
190 if (pipenum == 0)
191 ret = m66592_read(m66592, M66592_DCPCTR);
192 else if (pipenum < M66592_MAX_NUM_PIPE) {
193 offset = get_pipectr_addr(pipenum);
194 ret = m66592_read(m66592, offset);
195 } else
196 pr_err("unexpect pipe num (%d)\n", pipenum);
197
198 return ret;
199 }
200
201 static inline void control_reg_sqclr(struct m66592 *m66592, u16 pipenum)
202 {
203 unsigned long offset;
204
205 pipe_stop(m66592, pipenum);
206
207 if (pipenum == 0)
208 m66592_bset(m66592, M66592_SQCLR, M66592_DCPCTR);
209 else if (pipenum < M66592_MAX_NUM_PIPE) {
210 offset = get_pipectr_addr(pipenum);
211 m66592_bset(m66592, M66592_SQCLR, offset);
212 } else
213 pr_err("unexpect pipe num(%d)\n", pipenum);
214 }
215
216 static inline int get_buffer_size(struct m66592 *m66592, u16 pipenum)
217 {
218 u16 tmp;
219 int size;
220
221 if (pipenum == 0) {
222 tmp = m66592_read(m66592, M66592_DCPCFG);
223 if ((tmp & M66592_CNTMD) != 0)
224 size = 256;
225 else {
226 tmp = m66592_read(m66592, M66592_DCPMAXP);
227 size = tmp & M66592_MAXP;
228 }
229 } else {
230 m66592_write(m66592, pipenum, M66592_PIPESEL);
231 tmp = m66592_read(m66592, M66592_PIPECFG);
232 if ((tmp & M66592_CNTMD) != 0) {
233 tmp = m66592_read(m66592, M66592_PIPEBUF);
234 size = ((tmp >> 10) + 1) * 64;
235 } else {
236 tmp = m66592_read(m66592, M66592_PIPEMAXP);
237 size = tmp & M66592_MXPS;
238 }
239 }
240
241 return size;
242 }
243
244 static inline void pipe_change(struct m66592 *m66592, u16 pipenum)
245 {
246 struct m66592_ep *ep = m66592->pipenum2ep[pipenum];
247
248 if (ep->use_dma)
249 return;
250
251 m66592_mdfy(m66592, pipenum, M66592_CURPIPE, ep->fifosel);
252
253 ndelay(450);
254
255 m66592_bset(m66592, M66592_MBW, ep->fifosel);
256 }
257
258 static int pipe_buffer_setting(struct m66592 *m66592,
259 struct m66592_pipe_info *info)
260 {
261 u16 bufnum = 0, buf_bsize = 0;
262 u16 pipecfg = 0;
263
264 if (info->pipe == 0)
265 return -EINVAL;
266
267 m66592_write(m66592, info->pipe, M66592_PIPESEL);
268
269 if (info->dir_in)
270 pipecfg |= M66592_DIR;
271 pipecfg |= info->type;
272 pipecfg |= info->epnum;
273 switch (info->type) {
274 case M66592_INT:
275 bufnum = 4 + (info->pipe - M66592_BASE_PIPENUM_INT);
276 buf_bsize = 0;
277 break;
278 case M66592_BULK:
279 bufnum = m66592->bi_bufnum +
280 (info->pipe - M66592_BASE_PIPENUM_BULK) * 16;
281 m66592->bi_bufnum += 16;
282 buf_bsize = 7;
283 pipecfg |= M66592_DBLB;
284 if (!info->dir_in)
285 pipecfg |= M66592_SHTNAK;
286 break;
287 case M66592_ISO:
288 bufnum = m66592->bi_bufnum +
289 (info->pipe - M66592_BASE_PIPENUM_ISOC) * 16;
290 m66592->bi_bufnum += 16;
291 buf_bsize = 7;
292 break;
293 }
294 if (m66592->bi_bufnum > M66592_MAX_BUFNUM) {
295 pr_err("m66592 pipe memory is insufficient(%d)\n",
296 m66592->bi_bufnum);
297 return -ENOMEM;
298 }
299
300 m66592_write(m66592, pipecfg, M66592_PIPECFG);
301 m66592_write(m66592, (buf_bsize << 10) | (bufnum), M66592_PIPEBUF);
302 m66592_write(m66592, info->maxpacket, M66592_PIPEMAXP);
303 if (info->interval)
304 info->interval--;
305 m66592_write(m66592, info->interval, M66592_PIPEPERI);
306
307 return 0;
308 }
309
310 static void pipe_buffer_release(struct m66592 *m66592,
311 struct m66592_pipe_info *info)
312 {
313 if (info->pipe == 0)
314 return;
315
316 switch (info->type) {
317 case M66592_BULK:
318 if (is_bulk_pipe(info->pipe))
319 m66592->bi_bufnum -= 16;
320 break;
321 case M66592_ISO:
322 if (is_isoc_pipe(info->pipe))
323 m66592->bi_bufnum -= 16;
324 break;
325 }
326
327 if (is_bulk_pipe(info->pipe)) {
328 m66592->bulk--;
329 } else if (is_interrupt_pipe(info->pipe))
330 m66592->interrupt--;
331 else if (is_isoc_pipe(info->pipe)) {
332 m66592->isochronous--;
333 if (info->type == M66592_BULK)
334 m66592->bulk--;
335 } else
336 pr_err("ep_release: unexpect pipenum (%d)\n",
337 info->pipe);
338 }
339
340 static void pipe_initialize(struct m66592_ep *ep)
341 {
342 struct m66592 *m66592 = ep->m66592;
343
344 m66592_mdfy(m66592, 0, M66592_CURPIPE, ep->fifosel);
345
346 m66592_write(m66592, M66592_ACLRM, ep->pipectr);
347 m66592_write(m66592, 0, ep->pipectr);
348 m66592_write(m66592, M66592_SQCLR, ep->pipectr);
349 if (ep->use_dma) {
350 m66592_mdfy(m66592, ep->pipenum, M66592_CURPIPE, ep->fifosel);
351
352 ndelay(450);
353
354 m66592_bset(m66592, M66592_MBW, ep->fifosel);
355 }
356 }
357
358 static void m66592_ep_setting(struct m66592 *m66592, struct m66592_ep *ep,
359 const struct usb_endpoint_descriptor *desc,
360 u16 pipenum, int dma)
361 {
362 if ((pipenum != 0) && dma) {
363 if (m66592->num_dma == 0) {
364 m66592->num_dma++;
365 ep->use_dma = 1;
366 ep->fifoaddr = M66592_D0FIFO;
367 ep->fifosel = M66592_D0FIFOSEL;
368 ep->fifoctr = M66592_D0FIFOCTR;
369 ep->fifotrn = M66592_D0FIFOTRN;
370 #if !defined(CONFIG_SUPERH_BUILT_IN_M66592)
371 } else if (m66592->num_dma == 1) {
372 m66592->num_dma++;
373 ep->use_dma = 1;
374 ep->fifoaddr = M66592_D1FIFO;
375 ep->fifosel = M66592_D1FIFOSEL;
376 ep->fifoctr = M66592_D1FIFOCTR;
377 ep->fifotrn = M66592_D1FIFOTRN;
378 #endif
379 } else {
380 ep->use_dma = 0;
381 ep->fifoaddr = M66592_CFIFO;
382 ep->fifosel = M66592_CFIFOSEL;
383 ep->fifoctr = M66592_CFIFOCTR;
384 ep->fifotrn = 0;
385 }
386 } else {
387 ep->use_dma = 0;
388 ep->fifoaddr = M66592_CFIFO;
389 ep->fifosel = M66592_CFIFOSEL;
390 ep->fifoctr = M66592_CFIFOCTR;
391 ep->fifotrn = 0;
392 }
393
394 ep->pipectr = get_pipectr_addr(pipenum);
395 ep->pipenum = pipenum;
396 ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
397 m66592->pipenum2ep[pipenum] = ep;
398 m66592->epaddr2ep[desc->bEndpointAddress&USB_ENDPOINT_NUMBER_MASK] = ep;
399 INIT_LIST_HEAD(&ep->queue);
400 }
401
402 static void m66592_ep_release(struct m66592_ep *ep)
403 {
404 struct m66592 *m66592 = ep->m66592;
405 u16 pipenum = ep->pipenum;
406
407 if (pipenum == 0)
408 return;
409
410 if (ep->use_dma)
411 m66592->num_dma--;
412 ep->pipenum = 0;
413 ep->busy = 0;
414 ep->use_dma = 0;
415 }
416
417 static int alloc_pipe_config(struct m66592_ep *ep,
418 const struct usb_endpoint_descriptor *desc)
419 {
420 struct m66592 *m66592 = ep->m66592;
421 struct m66592_pipe_info info;
422 int dma = 0;
423 int *counter;
424 int ret;
425
426 ep->desc = desc;
427
428 BUG_ON(ep->pipenum);
429
430 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
431 case USB_ENDPOINT_XFER_BULK:
432 if (m66592->bulk >= M66592_MAX_NUM_BULK) {
433 if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
434 pr_err("bulk pipe is insufficient\n");
435 return -ENODEV;
436 } else {
437 info.pipe = M66592_BASE_PIPENUM_ISOC
438 + m66592->isochronous;
439 counter = &m66592->isochronous;
440 }
441 } else {
442 info.pipe = M66592_BASE_PIPENUM_BULK + m66592->bulk;
443 counter = &m66592->bulk;
444 }
445 info.type = M66592_BULK;
446 dma = 1;
447 break;
448 case USB_ENDPOINT_XFER_INT:
449 if (m66592->interrupt >= M66592_MAX_NUM_INT) {
450 pr_err("interrupt pipe is insufficient\n");
451 return -ENODEV;
452 }
453 info.pipe = M66592_BASE_PIPENUM_INT + m66592->interrupt;
454 info.type = M66592_INT;
455 counter = &m66592->interrupt;
456 break;
457 case USB_ENDPOINT_XFER_ISOC:
458 if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
459 pr_err("isochronous pipe is insufficient\n");
460 return -ENODEV;
461 }
462 info.pipe = M66592_BASE_PIPENUM_ISOC + m66592->isochronous;
463 info.type = M66592_ISO;
464 counter = &m66592->isochronous;
465 break;
466 default:
467 pr_err("unexpect xfer type\n");
468 return -EINVAL;
469 }
470 ep->type = info.type;
471
472 info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
473 info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
474 info.interval = desc->bInterval;
475 if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
476 info.dir_in = 1;
477 else
478 info.dir_in = 0;
479
480 ret = pipe_buffer_setting(m66592, &info);
481 if (ret < 0) {
482 pr_err("pipe_buffer_setting fail\n");
483 return ret;
484 }
485
486 (*counter)++;
487 if ((counter == &m66592->isochronous) && info.type == M66592_BULK)
488 m66592->bulk++;
489
490 m66592_ep_setting(m66592, ep, desc, info.pipe, dma);
491 pipe_initialize(ep);
492
493 return 0;
494 }
495
496 static int free_pipe_config(struct m66592_ep *ep)
497 {
498 struct m66592 *m66592 = ep->m66592;
499 struct m66592_pipe_info info;
500
501 info.pipe = ep->pipenum;
502 info.type = ep->type;
503 pipe_buffer_release(m66592, &info);
504 m66592_ep_release(ep);
505
506 return 0;
507 }
508
509 /*-------------------------------------------------------------------------*/
510 static void pipe_irq_enable(struct m66592 *m66592, u16 pipenum)
511 {
512 enable_irq_ready(m66592, pipenum);
513 enable_irq_nrdy(m66592, pipenum);
514 }
515
516 static void pipe_irq_disable(struct m66592 *m66592, u16 pipenum)
517 {
518 disable_irq_ready(m66592, pipenum);
519 disable_irq_nrdy(m66592, pipenum);
520 }
521
522 /* if complete is true, gadget driver complete function is not call */
523 static void control_end(struct m66592 *m66592, unsigned ccpl)
524 {
525 m66592->ep[0].internal_ccpl = ccpl;
526 pipe_start(m66592, 0);
527 m66592_bset(m66592, M66592_CCPL, M66592_DCPCTR);
528 }
529
530 static void start_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
531 {
532 struct m66592 *m66592 = ep->m66592;
533
534 pipe_change(m66592, ep->pipenum);
535 m66592_mdfy(m66592, M66592_ISEL | M66592_PIPE0,
536 (M66592_ISEL | M66592_CURPIPE),
537 M66592_CFIFOSEL);
538 m66592_write(m66592, M66592_BCLR, ep->fifoctr);
539 if (req->req.length == 0) {
540 m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
541 pipe_start(m66592, 0);
542 transfer_complete(ep, req, 0);
543 } else {
544 m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
545 irq_ep0_write(ep, req);
546 }
547 }
548
549 static void start_packet_write(struct m66592_ep *ep, struct m66592_request *req)
550 {
551 struct m66592 *m66592 = ep->m66592;
552 u16 tmp;
553
554 pipe_change(m66592, ep->pipenum);
555 disable_irq_empty(m66592, ep->pipenum);
556 pipe_start(m66592, ep->pipenum);
557
558 tmp = m66592_read(m66592, ep->fifoctr);
559 if (unlikely((tmp & M66592_FRDY) == 0))
560 pipe_irq_enable(m66592, ep->pipenum);
561 else
562 irq_packet_write(ep, req);
563 }
564
565 static void start_packet_read(struct m66592_ep *ep, struct m66592_request *req)
566 {
567 struct m66592 *m66592 = ep->m66592;
568 u16 pipenum = ep->pipenum;
569
570 if (ep->pipenum == 0) {
571 m66592_mdfy(m66592, M66592_PIPE0,
572 (M66592_ISEL | M66592_CURPIPE),
573 M66592_CFIFOSEL);
574 m66592_write(m66592, M66592_BCLR, ep->fifoctr);
575 pipe_start(m66592, pipenum);
576 pipe_irq_enable(m66592, pipenum);
577 } else {
578 if (ep->use_dma) {
579 m66592_bset(m66592, M66592_TRCLR, ep->fifosel);
580 pipe_change(m66592, pipenum);
581 m66592_bset(m66592, M66592_TRENB, ep->fifosel);
582 m66592_write(m66592,
583 (req->req.length + ep->ep.maxpacket - 1)
584 / ep->ep.maxpacket,
585 ep->fifotrn);
586 }
587 pipe_start(m66592, pipenum); /* trigger once */
588 pipe_irq_enable(m66592, pipenum);
589 }
590 }
591
592 static void start_packet(struct m66592_ep *ep, struct m66592_request *req)
593 {
594 if (ep->desc->bEndpointAddress & USB_DIR_IN)
595 start_packet_write(ep, req);
596 else
597 start_packet_read(ep, req);
598 }
599
600 static void start_ep0(struct m66592_ep *ep, struct m66592_request *req)
601 {
602 u16 ctsq;
603
604 ctsq = m66592_read(ep->m66592, M66592_INTSTS0) & M66592_CTSQ;
605
606 switch (ctsq) {
607 case M66592_CS_RDDS:
608 start_ep0_write(ep, req);
609 break;
610 case M66592_CS_WRDS:
611 start_packet_read(ep, req);
612 break;
613
614 case M66592_CS_WRND:
615 control_end(ep->m66592, 0);
616 break;
617 default:
618 pr_err("start_ep0: unexpect ctsq(%x)\n", ctsq);
619 break;
620 }
621 }
622
623 #if defined(CONFIG_SUPERH_BUILT_IN_M66592)
624 static void init_controller(struct m66592 *m66592)
625 {
626 usbf_start_clock();
627 m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
628 m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
629 m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
630 m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
631
632 /* This is a workaound for SH7722 2nd cut */
633 m66592_bset(m66592, 0x8000, M66592_DVSTCTR);
634 m66592_bset(m66592, 0x1000, M66592_TESTMODE);
635 m66592_bclr(m66592, 0x8000, M66592_DVSTCTR);
636
637 m66592_bset(m66592, M66592_INTL, M66592_INTENB1);
638
639 m66592_write(m66592, 0, M66592_CFBCFG);
640 m66592_write(m66592, 0, M66592_D0FBCFG);
641 m66592_bset(m66592, endian, M66592_CFBCFG);
642 m66592_bset(m66592, endian, M66592_D0FBCFG);
643 }
644 #else /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */
645 static void init_controller(struct m66592 *m66592)
646 {
647 m66592_bset(m66592, (vif & M66592_LDRV) | (endian & M66592_BIGEND),
648 M66592_PINCFG);
649 m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
650 m66592_mdfy(m66592, clock & M66592_XTAL, M66592_XTAL, M66592_SYSCFG);
651
652 m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
653 m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
654 m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
655
656 m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
657
658 msleep(3);
659
660 m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
661
662 msleep(1);
663
664 m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
665
666 m66592_bset(m66592, irq_sense & M66592_INTL, M66592_INTENB1);
667 m66592_write(m66592, M66592_BURST | M66592_CPU_ADR_RD_WR,
668 M66592_DMA0CFG);
669 }
670 #endif /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */
671
672 static void disable_controller(struct m66592 *m66592)
673 {
674 #if defined(CONFIG_SUPERH_BUILT_IN_M66592)
675 usbf_stop_clock();
676 #else
677 m66592_bclr(m66592, M66592_SCKE, M66592_SYSCFG);
678 udelay(1);
679 m66592_bclr(m66592, M66592_PLLC, M66592_SYSCFG);
680 udelay(1);
681 m66592_bclr(m66592, M66592_RCKE, M66592_SYSCFG);
682 udelay(1);
683 m66592_bclr(m66592, M66592_XCKE, M66592_SYSCFG);
684 #endif
685 }
686
687 static void m66592_start_xclock(struct m66592 *m66592)
688 {
689 #if defined(CONFIG_SUPERH_BUILT_IN_M66592)
690 usbf_start_clock();
691 #else
692 u16 tmp;
693
694 tmp = m66592_read(m66592, M66592_SYSCFG);
695 if (!(tmp & M66592_XCKE))
696 m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
697 #endif
698 }
699
700 /*-------------------------------------------------------------------------*/
701 static void transfer_complete(struct m66592_ep *ep,
702 struct m66592_request *req, int status)
703 __releases(m66592->lock)
704 __acquires(m66592->lock)
705 {
706 int restart = 0;
707
708 if (unlikely(ep->pipenum == 0)) {
709 if (ep->internal_ccpl) {
710 ep->internal_ccpl = 0;
711 return;
712 }
713 }
714
715 list_del_init(&req->queue);
716 if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
717 req->req.status = -ESHUTDOWN;
718 else
719 req->req.status = status;
720
721 if (!list_empty(&ep->queue))
722 restart = 1;
723
724 spin_unlock(&ep->m66592->lock);
725 req->req.complete(&ep->ep, &req->req);
726 spin_lock(&ep->m66592->lock);
727
728 if (restart) {
729 req = list_entry(ep->queue.next, struct m66592_request, queue);
730 if (ep->desc)
731 start_packet(ep, req);
732 }
733 }
734
735 static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
736 {
737 int i;
738 u16 tmp;
739 unsigned bufsize;
740 size_t size;
741 void *buf;
742 u16 pipenum = ep->pipenum;
743 struct m66592 *m66592 = ep->m66592;
744
745 pipe_change(m66592, pipenum);
746 m66592_bset(m66592, M66592_ISEL, ep->fifosel);
747
748 i = 0;
749 do {
750 tmp = m66592_read(m66592, ep->fifoctr);
751 if (i++ > 100000) {
752 pr_err("pipe0 is busy. maybe cpu i/o bus "
753 "conflict. please power off this controller.");
754 return;
755 }
756 ndelay(1);
757 } while ((tmp & M66592_FRDY) == 0);
758
759 /* prepare parameters */
760 bufsize = get_buffer_size(m66592, pipenum);
761 buf = req->req.buf + req->req.actual;
762 size = min(bufsize, req->req.length - req->req.actual);
763
764 /* write fifo */
765 if (req->req.buf) {
766 if (size > 0)
767 m66592_write_fifo(m66592, ep->fifoaddr, buf, size);
768 if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
769 m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
770 }
771
772 /* update parameters */
773 req->req.actual += size;
774
775 /* check transfer finish */
776 if ((!req->req.zero && (req->req.actual == req->req.length))
777 || (size % ep->ep.maxpacket)
778 || (size == 0)) {
779 disable_irq_ready(m66592, pipenum);
780 disable_irq_empty(m66592, pipenum);
781 } else {
782 disable_irq_ready(m66592, pipenum);
783 enable_irq_empty(m66592, pipenum);
784 }
785 pipe_start(m66592, pipenum);
786 }
787
788 static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req)
789 {
790 u16 tmp;
791 unsigned bufsize;
792 size_t size;
793 void *buf;
794 u16 pipenum = ep->pipenum;
795 struct m66592 *m66592 = ep->m66592;
796
797 pipe_change(m66592, pipenum);
798 tmp = m66592_read(m66592, ep->fifoctr);
799 if (unlikely((tmp & M66592_FRDY) == 0)) {
800 pipe_stop(m66592, pipenum);
801 pipe_irq_disable(m66592, pipenum);
802 pr_err("write fifo not ready. pipnum=%d\n", pipenum);
803 return;
804 }
805
806 /* prepare parameters */
807 bufsize = get_buffer_size(m66592, pipenum);
808 buf = req->req.buf + req->req.actual;
809 size = min(bufsize, req->req.length - req->req.actual);
810
811 /* write fifo */
812 if (req->req.buf) {
813 m66592_write_fifo(m66592, ep->fifoaddr, buf, size);
814 if ((size == 0)
815 || ((size % ep->ep.maxpacket) != 0)
816 || ((bufsize != ep->ep.maxpacket)
817 && (bufsize > size)))
818 m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
819 }
820
821 /* update parameters */
822 req->req.actual += size;
823 /* check transfer finish */
824 if ((!req->req.zero && (req->req.actual == req->req.length))
825 || (size % ep->ep.maxpacket)
826 || (size == 0)) {
827 disable_irq_ready(m66592, pipenum);
828 enable_irq_empty(m66592, pipenum);
829 } else {
830 disable_irq_empty(m66592, pipenum);
831 pipe_irq_enable(m66592, pipenum);
832 }
833 }
834
835 static void irq_packet_read(struct m66592_ep *ep, struct m66592_request *req)
836 {
837 u16 tmp;
838 int rcv_len, bufsize, req_len;
839 int size;
840 void *buf;
841 u16 pipenum = ep->pipenum;
842 struct m66592 *m66592 = ep->m66592;
843 int finish = 0;
844
845 pipe_change(m66592, pipenum);
846 tmp = m66592_read(m66592, ep->fifoctr);
847 if (unlikely((tmp & M66592_FRDY) == 0)) {
848 req->req.status = -EPIPE;
849 pipe_stop(m66592, pipenum);
850 pipe_irq_disable(m66592, pipenum);
851 pr_err("read fifo not ready");
852 return;
853 }
854
855 /* prepare parameters */
856 rcv_len = tmp & M66592_DTLN;
857 bufsize = get_buffer_size(m66592, pipenum);
858
859 buf = req->req.buf + req->req.actual;
860 req_len = req->req.length - req->req.actual;
861 if (rcv_len < bufsize)
862 size = min(rcv_len, req_len);
863 else
864 size = min(bufsize, req_len);
865
866 /* update parameters */
867 req->req.actual += size;
868
869 /* check transfer finish */
870 if ((!req->req.zero && (req->req.actual == req->req.length))
871 || (size % ep->ep.maxpacket)
872 || (size == 0)) {
873 pipe_stop(m66592, pipenum);
874 pipe_irq_disable(m66592, pipenum);
875 finish = 1;
876 }
877
878 /* read fifo */
879 if (req->req.buf) {
880 if (size == 0)
881 m66592_write(m66592, M66592_BCLR, ep->fifoctr);
882 else
883 m66592_read_fifo(m66592, ep->fifoaddr, buf, size);
884 }
885
886 if ((ep->pipenum != 0) && finish)
887 transfer_complete(ep, req, 0);
888 }
889
890 static void irq_pipe_ready(struct m66592 *m66592, u16 status, u16 enb)
891 {
892 u16 check;
893 u16 pipenum;
894 struct m66592_ep *ep;
895 struct m66592_request *req;
896
897 if ((status & M66592_BRDY0) && (enb & M66592_BRDY0)) {
898 m66592_write(m66592, ~M66592_BRDY0, M66592_BRDYSTS);
899 m66592_mdfy(m66592, M66592_PIPE0, M66592_CURPIPE,
900 M66592_CFIFOSEL);
901
902 ep = &m66592->ep[0];
903 req = list_entry(ep->queue.next, struct m66592_request, queue);
904 irq_packet_read(ep, req);
905 } else {
906 for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
907 check = 1 << pipenum;
908 if ((status & check) && (enb & check)) {
909 m66592_write(m66592, ~check, M66592_BRDYSTS);
910 ep = m66592->pipenum2ep[pipenum];
911 req = list_entry(ep->queue.next,
912 struct m66592_request, queue);
913 if (ep->desc->bEndpointAddress & USB_DIR_IN)
914 irq_packet_write(ep, req);
915 else
916 irq_packet_read(ep, req);
917 }
918 }
919 }
920 }
921
922 static void irq_pipe_empty(struct m66592 *m66592, u16 status, u16 enb)
923 {
924 u16 tmp;
925 u16 check;
926 u16 pipenum;
927 struct m66592_ep *ep;
928 struct m66592_request *req;
929
930 if ((status & M66592_BEMP0) && (enb & M66592_BEMP0)) {
931 m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
932
933 ep = &m66592->ep[0];
934 req = list_entry(ep->queue.next, struct m66592_request, queue);
935 irq_ep0_write(ep, req);
936 } else {
937 for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
938 check = 1 << pipenum;
939 if ((status & check) && (enb & check)) {
940 m66592_write(m66592, ~check, M66592_BEMPSTS);
941 tmp = control_reg_get(m66592, pipenum);
942 if ((tmp & M66592_INBUFM) == 0) {
943 disable_irq_empty(m66592, pipenum);
944 pipe_irq_disable(m66592, pipenum);
945 pipe_stop(m66592, pipenum);
946 ep = m66592->pipenum2ep[pipenum];
947 req = list_entry(ep->queue.next,
948 struct m66592_request,
949 queue);
950 if (!list_empty(&ep->queue))
951 transfer_complete(ep, req, 0);
952 }
953 }
954 }
955 }
956 }
957
958 static void get_status(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
959 __releases(m66592->lock)
960 __acquires(m66592->lock)
961 {
962 struct m66592_ep *ep;
963 u16 pid;
964 u16 status = 0;
965 u16 w_index = le16_to_cpu(ctrl->wIndex);
966
967 switch (ctrl->bRequestType & USB_RECIP_MASK) {
968 case USB_RECIP_DEVICE:
969 status = 1 << USB_DEVICE_SELF_POWERED;
970 break;
971 case USB_RECIP_INTERFACE:
972 status = 0;
973 break;
974 case USB_RECIP_ENDPOINT:
975 ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
976 pid = control_reg_get_pid(m66592, ep->pipenum);
977 if (pid == M66592_PID_STALL)
978 status = 1 << USB_ENDPOINT_HALT;
979 else
980 status = 0;
981 break;
982 default:
983 pipe_stall(m66592, 0);
984 return; /* exit */
985 }
986
987 m66592->ep0_data = cpu_to_le16(status);
988 m66592->ep0_req->buf = &m66592->ep0_data;
989 m66592->ep0_req->length = 2;
990 /* AV: what happens if we get called again before that gets through? */
991 spin_unlock(&m66592->lock);
992 m66592_queue(m66592->gadget.ep0, m66592->ep0_req, GFP_KERNEL);
993 spin_lock(&m66592->lock);
994 }
995
996 static void clear_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
997 {
998 switch (ctrl->bRequestType & USB_RECIP_MASK) {
999 case USB_RECIP_DEVICE:
1000 control_end(m66592, 1);
1001 break;
1002 case USB_RECIP_INTERFACE:
1003 control_end(m66592, 1);
1004 break;
1005 case USB_RECIP_ENDPOINT: {
1006 struct m66592_ep *ep;
1007 struct m66592_request *req;
1008 u16 w_index = le16_to_cpu(ctrl->wIndex);
1009
1010 ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
1011 pipe_stop(m66592, ep->pipenum);
1012 control_reg_sqclr(m66592, ep->pipenum);
1013
1014 control_end(m66592, 1);
1015
1016 req = list_entry(ep->queue.next,
1017 struct m66592_request, queue);
1018 if (ep->busy) {
1019 ep->busy = 0;
1020 if (list_empty(&ep->queue))
1021 break;
1022 start_packet(ep, req);
1023 } else if (!list_empty(&ep->queue))
1024 pipe_start(m66592, ep->pipenum);
1025 }
1026 break;
1027 default:
1028 pipe_stall(m66592, 0);
1029 break;
1030 }
1031 }
1032
1033 static void set_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
1034 {
1035
1036 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1037 case USB_RECIP_DEVICE:
1038 control_end(m66592, 1);
1039 break;
1040 case USB_RECIP_INTERFACE:
1041 control_end(m66592, 1);
1042 break;
1043 case USB_RECIP_ENDPOINT: {
1044 struct m66592_ep *ep;
1045 u16 w_index = le16_to_cpu(ctrl->wIndex);
1046
1047 ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
1048 pipe_stall(m66592, ep->pipenum);
1049
1050 control_end(m66592, 1);
1051 }
1052 break;
1053 default:
1054 pipe_stall(m66592, 0);
1055 break;
1056 }
1057 }
1058
1059 /* if return value is true, call class driver's setup() */
1060 static int setup_packet(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
1061 {
1062 u16 *p = (u16 *)ctrl;
1063 unsigned long offset = M66592_USBREQ;
1064 int i, ret = 0;
1065
1066 /* read fifo */
1067 m66592_write(m66592, ~M66592_VALID, M66592_INTSTS0);
1068
1069 for (i = 0; i < 4; i++)
1070 p[i] = m66592_read(m66592, offset + i*2);
1071
1072 /* check request */
1073 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1074 switch (ctrl->bRequest) {
1075 case USB_REQ_GET_STATUS:
1076 get_status(m66592, ctrl);
1077 break;
1078 case USB_REQ_CLEAR_FEATURE:
1079 clear_feature(m66592, ctrl);
1080 break;
1081 case USB_REQ_SET_FEATURE:
1082 set_feature(m66592, ctrl);
1083 break;
1084 default:
1085 ret = 1;
1086 break;
1087 }
1088 } else
1089 ret = 1;
1090 return ret;
1091 }
1092
1093 static void m66592_update_usb_speed(struct m66592 *m66592)
1094 {
1095 u16 speed = get_usb_speed(m66592);
1096
1097 switch (speed) {
1098 case M66592_HSMODE:
1099 m66592->gadget.speed = USB_SPEED_HIGH;
1100 break;
1101 case M66592_FSMODE:
1102 m66592->gadget.speed = USB_SPEED_FULL;
1103 break;
1104 default:
1105 m66592->gadget.speed = USB_SPEED_UNKNOWN;
1106 pr_err("USB speed unknown\n");
1107 }
1108 }
1109
1110 static void irq_device_state(struct m66592 *m66592)
1111 {
1112 u16 dvsq;
1113
1114 dvsq = m66592_read(m66592, M66592_INTSTS0) & M66592_DVSQ;
1115 m66592_write(m66592, ~M66592_DVST, M66592_INTSTS0);
1116
1117 if (dvsq == M66592_DS_DFLT) { /* bus reset */
1118 m66592->driver->disconnect(&m66592->gadget);
1119 m66592_update_usb_speed(m66592);
1120 }
1121 if (m66592->old_dvsq == M66592_DS_CNFG && dvsq != M66592_DS_CNFG)
1122 m66592_update_usb_speed(m66592);
1123 if ((dvsq == M66592_DS_CNFG || dvsq == M66592_DS_ADDS)
1124 && m66592->gadget.speed == USB_SPEED_UNKNOWN)
1125 m66592_update_usb_speed(m66592);
1126
1127 m66592->old_dvsq = dvsq;
1128 }
1129
1130 static void irq_control_stage(struct m66592 *m66592)
1131 __releases(m66592->lock)
1132 __acquires(m66592->lock)
1133 {
1134 struct usb_ctrlrequest ctrl;
1135 u16 ctsq;
1136
1137 ctsq = m66592_read(m66592, M66592_INTSTS0) & M66592_CTSQ;
1138 m66592_write(m66592, ~M66592_CTRT, M66592_INTSTS0);
1139
1140 switch (ctsq) {
1141 case M66592_CS_IDST: {
1142 struct m66592_ep *ep;
1143 struct m66592_request *req;
1144 ep = &m66592->ep[0];
1145 req = list_entry(ep->queue.next, struct m66592_request, queue);
1146 transfer_complete(ep, req, 0);
1147 }
1148 break;
1149
1150 case M66592_CS_RDDS:
1151 case M66592_CS_WRDS:
1152 case M66592_CS_WRND:
1153 if (setup_packet(m66592, &ctrl)) {
1154 spin_unlock(&m66592->lock);
1155 if (m66592->driver->setup(&m66592->gadget, &ctrl) < 0)
1156 pipe_stall(m66592, 0);
1157 spin_lock(&m66592->lock);
1158 }
1159 break;
1160 case M66592_CS_RDSS:
1161 case M66592_CS_WRSS:
1162 control_end(m66592, 0);
1163 break;
1164 default:
1165 pr_err("ctrl_stage: unexpect ctsq(%x)\n", ctsq);
1166 break;
1167 }
1168 }
1169
1170 static irqreturn_t m66592_irq(int irq, void *_m66592)
1171 {
1172 struct m66592 *m66592 = _m66592;
1173 u16 intsts0;
1174 u16 intenb0;
1175 u16 brdysts, nrdysts, bempsts;
1176 u16 brdyenb, nrdyenb, bempenb;
1177 u16 savepipe;
1178 u16 mask0;
1179
1180 spin_lock(&m66592->lock);
1181
1182 intsts0 = m66592_read(m66592, M66592_INTSTS0);
1183 intenb0 = m66592_read(m66592, M66592_INTENB0);
1184
1185 #if defined(CONFIG_SUPERH_BUILT_IN_M66592)
1186 if (!intsts0 && !intenb0) {
1187 /*
1188 * When USB clock stops, it cannot read register. Even if a
1189 * clock stops, the interrupt occurs. So this driver turn on
1190 * a clock by this timing and do re-reading of register.
1191 */
1192 m66592_start_xclock(m66592);
1193 intsts0 = m66592_read(m66592, M66592_INTSTS0);
1194 intenb0 = m66592_read(m66592, M66592_INTENB0);
1195 }
1196 #endif
1197
1198 savepipe = m66592_read(m66592, M66592_CFIFOSEL);
1199
1200 mask0 = intsts0 & intenb0;
1201 if (mask0) {
1202 brdysts = m66592_read(m66592, M66592_BRDYSTS);
1203 nrdysts = m66592_read(m66592, M66592_NRDYSTS);
1204 bempsts = m66592_read(m66592, M66592_BEMPSTS);
1205 brdyenb = m66592_read(m66592, M66592_BRDYENB);
1206 nrdyenb = m66592_read(m66592, M66592_NRDYENB);
1207 bempenb = m66592_read(m66592, M66592_BEMPENB);
1208
1209 if (mask0 & M66592_VBINT) {
1210 m66592_write(m66592, 0xffff & ~M66592_VBINT,
1211 M66592_INTSTS0);
1212 m66592_start_xclock(m66592);
1213
1214 /* start vbus sampling */
1215 m66592->old_vbus = m66592_read(m66592, M66592_INTSTS0)
1216 & M66592_VBSTS;
1217 m66592->scount = M66592_MAX_SAMPLING;
1218
1219 mod_timer(&m66592->timer,
1220 jiffies + msecs_to_jiffies(50));
1221 }
1222 if (intsts0 & M66592_DVSQ)
1223 irq_device_state(m66592);
1224
1225 if ((intsts0 & M66592_BRDY) && (intenb0 & M66592_BRDYE)
1226 && (brdysts & brdyenb)) {
1227 irq_pipe_ready(m66592, brdysts, brdyenb);
1228 }
1229 if ((intsts0 & M66592_BEMP) && (intenb0 & M66592_BEMPE)
1230 && (bempsts & bempenb)) {
1231 irq_pipe_empty(m66592, bempsts, bempenb);
1232 }
1233
1234 if (intsts0 & M66592_CTRT)
1235 irq_control_stage(m66592);
1236 }
1237
1238 m66592_write(m66592, savepipe, M66592_CFIFOSEL);
1239
1240 spin_unlock(&m66592->lock);
1241 return IRQ_HANDLED;
1242 }
1243
1244 static void m66592_timer(unsigned long _m66592)
1245 {
1246 struct m66592 *m66592 = (struct m66592 *)_m66592;
1247 unsigned long flags;
1248 u16 tmp;
1249
1250 spin_lock_irqsave(&m66592->lock, flags);
1251 tmp = m66592_read(m66592, M66592_SYSCFG);
1252 if (!(tmp & M66592_RCKE)) {
1253 m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
1254 udelay(10);
1255 m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
1256 }
1257 if (m66592->scount > 0) {
1258 tmp = m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS;
1259 if (tmp == m66592->old_vbus) {
1260 m66592->scount--;
1261 if (m66592->scount == 0) {
1262 if (tmp == M66592_VBSTS)
1263 m66592_usb_connect(m66592);
1264 else
1265 m66592_usb_disconnect(m66592);
1266 } else {
1267 mod_timer(&m66592->timer,
1268 jiffies + msecs_to_jiffies(50));
1269 }
1270 } else {
1271 m66592->scount = M66592_MAX_SAMPLING;
1272 m66592->old_vbus = tmp;
1273 mod_timer(&m66592->timer,
1274 jiffies + msecs_to_jiffies(50));
1275 }
1276 }
1277 spin_unlock_irqrestore(&m66592->lock, flags);
1278 }
1279
1280 /*-------------------------------------------------------------------------*/
1281 static int m66592_enable(struct usb_ep *_ep,
1282 const struct usb_endpoint_descriptor *desc)
1283 {
1284 struct m66592_ep *ep;
1285
1286 ep = container_of(_ep, struct m66592_ep, ep);
1287 return alloc_pipe_config(ep, desc);
1288 }
1289
1290 static int m66592_disable(struct usb_ep *_ep)
1291 {
1292 struct m66592_ep *ep;
1293 struct m66592_request *req;
1294 unsigned long flags;
1295
1296 ep = container_of(_ep, struct m66592_ep, ep);
1297 BUG_ON(!ep);
1298
1299 while (!list_empty(&ep->queue)) {
1300 req = list_entry(ep->queue.next, struct m66592_request, queue);
1301 spin_lock_irqsave(&ep->m66592->lock, flags);
1302 transfer_complete(ep, req, -ECONNRESET);
1303 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1304 }
1305
1306 pipe_irq_disable(ep->m66592, ep->pipenum);
1307 return free_pipe_config(ep);
1308 }
1309
1310 static struct usb_request *m66592_alloc_request(struct usb_ep *_ep,
1311 gfp_t gfp_flags)
1312 {
1313 struct m66592_request *req;
1314
1315 req = kzalloc(sizeof(struct m66592_request), gfp_flags);
1316 if (!req)
1317 return NULL;
1318
1319 INIT_LIST_HEAD(&req->queue);
1320
1321 return &req->req;
1322 }
1323
1324 static void m66592_free_request(struct usb_ep *_ep, struct usb_request *_req)
1325 {
1326 struct m66592_request *req;
1327
1328 req = container_of(_req, struct m66592_request, req);
1329 kfree(req);
1330 }
1331
1332 static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
1333 gfp_t gfp_flags)
1334 {
1335 struct m66592_ep *ep;
1336 struct m66592_request *req;
1337 unsigned long flags;
1338 int request = 0;
1339
1340 ep = container_of(_ep, struct m66592_ep, ep);
1341 req = container_of(_req, struct m66592_request, req);
1342
1343 if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
1344 return -ESHUTDOWN;
1345
1346 spin_lock_irqsave(&ep->m66592->lock, flags);
1347
1348 if (list_empty(&ep->queue))
1349 request = 1;
1350
1351 list_add_tail(&req->queue, &ep->queue);
1352 req->req.actual = 0;
1353 req->req.status = -EINPROGRESS;
1354
1355 if (ep->desc == NULL) /* control */
1356 start_ep0(ep, req);
1357 else {
1358 if (request && !ep->busy)
1359 start_packet(ep, req);
1360 }
1361
1362 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1363
1364 return 0;
1365 }
1366
1367 static int m66592_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1368 {
1369 struct m66592_ep *ep;
1370 struct m66592_request *req;
1371 unsigned long flags;
1372
1373 ep = container_of(_ep, struct m66592_ep, ep);
1374 req = container_of(_req, struct m66592_request, req);
1375
1376 spin_lock_irqsave(&ep->m66592->lock, flags);
1377 if (!list_empty(&ep->queue))
1378 transfer_complete(ep, req, -ECONNRESET);
1379 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1380
1381 return 0;
1382 }
1383
1384 static int m66592_set_halt(struct usb_ep *_ep, int value)
1385 {
1386 struct m66592_ep *ep;
1387 struct m66592_request *req;
1388 unsigned long flags;
1389 int ret = 0;
1390
1391 ep = container_of(_ep, struct m66592_ep, ep);
1392 req = list_entry(ep->queue.next, struct m66592_request, queue);
1393
1394 spin_lock_irqsave(&ep->m66592->lock, flags);
1395 if (!list_empty(&ep->queue)) {
1396 ret = -EAGAIN;
1397 goto out;
1398 }
1399 if (value) {
1400 ep->busy = 1;
1401 pipe_stall(ep->m66592, ep->pipenum);
1402 } else {
1403 ep->busy = 0;
1404 pipe_stop(ep->m66592, ep->pipenum);
1405 }
1406
1407 out:
1408 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1409 return ret;
1410 }
1411
1412 static void m66592_fifo_flush(struct usb_ep *_ep)
1413 {
1414 struct m66592_ep *ep;
1415 unsigned long flags;
1416
1417 ep = container_of(_ep, struct m66592_ep, ep);
1418 spin_lock_irqsave(&ep->m66592->lock, flags);
1419 if (list_empty(&ep->queue) && !ep->busy) {
1420 pipe_stop(ep->m66592, ep->pipenum);
1421 m66592_bclr(ep->m66592, M66592_BCLR, ep->fifoctr);
1422 }
1423 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1424 }
1425
1426 static struct usb_ep_ops m66592_ep_ops = {
1427 .enable = m66592_enable,
1428 .disable = m66592_disable,
1429
1430 .alloc_request = m66592_alloc_request,
1431 .free_request = m66592_free_request,
1432
1433 .queue = m66592_queue,
1434 .dequeue = m66592_dequeue,
1435
1436 .set_halt = m66592_set_halt,
1437 .fifo_flush = m66592_fifo_flush,
1438 };
1439
1440 /*-------------------------------------------------------------------------*/
1441 static struct m66592 *the_controller;
1442
1443 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1444 {
1445 struct m66592 *m66592 = the_controller;
1446 int retval;
1447
1448 if (!driver
1449 || driver->speed != USB_SPEED_HIGH
1450 || !driver->bind
1451 || !driver->setup)
1452 return -EINVAL;
1453 if (!m66592)
1454 return -ENODEV;
1455 if (m66592->driver)
1456 return -EBUSY;
1457
1458 /* hook up the driver */
1459 driver->driver.bus = NULL;
1460 m66592->driver = driver;
1461 m66592->gadget.dev.driver = &driver->driver;
1462
1463 retval = device_add(&m66592->gadget.dev);
1464 if (retval) {
1465 pr_err("device_add error (%d)\n", retval);
1466 goto error;
1467 }
1468
1469 retval = driver->bind (&m66592->gadget);
1470 if (retval) {
1471 pr_err("bind to driver error (%d)\n", retval);
1472 device_del(&m66592->gadget.dev);
1473 goto error;
1474 }
1475
1476 m66592_bset(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
1477 if (m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS) {
1478 m66592_start_xclock(m66592);
1479 /* start vbus sampling */
1480 m66592->old_vbus = m66592_read(m66592,
1481 M66592_INTSTS0) & M66592_VBSTS;
1482 m66592->scount = M66592_MAX_SAMPLING;
1483 mod_timer(&m66592->timer, jiffies + msecs_to_jiffies(50));
1484 }
1485
1486 return 0;
1487
1488 error:
1489 m66592->driver = NULL;
1490 m66592->gadget.dev.driver = NULL;
1491
1492 return retval;
1493 }
1494 EXPORT_SYMBOL(usb_gadget_register_driver);
1495
1496 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1497 {
1498 struct m66592 *m66592 = the_controller;
1499 unsigned long flags;
1500
1501 if (driver != m66592->driver || !driver->unbind)
1502 return -EINVAL;
1503
1504 spin_lock_irqsave(&m66592->lock, flags);
1505 if (m66592->gadget.speed != USB_SPEED_UNKNOWN)
1506 m66592_usb_disconnect(m66592);
1507 spin_unlock_irqrestore(&m66592->lock, flags);
1508
1509 m66592_bclr(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
1510
1511 driver->unbind(&m66592->gadget);
1512 m66592->gadget.dev.driver = NULL;
1513
1514 init_controller(m66592);
1515 disable_controller(m66592);
1516
1517 device_del(&m66592->gadget.dev);
1518 m66592->driver = NULL;
1519 return 0;
1520 }
1521 EXPORT_SYMBOL(usb_gadget_unregister_driver);
1522
1523 /*-------------------------------------------------------------------------*/
1524 static int m66592_get_frame(struct usb_gadget *_gadget)
1525 {
1526 struct m66592 *m66592 = gadget_to_m66592(_gadget);
1527 return m66592_read(m66592, M66592_FRMNUM) & 0x03FF;
1528 }
1529
1530 static struct usb_gadget_ops m66592_gadget_ops = {
1531 .get_frame = m66592_get_frame,
1532 };
1533
1534 static int __exit m66592_remove(struct platform_device *pdev)
1535 {
1536 struct m66592 *m66592 = dev_get_drvdata(&pdev->dev);
1537
1538 del_timer_sync(&m66592->timer);
1539 iounmap(m66592->reg);
1540 free_irq(platform_get_irq(pdev, 0), m66592);
1541 m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
1542 usbf_stop_clock();
1543 kfree(m66592);
1544 return 0;
1545 }
1546
1547 static void nop_completion(struct usb_ep *ep, struct usb_request *r)
1548 {
1549 }
1550
1551 #define resource_len(r) (((r)->end - (r)->start) + 1)
1552
1553 static int __init m66592_probe(struct platform_device *pdev)
1554 {
1555 struct resource *res;
1556 int irq;
1557 void __iomem *reg = NULL;
1558 struct m66592 *m66592 = NULL;
1559 int ret = 0;
1560 int i;
1561
1562 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1563 (char *)udc_name);
1564 if (!res) {
1565 ret = -ENODEV;
1566 pr_err("platform_get_resource_byname error.\n");
1567 goto clean_up;
1568 }
1569
1570 irq = platform_get_irq(pdev, 0);
1571 if (irq < 0) {
1572 ret = -ENODEV;
1573 pr_err("platform_get_irq error.\n");
1574 goto clean_up;
1575 }
1576
1577 reg = ioremap(res->start, resource_len(res));
1578 if (reg == NULL) {
1579 ret = -ENOMEM;
1580 pr_err("ioremap error.\n");
1581 goto clean_up;
1582 }
1583
1584 /* initialize ucd */
1585 m66592 = kzalloc(sizeof(struct m66592), GFP_KERNEL);
1586 if (m66592 == NULL) {
1587 pr_err("kzalloc error\n");
1588 goto clean_up;
1589 }
1590
1591 spin_lock_init(&m66592->lock);
1592 dev_set_drvdata(&pdev->dev, m66592);
1593
1594 m66592->gadget.ops = &m66592_gadget_ops;
1595 device_initialize(&m66592->gadget.dev);
1596 strcpy(m66592->gadget.dev.bus_id, "gadget");
1597 m66592->gadget.is_dualspeed = 1;
1598 m66592->gadget.dev.parent = &pdev->dev;
1599 m66592->gadget.dev.dma_mask = pdev->dev.dma_mask;
1600 m66592->gadget.dev.release = pdev->dev.release;
1601 m66592->gadget.name = udc_name;
1602
1603 init_timer(&m66592->timer);
1604 m66592->timer.function = m66592_timer;
1605 m66592->timer.data = (unsigned long)m66592;
1606 m66592->reg = reg;
1607
1608 m66592->bi_bufnum = M66592_BASE_BUFNUM;
1609
1610 ret = request_irq(irq, m66592_irq, IRQF_DISABLED | IRQF_SHARED,
1611 udc_name, m66592);
1612 if (ret < 0) {
1613 pr_err("request_irq error (%d)\n", ret);
1614 goto clean_up;
1615 }
1616
1617 INIT_LIST_HEAD(&m66592->gadget.ep_list);
1618 m66592->gadget.ep0 = &m66592->ep[0].ep;
1619 INIT_LIST_HEAD(&m66592->gadget.ep0->ep_list);
1620 for (i = 0; i < M66592_MAX_NUM_PIPE; i++) {
1621 struct m66592_ep *ep = &m66592->ep[i];
1622
1623 if (i != 0) {
1624 INIT_LIST_HEAD(&m66592->ep[i].ep.ep_list);
1625 list_add_tail(&m66592->ep[i].ep.ep_list,
1626 &m66592->gadget.ep_list);
1627 }
1628 ep->m66592 = m66592;
1629 INIT_LIST_HEAD(&ep->queue);
1630 ep->ep.name = m66592_ep_name[i];
1631 ep->ep.ops = &m66592_ep_ops;
1632 ep->ep.maxpacket = 512;
1633 }
1634 m66592->ep[0].ep.maxpacket = 64;
1635 m66592->ep[0].pipenum = 0;
1636 m66592->ep[0].fifoaddr = M66592_CFIFO;
1637 m66592->ep[0].fifosel = M66592_CFIFOSEL;
1638 m66592->ep[0].fifoctr = M66592_CFIFOCTR;
1639 m66592->ep[0].fifotrn = 0;
1640 m66592->ep[0].pipectr = get_pipectr_addr(0);
1641 m66592->pipenum2ep[0] = &m66592->ep[0];
1642 m66592->epaddr2ep[0] = &m66592->ep[0];
1643
1644 the_controller = m66592;
1645
1646 m66592->ep0_req = m66592_alloc_request(&m66592->ep[0].ep, GFP_KERNEL);
1647 if (m66592->ep0_req == NULL)
1648 goto clean_up2;
1649 m66592->ep0_req->complete = nop_completion;
1650
1651 init_controller(m66592);
1652
1653 dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
1654 return 0;
1655
1656 clean_up2:
1657 free_irq(irq, m66592);
1658 clean_up:
1659 if (m66592) {
1660 if (m66592->ep0_req)
1661 m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
1662 kfree(m66592);
1663 }
1664 if (reg)
1665 iounmap(reg);
1666
1667 return ret;
1668 }
1669
1670 /*-------------------------------------------------------------------------*/
1671 static struct platform_driver m66592_driver = {
1672 .remove = __exit_p(m66592_remove),
1673 .driver = {
1674 .name = (char *) udc_name,
1675 .owner = THIS_MODULE,
1676 },
1677 };
1678
1679 static int __init m66592_udc_init(void)
1680 {
1681 return platform_driver_probe(&m66592_driver, m66592_probe);
1682 }
1683 module_init(m66592_udc_init);
1684
1685 static void __exit m66592_udc_cleanup(void)
1686 {
1687 platform_driver_unregister(&m66592_driver);
1688 }
1689 module_exit(m66592_udc_cleanup);
Linux for Ginger Game Console