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PRCM: 34XX: Fix wrong shift value used in dpll4_m4x2_ck enable bit
[linux-ginger.git] / drivers / usb / gadget / omap_udc.c
blob3528f49b670b48227715f0c1c3a443b95b788c4b
1 /*
2 * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
3 *
4 * Copyright (C) 2004 Texas Instruments, Inc.
5 * Copyright (C) 2004-2005 David Brownell
6 *
7 * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24 #undef DEBUG
25 #undef VERBOSE
26
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/ioport.h>
30 #include <linux/types.h>
31 #include <linux/errno.h>
32 #include <linux/delay.h>
33 #include <linux/slab.h>
34 #include <linux/init.h>
35 #include <linux/timer.h>
36 #include <linux/list.h>
37 #include <linux/interrupt.h>
38 #include <linux/proc_fs.h>
39 #include <linux/mm.h>
40 #include <linux/moduleparam.h>
41 #include <linux/platform_device.h>
42 #include <linux/usb/ch9.h>
43 #include <linux/usb/gadget.h>
44 #include <linux/usb/otg.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/clk.h>
47
48 #include <asm/byteorder.h>
49 #include <asm/io.h>
50 #include <asm/irq.h>
51 #include <asm/system.h>
52 #include <asm/unaligned.h>
53 #include <asm/mach-types.h>
54
55 #include <asm/arch/dma.h>
56 #include <asm/arch/usb.h>
57 #include <asm/arch/control.h>
58
59 #include "omap_udc.h"
60
61 #undef USB_TRACE
62
63 /* bulk DMA seems to be behaving for both IN and OUT */
64 #define USE_DMA
65
66 /* ISO too */
67 #define USE_ISO
68
69 #define DRIVER_DESC "OMAP UDC driver"
70 #define DRIVER_VERSION "4 October 2004"
71
72 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
73
74 #define OMAP2_DMA_CH(ch) (((ch) - 1) << 1)
75 #define OMAP24XX_DMA(name, ch) (OMAP24XX_DMA_##name + OMAP2_DMA_CH(ch))
76
77 /*
78 * The OMAP UDC needs _very_ early endpoint setup: before enabling the
79 * D+ pullup to allow enumeration. That's too early for the gadget
80 * framework to use from usb_endpoint_enable(), which happens after
81 * enumeration as part of activating an interface. (But if we add an
82 * optional new "UDC not yet running" state to the gadget driver model,
83 * even just during driver binding, the endpoint autoconfig logic is the
84 * natural spot to manufacture new endpoints.)
85 *
86 * So instead of using endpoint enable calls to control the hardware setup,
87 * this driver defines a "fifo mode" parameter. It's used during driver
88 * initialization to choose among a set of pre-defined endpoint configs.
89 * See omap_udc_setup() for available modes, or to add others. That code
90 * lives in an init section, so use this driver as a module if you need
91 * to change the fifo mode after the kernel boots.
92 *
93 * Gadget drivers normally ignore endpoints they don't care about, and
94 * won't include them in configuration descriptors. That means only
95 * misbehaving hosts would even notice they exist.
96 */
97 #ifdef USE_ISO
98 static unsigned fifo_mode = 3;
99 #else
100 static unsigned fifo_mode = 0;
101 #endif
102
103 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
104 * boot parameter "omap_udc:fifo_mode=42"
105 */
106 module_param (fifo_mode, uint, 0);
107 MODULE_PARM_DESC (fifo_mode, "endpoint configuration");
108
109 #ifdef USE_DMA
110 static unsigned use_dma = 1;
111
112 /* "modprobe omap_udc use_dma=y", or else as a kernel
113 * boot parameter "omap_udc:use_dma=y"
114 */
115 module_param (use_dma, bool, 0);
116 MODULE_PARM_DESC (use_dma, "enable/disable DMA");
117 #else /* !USE_DMA */
118
119 /* save a bit of code */
120 #define use_dma 0
121 #endif /* !USE_DMA */
122
123
124 static const char driver_name [] = "omap_udc";
125 static const char driver_desc [] = DRIVER_DESC;
126
127 /*-------------------------------------------------------------------------*/
128
129 /* there's a notion of "current endpoint" for modifying endpoint
130 * state, and PIO access to its FIFO.
131 */
132
133 static void use_ep(struct omap_ep *ep, u16 select)
134 {
135 u16 num = ep->bEndpointAddress & 0x0f;
136
137 if (ep->bEndpointAddress & USB_DIR_IN)
138 num |= UDC_EP_DIR;
139 omap_writew(num | select, UDC_EP_NUM);
140 /* when select, MUST deselect later !! */
141 }
142
143 static inline void deselect_ep(void)
144 {
145 u16 w;
146
147 w = omap_readw(UDC_EP_NUM);
148 w &= ~UDC_EP_SEL;
149 omap_writew(w, UDC_EP_NUM);
150 /* 6 wait states before TX will happen */
151 }
152
153 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
154
155 /*-------------------------------------------------------------------------*/
156
157 static int omap_ep_enable(struct usb_ep *_ep,
158 const struct usb_endpoint_descriptor *desc)
159 {
160 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
161 struct omap_udc *udc;
162 unsigned long flags;
163 u16 maxp;
164
165 /* catch various bogus parameters */
166 if (!_ep || !desc || ep->desc
167 || desc->bDescriptorType != USB_DT_ENDPOINT
168 || ep->bEndpointAddress != desc->bEndpointAddress
169 || ep->maxpacket < le16_to_cpu
170 (desc->wMaxPacketSize)) {
171 DBG("%s, bad ep or descriptor\n", __func__);
172 return -EINVAL;
173 }
174 maxp = le16_to_cpu (desc->wMaxPacketSize);
175 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
176 && maxp != ep->maxpacket)
177 || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket
178 || !desc->wMaxPacketSize) {
179 DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
180 return -ERANGE;
181 }
182
183 #ifdef USE_ISO
184 if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
185 && desc->bInterval != 1)) {
186 /* hardware wants period = 1; USB allows 2^(Interval-1) */
187 DBG("%s, unsupported ISO period %dms\n", _ep->name,
188 1 << (desc->bInterval - 1));
189 return -EDOM;
190 }
191 #else
192 if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
193 DBG("%s, ISO nyet\n", _ep->name);
194 return -EDOM;
195 }
196 #endif
197
198 /* xfer types must match, except that interrupt ~= bulk */
199 if (ep->bmAttributes != desc->bmAttributes
200 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
201 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
202 DBG("%s, %s type mismatch\n", __func__, _ep->name);
203 return -EINVAL;
204 }
205
206 udc = ep->udc;
207 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
208 DBG("%s, bogus device state\n", __func__);
209 return -ESHUTDOWN;
210 }
211
212 spin_lock_irqsave(&udc->lock, flags);
213
214 ep->desc = desc;
215 ep->irqs = 0;
216 ep->stopped = 0;
217 ep->ep.maxpacket = maxp;
218
219 /* set endpoint to initial state */
220 ep->dma_channel = 0;
221 ep->has_dma = 0;
222 ep->lch = -1;
223 use_ep(ep, UDC_EP_SEL);
224 omap_writew(udc->clr_halt, UDC_CTRL);
225 ep->ackwait = 0;
226 deselect_ep();
227
228 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
229 list_add(&ep->iso, &udc->iso);
230
231 /* maybe assign a DMA channel to this endpoint */
232 if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
233 /* FIXME ISO can dma, but prefers first channel */
234 dma_channel_claim(ep, 0);
235
236 /* PIO OUT may RX packets */
237 if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
238 && !ep->has_dma
239 && !(ep->bEndpointAddress & USB_DIR_IN)) {
240 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
241 ep->ackwait = 1 + ep->double_buf;
242 }
243
244 spin_unlock_irqrestore(&udc->lock, flags);
245 VDBG("%s enabled\n", _ep->name);
246 return 0;
247 }
248
249 static void nuke(struct omap_ep *, int status);
250
251 static int omap_ep_disable(struct usb_ep *_ep)
252 {
253 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
254 unsigned long flags;
255
256 if (!_ep || !ep->desc) {
257 DBG("%s, %s not enabled\n", __func__,
258 _ep ? ep->ep.name : NULL);
259 return -EINVAL;
260 }
261
262 spin_lock_irqsave(&ep->udc->lock, flags);
263 ep->desc = NULL;
264 nuke (ep, -ESHUTDOWN);
265 ep->ep.maxpacket = ep->maxpacket;
266 ep->has_dma = 0;
267 omap_writew(UDC_SET_HALT, UDC_CTRL);
268 list_del_init(&ep->iso);
269 del_timer(&ep->timer);
270
271 spin_unlock_irqrestore(&ep->udc->lock, flags);
272
273 VDBG("%s disabled\n", _ep->name);
274 return 0;
275 }
276
277 /*-------------------------------------------------------------------------*/
278
279 static struct usb_request *
280 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
281 {
282 struct omap_req *req;
283
284 req = kzalloc(sizeof(*req), gfp_flags);
285 if (req) {
286 req->req.dma = DMA_ADDR_INVALID;
287 INIT_LIST_HEAD (&req->queue);
288 }
289 return &req->req;
290 }
291
292 static void
293 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
294 {
295 struct omap_req *req = container_of(_req, struct omap_req, req);
296
297 if (_req)
298 kfree (req);
299 }
300
301 /*-------------------------------------------------------------------------*/
302
303 static void
304 done(struct omap_ep *ep, struct omap_req *req, int status)
305 {
306 unsigned stopped = ep->stopped;
307
308 list_del_init(&req->queue);
309
310 if (req->req.status == -EINPROGRESS)
311 req->req.status = status;
312 else
313 status = req->req.status;
314
315 if (use_dma && ep->has_dma) {
316 if (req->mapped) {
317 dma_unmap_single(ep->udc->gadget.dev.parent,
318 req->req.dma, req->req.length,
319 (ep->bEndpointAddress & USB_DIR_IN)
320 ? DMA_TO_DEVICE
321 : DMA_FROM_DEVICE);
322 req->req.dma = DMA_ADDR_INVALID;
323 req->mapped = 0;
324 } else
325 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
326 req->req.dma, req->req.length,
327 (ep->bEndpointAddress & USB_DIR_IN)
328 ? DMA_TO_DEVICE
329 : DMA_FROM_DEVICE);
330 }
331
332 #ifndef USB_TRACE
333 if (status && status != -ESHUTDOWN)
334 #endif
335 VDBG("complete %s req %p stat %d len %u/%u\n",
336 ep->ep.name, &req->req, status,
337 req->req.actual, req->req.length);
338
339 /* don't modify queue heads during completion callback */
340 ep->stopped = 1;
341 spin_unlock(&ep->udc->lock);
342 req->req.complete(&ep->ep, &req->req);
343 spin_lock(&ep->udc->lock);
344 ep->stopped = stopped;
345 }
346
347 /*-------------------------------------------------------------------------*/
348
349 #define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
350 #define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL)
351
352 #define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
353 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
354
355 static inline int
356 write_packet(u8 *buf, struct omap_req *req, unsigned max)
357 {
358 unsigned len;
359 u16 *wp;
360
361 len = min(req->req.length - req->req.actual, max);
362 req->req.actual += len;
363
364 max = len;
365 if (likely((((int)buf) & 1) == 0)) {
366 wp = (u16 *)buf;
367 while (max >= 2) {
368 omap_writew(*wp++, UDC_DATA);
369 max -= 2;
370 }
371 buf = (u8 *)wp;
372 }
373 while (max--)
374 omap_writeb(*buf++, UDC_DATA);
375 return len;
376 }
377
378 // FIXME change r/w fifo calling convention
379
380
381 // return: 0 = still running, 1 = completed, negative = errno
382 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
383 {
384 u8 *buf;
385 unsigned count;
386 int is_last;
387 u16 ep_stat;
388
389 buf = req->req.buf + req->req.actual;
390 prefetch(buf);
391
392 /* PIO-IN isn't double buffered except for iso */
393 ep_stat = omap_readw(UDC_STAT_FLG);
394 if (ep_stat & UDC_FIFO_UNWRITABLE)
395 return 0;
396
397 count = ep->ep.maxpacket;
398 count = write_packet(buf, req, count);
399 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
400 ep->ackwait = 1;
401
402 /* last packet is often short (sometimes a zlp) */
403 if (count != ep->ep.maxpacket)
404 is_last = 1;
405 else if (req->req.length == req->req.actual
406 && !req->req.zero)
407 is_last = 1;
408 else
409 is_last = 0;
410
411 /* NOTE: requests complete when all IN data is in a
412 * FIFO (or sometimes later, if a zlp was needed).
413 * Use usb_ep_fifo_status() where needed.
414 */
415 if (is_last)
416 done(ep, req, 0);
417 return is_last;
418 }
419
420 static inline int
421 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
422 {
423 unsigned len;
424 u16 *wp;
425
426 len = min(req->req.length - req->req.actual, avail);
427 req->req.actual += len;
428 avail = len;
429
430 if (likely((((int)buf) & 1) == 0)) {
431 wp = (u16 *)buf;
432 while (avail >= 2) {
433 *wp++ = omap_readw(UDC_DATA);
434 avail -= 2;
435 }
436 buf = (u8 *)wp;
437 }
438 while (avail--)
439 *buf++ = omap_readb(UDC_DATA);
440 return len;
441 }
442
443 // return: 0 = still running, 1 = queue empty, negative = errno
444 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
445 {
446 u8 *buf;
447 unsigned count, avail;
448 int is_last;
449
450 buf = req->req.buf + req->req.actual;
451 prefetchw(buf);
452
453 for (;;) {
454 u16 ep_stat = omap_readw(UDC_STAT_FLG);
455
456 is_last = 0;
457 if (ep_stat & FIFO_EMPTY) {
458 if (!ep->double_buf)
459 break;
460 ep->fnf = 1;
461 }
462 if (ep_stat & UDC_EP_HALTED)
463 break;
464
465 if (ep_stat & UDC_FIFO_FULL)
466 avail = ep->ep.maxpacket;
467 else {
468 avail = omap_readw(UDC_RXFSTAT);
469 ep->fnf = ep->double_buf;
470 }
471 count = read_packet(buf, req, avail);
472
473 /* partial packet reads may not be errors */
474 if (count < ep->ep.maxpacket) {
475 is_last = 1;
476 /* overflowed this request? flush extra data */
477 if (count != avail) {
478 req->req.status = -EOVERFLOW;
479 avail -= count;
480 while (avail--)
481 omap_readw(UDC_DATA);
482 }
483 } else if (req->req.length == req->req.actual)
484 is_last = 1;
485 else
486 is_last = 0;
487
488 if (!ep->bEndpointAddress)
489 break;
490 if (is_last)
491 done(ep, req, 0);
492 break;
493 }
494 return is_last;
495 }
496
497 /*-------------------------------------------------------------------------*/
498
499 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
500 {
501 dma_addr_t end;
502
503 /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
504 * the last transfer's bytecount by more than a FIFO's worth.
505 */
506 if (cpu_is_omap15xx())
507 return 0;
508
509 end = omap_get_dma_src_pos(ep->lch);
510 if (end == ep->dma_counter)
511 return 0;
512
513 end |= start & (0xffff << 16);
514 if (end < start)
515 end += 0x10000;
516 return end - start;
517 }
518
519 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
520 {
521 dma_addr_t end;
522
523 end = omap_get_dma_dst_pos(ep->lch);
524 if (end == ep->dma_counter)
525 return 0;
526
527 end |= start & (0xffff << 16);
528 if (cpu_is_omap15xx())
529 end++;
530 if (end < start)
531 end += 0x10000;
532 return end - start;
533 }
534
535
536 /* Each USB transfer request using DMA maps to one or more DMA transfers.
537 * When DMA completion isn't request completion, the UDC continues with
538 * the next DMA transfer for that USB transfer.
539 */
540
541 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
542 {
543 u16 txdma_ctrl, w;
544 unsigned length = req->req.length - req->req.actual;
545 const int sync_mode = cpu_is_omap15xx()
546 ? OMAP_DMA_SYNC_FRAME
547 : OMAP_DMA_SYNC_ELEMENT;
548 int dma_trigger = 0;
549
550 if (cpu_is_omap24xx())
551 dma_trigger = OMAP24XX_DMA(USB_W2FC_TX0, ep->dma_channel);
552
553 /* measure length in either bytes or packets */
554 if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
555 || (cpu_is_omap24xx() && length < ep->maxpacket)
556 || (cpu_is_omap15xx() && length < ep->maxpacket)) {
557 txdma_ctrl = UDC_TXN_EOT | length;
558 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
559 length, 1, sync_mode, dma_trigger, 0);
560 } else {
561 length = min(length / ep->maxpacket,
562 (unsigned) UDC_TXN_TSC + 1);
563 txdma_ctrl = length;
564 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
565 ep->ep.maxpacket >> 1, length, sync_mode,
566 dma_trigger, 0);
567 length *= ep->maxpacket;
568 }
569 omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
570 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
571 0, 0);
572
573 omap_start_dma(ep->lch);
574 ep->dma_counter = omap_get_dma_src_pos(ep->lch);
575 w = omap_readw(UDC_DMA_IRQ_EN);
576 w |= UDC_TX_DONE_IE(ep->dma_channel);
577 omap_writew(w, UDC_DMA_IRQ_EN);
578 omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
579 req->dma_bytes = length;
580 }
581
582 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
583 {
584 u16 w;
585
586 if (status == 0) {
587 req->req.actual += req->dma_bytes;
588
589 /* return if this request needs to send data or zlp */
590 if (req->req.actual < req->req.length)
591 return;
592 if (req->req.zero
593 && req->dma_bytes != 0
594 && (req->req.actual % ep->maxpacket) == 0)
595 return;
596 } else
597 req->req.actual += dma_src_len(ep, req->req.dma
598 + req->req.actual);
599
600 /* tx completion */
601 omap_stop_dma(ep->lch);
602 w = omap_readw(UDC_DMA_IRQ_EN);
603 w &= ~UDC_TX_DONE_IE(ep->dma_channel);
604 omap_writew(w, UDC_DMA_IRQ_EN);
605 done(ep, req, status);
606 }
607
608 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
609 {
610 unsigned packets = req->req.length - req->req.actual;
611 int dma_trigger = 0;
612 u16 w;
613
614 if (cpu_is_omap24xx())
615 dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel);
616
617 /* NOTE: we filtered out "short reads" before, so we know
618 * the buffer has only whole numbers of packets.
619 * except MODE SELECT(6) sent the 24 bytes data in OMAP24XX DMA mode
620 */
621 if (cpu_is_omap24xx() && packets < ep->maxpacket) {
622 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
623 packets, 1, OMAP_DMA_SYNC_ELEMENT,
624 dma_trigger, 0);
625 req->dma_bytes = packets;
626 } else {
627 /* set up this DMA transfer, enable the fifo, start */
628 packets /= ep->ep.maxpacket;
629 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
630 req->dma_bytes = packets * ep->ep.maxpacket;
631 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
632 ep->ep.maxpacket >> 1, packets,
633 OMAP_DMA_SYNC_ELEMENT,
634 dma_trigger, 0);
635 }
636 omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
637 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
638 0, 0);
639 ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
640
641 omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
642 w = omap_readw(UDC_DMA_IRQ_EN);
643 w |= UDC_RX_EOT_IE(ep->dma_channel);
644 omap_writew(w, UDC_DMA_IRQ_EN);
645 omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
646 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
647
648 omap_start_dma(ep->lch);
649 }
650
651 static void
652 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
653 {
654 u16 count, w;
655
656 if (status == 0)
657 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
658 count = dma_dest_len(ep, req->req.dma + req->req.actual);
659 count += req->req.actual;
660 if (one)
661 count--;
662 if (count <= req->req.length)
663 req->req.actual = count;
664
665 if (count != req->dma_bytes || status)
666 omap_stop_dma(ep->lch);
667
668 /* if this wasn't short, request may need another transfer */
669 else if (req->req.actual < req->req.length)
670 return;
671
672 /* rx completion */
673 w = omap_readw(UDC_DMA_IRQ_EN);
674 w &= ~UDC_RX_EOT_IE(ep->dma_channel);
675 omap_writew(w, UDC_DMA_IRQ_EN);
676 done(ep, req, status);
677 }
678
679 static void dma_irq(struct omap_udc *udc, u16 irq_src)
680 {
681 u16 dman_stat = omap_readw(UDC_DMAN_STAT);
682 struct omap_ep *ep;
683 struct omap_req *req;
684
685 /* IN dma: tx to host */
686 if (irq_src & UDC_TXN_DONE) {
687 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
688 ep->irqs++;
689 /* can see TXN_DONE after dma abort */
690 if (!list_empty(&ep->queue)) {
691 req = container_of(ep->queue.next,
692 struct omap_req, queue);
693 finish_in_dma(ep, req, 0);
694 }
695 omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
696
697 if (!list_empty (&ep->queue)) {
698 req = container_of(ep->queue.next,
699 struct omap_req, queue);
700 next_in_dma(ep, req);
701 }
702 }
703
704 /* OUT dma: rx from host */
705 if (irq_src & UDC_RXN_EOT) {
706 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
707 ep->irqs++;
708 /* can see RXN_EOT after dma abort */
709 if (!list_empty(&ep->queue)) {
710 req = container_of(ep->queue.next,
711 struct omap_req, queue);
712 finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
713 }
714 omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
715
716 if (!list_empty (&ep->queue)) {
717 req = container_of(ep->queue.next,
718 struct omap_req, queue);
719 next_out_dma(ep, req);
720 }
721 }
722
723 if (irq_src & UDC_RXN_CNT) {
724 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
725 ep->irqs++;
726 /* omap15xx does this unasked... */
727 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
728 omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
729 }
730 }
731
732 static void dma_error(int lch, u16 ch_status, void *data)
733 {
734 struct omap_ep *ep = data;
735
736 /* if ch_status & OMAP_DMA_DROP_IRQ ... */
737 /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
738 ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
739
740 /* complete current transfer ... */
741 }
742
743 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
744 {
745 u16 reg;
746 int status, restart, is_in;
747 int dma_channel;
748
749 is_in = ep->bEndpointAddress & USB_DIR_IN;
750 if (is_in)
751 reg = omap_readw(UDC_TXDMA_CFG);
752 else
753 reg = omap_readw(UDC_RXDMA_CFG);
754 reg |= UDC_DMA_REQ; /* "pulse" activated */
755
756 ep->dma_channel = 0;
757 ep->lch = -1;
758 if (channel == 0 || channel > 3) {
759 if ((reg & 0x0f00) == 0)
760 channel = 3;
761 else if ((reg & 0x00f0) == 0)
762 channel = 2;
763 else if ((reg & 0x000f) == 0) /* preferred for ISO */
764 channel = 1;
765 else {
766 status = -EMLINK;
767 goto just_restart;
768 }
769 }
770 reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
771 ep->dma_channel = channel;
772
773 if (is_in) {
774 if (cpu_is_omap24xx())
775 dma_channel = OMAP24XX_DMA(USB_W2FC_TX0, channel);
776 else
777 dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
778 status = omap_request_dma(dma_channel,
779 ep->ep.name, dma_error, ep, &ep->lch);
780 if (status == 0) {
781 omap_writew(reg, UDC_TXDMA_CFG);
782 /* EMIFF or SDRC */
783 omap_set_dma_src_burst_mode(ep->lch,
784 OMAP_DMA_DATA_BURST_4);
785 omap_set_dma_src_data_pack(ep->lch, 1);
786 /* TIPB */
787 omap_set_dma_dest_params(ep->lch,
788 OMAP_DMA_PORT_TIPB,
789 OMAP_DMA_AMODE_CONSTANT,
790 (unsigned long) io_v2p(UDC_DATA_DMA),
791 0, 0);
792 }
793 } else {
794 if (cpu_is_omap24xx())
795 dma_channel = OMAP24XX_DMA(USB_W2FC_RX0, channel);
796 else
797 dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
798
799 status = omap_request_dma(dma_channel,
800 ep->ep.name, dma_error, ep, &ep->lch);
801 if (status == 0) {
802 omap_writew(reg, UDC_RXDMA_CFG);
803 /* TIPB */
804 omap_set_dma_src_params(ep->lch,
805 OMAP_DMA_PORT_TIPB,
806 OMAP_DMA_AMODE_CONSTANT,
807 (unsigned long) io_v2p(UDC_DATA_DMA),
808 0, 0);
809 /* EMIFF or SDRC */
810 omap_set_dma_dest_burst_mode(ep->lch,
811 OMAP_DMA_DATA_BURST_4);
812 omap_set_dma_dest_data_pack(ep->lch, 1);
813 }
814 }
815 if (status)
816 ep->dma_channel = 0;
817 else {
818 ep->has_dma = 1;
819 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
820
821 /* channel type P: hw synch (fifo) */
822 if (cpu_class_is_omap1() && !cpu_is_omap15xx())
823 omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
824 }
825
826 just_restart:
827 /* restart any queue, even if the claim failed */
828 restart = !ep->stopped && !list_empty(&ep->queue);
829
830 if (status)
831 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
832 restart ? " (restart)" : "");
833 else
834 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
835 is_in ? 't' : 'r',
836 ep->dma_channel - 1, ep->lch,
837 restart ? " (restart)" : "");
838
839 if (restart) {
840 struct omap_req *req;
841 req = container_of(ep->queue.next, struct omap_req, queue);
842 if (ep->has_dma)
843 (is_in ? next_in_dma : next_out_dma)(ep, req);
844 else {
845 use_ep(ep, UDC_EP_SEL);
846 (is_in ? write_fifo : read_fifo)(ep, req);
847 deselect_ep();
848 if (!is_in) {
849 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
850 ep->ackwait = 1 + ep->double_buf;
851 }
852 /* IN: 6 wait states before it'll tx */
853 }
854 }
855 }
856
857 static void dma_channel_release(struct omap_ep *ep)
858 {
859 int shift = 4 * (ep->dma_channel - 1);
860 u16 mask = 0x0f << shift;
861 struct omap_req *req;
862 int active;
863
864 /* abort any active usb transfer request */
865 if (!list_empty(&ep->queue))
866 req = container_of(ep->queue.next, struct omap_req, queue);
867 else
868 req = NULL;
869
870 active = omap_get_dma_active_status(ep->lch);
871
872 DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
873 active ? "active" : "idle",
874 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
875 ep->dma_channel - 1, req);
876
877 /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
878 * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
879 */
880
881 /* wait till current packet DMA finishes, and fifo empties */
882 if (ep->bEndpointAddress & USB_DIR_IN) {
883 omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
884 UDC_TXDMA_CFG);
885
886 if (req) {
887 finish_in_dma(ep, req, -ECONNRESET);
888
889 /* clear FIFO; hosts probably won't empty it */
890 use_ep(ep, UDC_EP_SEL);
891 omap_writew(UDC_CLR_EP, UDC_CTRL);
892 deselect_ep();
893 }
894 while (omap_readw(UDC_TXDMA_CFG) & mask)
895 udelay(10);
896 } else {
897 omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
898 UDC_RXDMA_CFG);
899
900 /* dma empties the fifo */
901 while (omap_readw(UDC_RXDMA_CFG) & mask)
902 udelay(10);
903 if (req)
904 finish_out_dma(ep, req, -ECONNRESET, 0);
905 }
906 omap_free_dma(ep->lch);
907 ep->dma_channel = 0;
908 ep->lch = -1;
909 /* has_dma still set, till endpoint is fully quiesced */
910 }
911
912
913 /*-------------------------------------------------------------------------*/
914
915 static int
916 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
917 {
918 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
919 struct omap_req *req = container_of(_req, struct omap_req, req);
920 struct omap_udc *udc;
921 unsigned long flags;
922 int is_iso = 0;
923
924 /* catch various bogus parameters */
925 if (!_req || !req->req.complete || !req->req.buf
926 || !list_empty(&req->queue)) {
927 DBG("%s, bad params\n", __func__);
928 return -EINVAL;
929 }
930 if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
931 DBG("%s, bad ep\n", __func__);
932 return -EINVAL;
933 }
934 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
935 if (req->req.length > ep->ep.maxpacket)
936 return -EMSGSIZE;
937 is_iso = 1;
938 }
939
940 /* this isn't bogus, but OMAP DMA isn't the only hardware to
941 * have a hard time with partial packet reads... reject it.
942 * Except OMAP2 can handle the small packets.
943 */
944 if (use_dma
945 && ep->has_dma
946 && ep->bEndpointAddress != 0
947 && (ep->bEndpointAddress & USB_DIR_IN) == 0
948 && !cpu_class_is_omap2()
949 && (req->req.length % ep->ep.maxpacket) != 0) {
950 DBG("%s, no partial packet OUT reads\n", __func__);
951 return -EMSGSIZE;
952 }
953
954 udc = ep->udc;
955 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
956 return -ESHUTDOWN;
957
958 if (use_dma && ep->has_dma) {
959 if (req->req.dma == DMA_ADDR_INVALID) {
960 req->req.dma = dma_map_single(
961 ep->udc->gadget.dev.parent,
962 req->req.buf,
963 req->req.length,
964 (ep->bEndpointAddress & USB_DIR_IN)
965 ? DMA_TO_DEVICE
966 : DMA_FROM_DEVICE);
967 req->mapped = 1;
968 } else {
969 dma_sync_single_for_device(
970 ep->udc->gadget.dev.parent,
971 req->req.dma, req->req.length,
972 (ep->bEndpointAddress & USB_DIR_IN)
973 ? DMA_TO_DEVICE
974 : DMA_FROM_DEVICE);
975 req->mapped = 0;
976 }
977 }
978
979 VDBG("%s queue req %p, len %d buf %p\n",
980 ep->ep.name, _req, _req->length, _req->buf);
981
982 spin_lock_irqsave(&udc->lock, flags);
983
984 req->req.status = -EINPROGRESS;
985 req->req.actual = 0;
986
987 /* maybe kickstart non-iso i/o queues */
988 if (is_iso) {
989 u16 w;
990
991 w = omap_readw(UDC_IRQ_EN);
992 w |= UDC_SOF_IE;
993 omap_writew(w, UDC_IRQ_EN);
994 } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
995 int is_in;
996
997 if (ep->bEndpointAddress == 0) {
998 if (!udc->ep0_pending || !list_empty (&ep->queue)) {
999 spin_unlock_irqrestore(&udc->lock, flags);
1000 return -EL2HLT;
1001 }
1002
1003 /* empty DATA stage? */
1004 is_in = udc->ep0_in;
1005 if (!req->req.length) {
1006
1007 /* chip became CONFIGURED or ADDRESSED
1008 * earlier; drivers may already have queued
1009 * requests to non-control endpoints
1010 */
1011 if (udc->ep0_set_config) {
1012 u16 irq_en = omap_readw(UDC_IRQ_EN);
1013
1014 irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
1015 if (!udc->ep0_reset_config)
1016 irq_en |= UDC_EPN_RX_IE
1017 | UDC_EPN_TX_IE;
1018 omap_writew(irq_en, UDC_IRQ_EN);
1019 }
1020
1021 /* STATUS for zero length DATA stages is
1022 * always an IN ... even for IN transfers,
1023 * a weird case which seem to stall OMAP.
1024 */
1025 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
1026 omap_writew(UDC_CLR_EP, UDC_CTRL);
1027 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1028 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1029
1030 /* cleanup */
1031 udc->ep0_pending = 0;
1032 done(ep, req, 0);
1033 req = NULL;
1034
1035 /* non-empty DATA stage */
1036 } else if (is_in) {
1037 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
1038 } else {
1039 if (udc->ep0_setup)
1040 goto irq_wait;
1041 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1042 }
1043 } else {
1044 is_in = ep->bEndpointAddress & USB_DIR_IN;
1045 if (!ep->has_dma)
1046 use_ep(ep, UDC_EP_SEL);
1047 /* if ISO: SOF IRQs must be enabled/disabled! */
1048 }
1049
1050 if (ep->has_dma)
1051 (is_in ? next_in_dma : next_out_dma)(ep, req);
1052 else if (req) {
1053 if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1054 req = NULL;
1055 deselect_ep();
1056 if (!is_in) {
1057 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1058 ep->ackwait = 1 + ep->double_buf;
1059 }
1060 /* IN: 6 wait states before it'll tx */
1061 }
1062 }
1063
1064 irq_wait:
1065 /* irq handler advances the queue */
1066 if (req != NULL)
1067 list_add_tail(&req->queue, &ep->queue);
1068 spin_unlock_irqrestore(&udc->lock, flags);
1069
1070 return 0;
1071 }
1072
1073 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1074 {
1075 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1076 struct omap_req *req;
1077 unsigned long flags;
1078
1079 if (!_ep || !_req)
1080 return -EINVAL;
1081
1082 spin_lock_irqsave(&ep->udc->lock, flags);
1083
1084 /* make sure it's actually queued on this endpoint */
1085 list_for_each_entry (req, &ep->queue, queue) {
1086 if (&req->req == _req)
1087 break;
1088 }
1089 if (&req->req != _req) {
1090 spin_unlock_irqrestore(&ep->udc->lock, flags);
1091 return -EINVAL;
1092 }
1093
1094 if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1095 int channel = ep->dma_channel;
1096
1097 /* releasing the channel cancels the request,
1098 * reclaiming the channel restarts the queue
1099 */
1100 dma_channel_release(ep);
1101 dma_channel_claim(ep, channel);
1102 } else
1103 done(ep, req, -ECONNRESET);
1104 spin_unlock_irqrestore(&ep->udc->lock, flags);
1105 return 0;
1106 }
1107
1108 /*-------------------------------------------------------------------------*/
1109
1110 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1111 {
1112 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1113 unsigned long flags;
1114 int status = -EOPNOTSUPP;
1115
1116 spin_lock_irqsave(&ep->udc->lock, flags);
1117
1118 /* just use protocol stalls for ep0; real halts are annoying */
1119 if (ep->bEndpointAddress == 0) {
1120 if (!ep->udc->ep0_pending)
1121 status = -EINVAL;
1122 else if (value) {
1123 if (ep->udc->ep0_set_config) {
1124 WARN("error changing config?\n");
1125 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1126 }
1127 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1128 ep->udc->ep0_pending = 0;
1129 status = 0;
1130 } else /* NOP */
1131 status = 0;
1132
1133 /* otherwise, all active non-ISO endpoints can halt */
1134 } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1135
1136 /* IN endpoints must already be idle */
1137 if ((ep->bEndpointAddress & USB_DIR_IN)
1138 && !list_empty(&ep->queue)) {
1139 status = -EAGAIN;
1140 goto done;
1141 }
1142
1143 if (value) {
1144 int channel;
1145
1146 if (use_dma && ep->dma_channel
1147 && !list_empty(&ep->queue)) {
1148 channel = ep->dma_channel;
1149 dma_channel_release(ep);
1150 } else
1151 channel = 0;
1152
1153 use_ep(ep, UDC_EP_SEL);
1154 if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
1155 omap_writew(UDC_SET_HALT, UDC_CTRL);
1156 status = 0;
1157 } else
1158 status = -EAGAIN;
1159 deselect_ep();
1160
1161 if (channel)
1162 dma_channel_claim(ep, channel);
1163 } else {
1164 use_ep(ep, 0);
1165 omap_writew(ep->udc->clr_halt, UDC_CTRL);
1166 ep->ackwait = 0;
1167 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1168 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1169 ep->ackwait = 1 + ep->double_buf;
1170 }
1171 }
1172 }
1173 done:
1174 VDBG("%s %s halt stat %d\n", ep->ep.name,
1175 value ? "set" : "clear", status);
1176
1177 spin_unlock_irqrestore(&ep->udc->lock, flags);
1178 return status;
1179 }
1180
1181 static struct usb_ep_ops omap_ep_ops = {
1182 .enable = omap_ep_enable,
1183 .disable = omap_ep_disable,
1184
1185 .alloc_request = omap_alloc_request,
1186 .free_request = omap_free_request,
1187
1188 .queue = omap_ep_queue,
1189 .dequeue = omap_ep_dequeue,
1190
1191 .set_halt = omap_ep_set_halt,
1192 // fifo_status ... report bytes in fifo
1193 // fifo_flush ... flush fifo
1194 };
1195
1196 /*-------------------------------------------------------------------------*/
1197
1198 static int omap_get_frame(struct usb_gadget *gadget)
1199 {
1200 u16 sof = omap_readw(UDC_SOF);
1201 return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1202 }
1203
1204 static int omap_wakeup(struct usb_gadget *gadget)
1205 {
1206 struct omap_udc *udc;
1207 unsigned long flags;
1208 int retval = -EHOSTUNREACH;
1209
1210 udc = container_of(gadget, struct omap_udc, gadget);
1211
1212 spin_lock_irqsave(&udc->lock, flags);
1213 if (udc->devstat & UDC_SUS) {
1214 /* NOTE: OTG spec erratum says that OTG devices may
1215 * issue wakeups without host enable.
1216 */
1217 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1218 DBG("remote wakeup...\n");
1219 omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
1220 retval = 0;
1221 }
1222
1223 /* NOTE: non-OTG systems may use SRP TOO... */
1224 } else if (!(udc->devstat & UDC_ATT)) {
1225 if (udc->transceiver)
1226 retval = otg_start_srp(udc->transceiver);
1227 }
1228 spin_unlock_irqrestore(&udc->lock, flags);
1229
1230 return retval;
1231 }
1232
1233 static int
1234 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1235 {
1236 struct omap_udc *udc;
1237 unsigned long flags;
1238 u16 syscon1;
1239
1240 udc = container_of(gadget, struct omap_udc, gadget);
1241 spin_lock_irqsave(&udc->lock, flags);
1242 syscon1 = omap_readw(UDC_SYSCON1);
1243 if (is_selfpowered)
1244 syscon1 |= UDC_SELF_PWR;
1245 else
1246 syscon1 &= ~UDC_SELF_PWR;
1247 omap_writew(syscon1, UDC_SYSCON1);
1248 spin_unlock_irqrestore(&udc->lock, flags);
1249
1250 return 0;
1251 }
1252
1253 static int can_pullup(struct omap_udc *udc)
1254 {
1255 return udc->driver && udc->softconnect && udc->vbus_active;
1256 }
1257
1258 static void pullup_enable(struct omap_udc *udc)
1259 {
1260 u16 w;
1261
1262 w = omap_readw(UDC_SYSCON1);
1263 w |= UDC_PULLUP_EN;
1264 omap_writew(w, UDC_SYSCON1);
1265 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1266 u32 l;
1267
1268 l = omap_readl(OTG_CTRL);
1269 l |= OTG_BSESSVLD;
1270 omap_writel(l, OTG_CTRL);
1271 }
1272 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1273 }
1274
1275 static void pullup_disable(struct omap_udc *udc)
1276 {
1277 u16 w;
1278
1279 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1280 u32 l;
1281
1282 l = omap_readl(OTG_CTRL);
1283 l &= ~OTG_BSESSVLD;
1284 omap_writel(l, OTG_CTRL);
1285 }
1286 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1287 w = omap_readw(UDC_SYSCON1);
1288 w &= ~UDC_PULLUP_EN;
1289 omap_writew(w, UDC_SYSCON1);
1290 }
1291
1292 static struct omap_udc *udc;
1293
1294 static void omap_udc_enable_clock(int enable)
1295 {
1296 if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1297 return;
1298
1299 if (enable) {
1300 clk_enable(udc->dc_clk);
1301 clk_enable(udc->hhc_clk);
1302 udelay(100);
1303 } else {
1304 clk_disable(udc->hhc_clk);
1305 clk_disable(udc->dc_clk);
1306 }
1307 }
1308
1309 /*
1310 * Called by whatever detects VBUS sessions: external transceiver
1311 * driver, or maybe GPIO0 VBUS IRQ. May request 48 MHz clock.
1312 */
1313 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1314 {
1315 struct omap_udc *udc;
1316 unsigned long flags;
1317 u32 l;
1318
1319 udc = container_of(gadget, struct omap_udc, gadget);
1320 spin_lock_irqsave(&udc->lock, flags);
1321 VDBG("VBUS %s\n", is_active ? "on" : "off");
1322 udc->vbus_active = (is_active != 0);
1323 if (cpu_is_omap15xx()) {
1324 /* "software" detect, ignored if !VBUS_MODE_1510 */
1325 l = omap_readl(FUNC_MUX_CTRL_0);
1326 if (is_active)
1327 l |= VBUS_CTRL_1510;
1328 else
1329 l &= ~VBUS_CTRL_1510;
1330 omap_writel(l, FUNC_MUX_CTRL_0);
1331 }
1332 if (udc->dc_clk != NULL && is_active) {
1333 if (!udc->clk_requested) {
1334 omap_udc_enable_clock(1);
1335 udc->clk_requested = 1;
1336 }
1337 }
1338 if (can_pullup(udc))
1339 pullup_enable(udc);
1340 else
1341 pullup_disable(udc);
1342 if (udc->dc_clk != NULL && !is_active) {
1343 if (udc->clk_requested) {
1344 omap_udc_enable_clock(0);
1345 udc->clk_requested = 0;
1346 }
1347 }
1348 spin_unlock_irqrestore(&udc->lock, flags);
1349 return 0;
1350 }
1351
1352 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1353 {
1354 struct omap_udc *udc;
1355
1356 udc = container_of(gadget, struct omap_udc, gadget);
1357 if (udc->transceiver)
1358 return otg_set_power(udc->transceiver, mA);
1359 return -EOPNOTSUPP;
1360 }
1361
1362 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1363 {
1364 struct omap_udc *udc;
1365 unsigned long flags;
1366
1367 udc = container_of(gadget, struct omap_udc, gadget);
1368 spin_lock_irqsave(&udc->lock, flags);
1369 udc->softconnect = (is_on != 0);
1370 if (can_pullup(udc))
1371 pullup_enable(udc);
1372 else
1373 pullup_disable(udc);
1374 spin_unlock_irqrestore(&udc->lock, flags);
1375 return 0;
1376 }
1377
1378 static struct usb_gadget_ops omap_gadget_ops = {
1379 .get_frame = omap_get_frame,
1380 .wakeup = omap_wakeup,
1381 .set_selfpowered = omap_set_selfpowered,
1382 .vbus_session = omap_vbus_session,
1383 .vbus_draw = omap_vbus_draw,
1384 .pullup = omap_pullup,
1385 };
1386
1387 /*-------------------------------------------------------------------------*/
1388
1389 /* dequeue ALL requests; caller holds udc->lock */
1390 static void nuke(struct omap_ep *ep, int status)
1391 {
1392 struct omap_req *req;
1393
1394 ep->stopped = 1;
1395
1396 if (use_dma && ep->dma_channel)
1397 dma_channel_release(ep);
1398
1399 use_ep(ep, 0);
1400 omap_writew(UDC_CLR_EP, UDC_CTRL);
1401 if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1402 omap_writew(UDC_SET_HALT, UDC_CTRL);
1403
1404 while (!list_empty(&ep->queue)) {
1405 req = list_entry(ep->queue.next, struct omap_req, queue);
1406 done(ep, req, status);
1407 }
1408 }
1409
1410 /* caller holds udc->lock */
1411 static void udc_quiesce(struct omap_udc *udc)
1412 {
1413 struct omap_ep *ep;
1414
1415 udc->gadget.speed = USB_SPEED_UNKNOWN;
1416 nuke(&udc->ep[0], -ESHUTDOWN);
1417 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1418 nuke(ep, -ESHUTDOWN);
1419 }
1420
1421 /*-------------------------------------------------------------------------*/
1422
1423 static void update_otg(struct omap_udc *udc)
1424 {
1425 u16 devstat;
1426
1427 if (!gadget_is_otg(&udc->gadget))
1428 return;
1429
1430 if (omap_readl(OTG_CTRL) & OTG_ID)
1431 devstat = omap_readw(UDC_DEVSTAT);
1432 else
1433 devstat = 0;
1434
1435 udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1436 udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1437 udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1438
1439 /* Enable HNP early, avoiding races on suspend irq path.
1440 * ASSUMES OTG state machine B_BUS_REQ input is true.
1441 */
1442 if (udc->gadget.b_hnp_enable) {
1443 u32 l;
1444
1445 l = omap_readl(OTG_CTRL);
1446 l |= OTG_B_HNPEN | OTG_B_BUSREQ;
1447 l &= ~OTG_PULLUP;
1448 omap_writel(l, OTG_CTRL);
1449 }
1450 }
1451
1452 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1453 {
1454 struct omap_ep *ep0 = &udc->ep[0];
1455 struct omap_req *req = NULL;
1456
1457 ep0->irqs++;
1458
1459 /* Clear any pending requests and then scrub any rx/tx state
1460 * before starting to handle the SETUP request.
1461 */
1462 if (irq_src & UDC_SETUP) {
1463 u16 ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1464
1465 nuke(ep0, 0);
1466 if (ack) {
1467 omap_writew(ack, UDC_IRQ_SRC);
1468 irq_src = UDC_SETUP;
1469 }
1470 }
1471
1472 /* IN/OUT packets mean we're in the DATA or STATUS stage.
1473 * This driver uses only uses protocol stalls (ep0 never halts),
1474 * and if we got this far the gadget driver already had a
1475 * chance to stall. Tries to be forgiving of host oddities.
1476 *
1477 * NOTE: the last chance gadget drivers have to stall control
1478 * requests is during their request completion callback.
1479 */
1480 if (!list_empty(&ep0->queue))
1481 req = container_of(ep0->queue.next, struct omap_req, queue);
1482
1483 /* IN == TX to host */
1484 if (irq_src & UDC_EP0_TX) {
1485 int stat;
1486
1487 omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
1488 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1489 stat = omap_readw(UDC_STAT_FLG);
1490 if (stat & UDC_ACK) {
1491 if (udc->ep0_in) {
1492 /* write next IN packet from response,
1493 * or set up the status stage.
1494 */
1495 if (req)
1496 stat = write_fifo(ep0, req);
1497 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1498 if (!req && udc->ep0_pending) {
1499 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1500 omap_writew(UDC_CLR_EP, UDC_CTRL);
1501 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1502 omap_writew(0, UDC_EP_NUM);
1503 udc->ep0_pending = 0;
1504 } /* else: 6 wait states before it'll tx */
1505 } else {
1506 /* ack status stage of OUT transfer */
1507 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1508 if (req)
1509 done(ep0, req, 0);
1510 }
1511 req = NULL;
1512 } else if (stat & UDC_STALL) {
1513 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1514 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1515 } else {
1516 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1517 }
1518 }
1519
1520 /* OUT == RX from host */
1521 if (irq_src & UDC_EP0_RX) {
1522 int stat;
1523
1524 omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
1525 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1526 stat = omap_readw(UDC_STAT_FLG);
1527 if (stat & UDC_ACK) {
1528 if (!udc->ep0_in) {
1529 stat = 0;
1530 /* read next OUT packet of request, maybe
1531 * reactiviting the fifo; stall on errors.
1532 */
1533 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1534 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1535 udc->ep0_pending = 0;
1536 stat = 0;
1537 } else if (stat == 0)
1538 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1539 omap_writew(0, UDC_EP_NUM);
1540
1541 /* activate status stage */
1542 if (stat == 1) {
1543 done(ep0, req, 0);
1544 /* that may have STALLed ep0... */
1545 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
1546 UDC_EP_NUM);
1547 omap_writew(UDC_CLR_EP, UDC_CTRL);
1548 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1549 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1550 udc->ep0_pending = 0;
1551 }
1552 } else {
1553 /* ack status stage of IN transfer */
1554 omap_writew(0, UDC_EP_NUM);
1555 if (req)
1556 done(ep0, req, 0);
1557 }
1558 } else if (stat & UDC_STALL) {
1559 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1560 omap_writew(0, UDC_EP_NUM);
1561 } else {
1562 omap_writew(0, UDC_EP_NUM);
1563 }
1564 }
1565
1566 /* SETUP starts all control transfers */
1567 if (irq_src & UDC_SETUP) {
1568 union u {
1569 u16 word[4];
1570 struct usb_ctrlrequest r;
1571 } u;
1572 int status = -EINVAL;
1573 struct omap_ep *ep;
1574
1575 /* read the (latest) SETUP message */
1576 do {
1577 omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
1578 /* two bytes at a time */
1579 u.word[0] = omap_readw(UDC_DATA);
1580 u.word[1] = omap_readw(UDC_DATA);
1581 u.word[2] = omap_readw(UDC_DATA);
1582 u.word[3] = omap_readw(UDC_DATA);
1583 omap_writew(0, UDC_EP_NUM);
1584 } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
1585
1586 #define w_value le16_to_cpu(u.r.wValue)
1587 #define w_index le16_to_cpu(u.r.wIndex)
1588 #define w_length le16_to_cpu(u.r.wLength)
1589
1590 /* Delegate almost all control requests to the gadget driver,
1591 * except for a handful of ch9 status/feature requests that
1592 * hardware doesn't autodecode _and_ the gadget API hides.
1593 */
1594 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1595 udc->ep0_set_config = 0;
1596 udc->ep0_pending = 1;
1597 ep0->stopped = 0;
1598 ep0->ackwait = 0;
1599 switch (u.r.bRequest) {
1600 case USB_REQ_SET_CONFIGURATION:
1601 /* udc needs to know when ep != 0 is valid */
1602 if (u.r.bRequestType != USB_RECIP_DEVICE)
1603 goto delegate;
1604 if (w_length != 0)
1605 goto do_stall;
1606 udc->ep0_set_config = 1;
1607 udc->ep0_reset_config = (w_value == 0);
1608 VDBG("set config %d\n", w_value);
1609
1610 /* update udc NOW since gadget driver may start
1611 * queueing requests immediately; clear config
1612 * later if it fails the request.
1613 */
1614 if (udc->ep0_reset_config)
1615 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1616 else
1617 omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
1618 update_otg(udc);
1619 goto delegate;
1620 case USB_REQ_CLEAR_FEATURE:
1621 /* clear endpoint halt */
1622 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1623 goto delegate;
1624 if (w_value != USB_ENDPOINT_HALT
1625 || w_length != 0)
1626 goto do_stall;
1627 ep = &udc->ep[w_index & 0xf];
1628 if (ep != ep0) {
1629 if (w_index & USB_DIR_IN)
1630 ep += 16;
1631 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1632 || !ep->desc)
1633 goto do_stall;
1634 use_ep(ep, 0);
1635 omap_writew(udc->clr_halt, UDC_CTRL);
1636 ep->ackwait = 0;
1637 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1638 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1639 ep->ackwait = 1 + ep->double_buf;
1640 }
1641 /* NOTE: assumes the host behaves sanely,
1642 * only clearing real halts. Else we may
1643 * need to kill pending transfers and then
1644 * restart the queue... very messy for DMA!
1645 */
1646 }
1647 VDBG("%s halt cleared by host\n", ep->name);
1648 goto ep0out_status_stage;
1649 case USB_REQ_SET_FEATURE:
1650 /* set endpoint halt */
1651 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1652 goto delegate;
1653 if (w_value != USB_ENDPOINT_HALT
1654 || w_length != 0)
1655 goto do_stall;
1656 ep = &udc->ep[w_index & 0xf];
1657 if (w_index & USB_DIR_IN)
1658 ep += 16;
1659 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1660 || ep == ep0 || !ep->desc)
1661 goto do_stall;
1662 if (use_dma && ep->has_dma) {
1663 /* this has rude side-effects (aborts) and
1664 * can't really work if DMA-IN is active
1665 */
1666 DBG("%s host set_halt, NYET \n", ep->name);
1667 goto do_stall;
1668 }
1669 use_ep(ep, 0);
1670 /* can't halt if fifo isn't empty... */
1671 omap_writew(UDC_CLR_EP, UDC_CTRL);
1672 omap_writew(UDC_SET_HALT, UDC_CTRL);
1673 VDBG("%s halted by host\n", ep->name);
1674 ep0out_status_stage:
1675 status = 0;
1676 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1677 omap_writew(UDC_CLR_EP, UDC_CTRL);
1678 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1679 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1680 udc->ep0_pending = 0;
1681 break;
1682 case USB_REQ_GET_STATUS:
1683 /* USB_ENDPOINT_HALT status? */
1684 if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1685 goto intf_status;
1686
1687 /* ep0 never stalls */
1688 if (!(w_index & 0xf))
1689 goto zero_status;
1690
1691 /* only active endpoints count */
1692 ep = &udc->ep[w_index & 0xf];
1693 if (w_index & USB_DIR_IN)
1694 ep += 16;
1695 if (!ep->desc)
1696 goto do_stall;
1697
1698 /* iso never stalls */
1699 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1700 goto zero_status;
1701
1702 /* FIXME don't assume non-halted endpoints!! */
1703 ERR("%s status, can't report\n", ep->ep.name);
1704 goto do_stall;
1705
1706 intf_status:
1707 /* return interface status. if we were pedantic,
1708 * we'd detect non-existent interfaces, and stall.
1709 */
1710 if (u.r.bRequestType
1711 != (USB_DIR_IN|USB_RECIP_INTERFACE))
1712 goto delegate;
1713
1714 zero_status:
1715 /* return two zero bytes */
1716 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1717 omap_writew(0, UDC_DATA);
1718 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1719 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1720 status = 0;
1721 VDBG("GET_STATUS, interface %d\n", w_index);
1722 /* next, status stage */
1723 break;
1724 default:
1725 delegate:
1726 /* activate the ep0out fifo right away */
1727 if (!udc->ep0_in && w_length) {
1728 omap_writew(0, UDC_EP_NUM);
1729 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1730 }
1731
1732 /* gadget drivers see class/vendor specific requests,
1733 * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1734 * and more
1735 */
1736 VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1737 u.r.bRequestType, u.r.bRequest,
1738 w_value, w_index, w_length);
1739
1740 #undef w_value
1741 #undef w_index
1742 #undef w_length
1743
1744 /* The gadget driver may return an error here,
1745 * causing an immediate protocol stall.
1746 *
1747 * Else it must issue a response, either queueing a
1748 * response buffer for the DATA stage, or halting ep0
1749 * (causing a protocol stall, not a real halt). A
1750 * zero length buffer means no DATA stage.
1751 *
1752 * It's fine to issue that response after the setup()
1753 * call returns, and this IRQ was handled.
1754 */
1755 udc->ep0_setup = 1;
1756 spin_unlock(&udc->lock);
1757 status = udc->driver->setup (&udc->gadget, &u.r);
1758 spin_lock(&udc->lock);
1759 udc->ep0_setup = 0;
1760 }
1761
1762 if (status < 0) {
1763 do_stall:
1764 VDBG("req %02x.%02x protocol STALL; stat %d\n",
1765 u.r.bRequestType, u.r.bRequest, status);
1766 if (udc->ep0_set_config) {
1767 if (udc->ep0_reset_config)
1768 WARN("error resetting config?\n");
1769 else
1770 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1771 }
1772 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1773 udc->ep0_pending = 0;
1774 }
1775 }
1776 }
1777
1778 /*-------------------------------------------------------------------------*/
1779
1780 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1781
1782 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1783 {
1784 u16 devstat, change;
1785
1786 devstat = omap_readw(UDC_DEVSTAT);
1787 change = devstat ^ udc->devstat;
1788 udc->devstat = devstat;
1789
1790 if (change & (UDC_USB_RESET|UDC_ATT)) {
1791 udc_quiesce(udc);
1792
1793 if (change & UDC_ATT) {
1794 /* driver for any external transceiver will
1795 * have called omap_vbus_session() already
1796 */
1797 if (devstat & UDC_ATT) {
1798 udc->gadget.speed = USB_SPEED_FULL;
1799 VDBG("connect\n");
1800 if (!udc->transceiver)
1801 pullup_enable(udc);
1802 // if (driver->connect) call it
1803 } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1804 udc->gadget.speed = USB_SPEED_UNKNOWN;
1805 if (!udc->transceiver)
1806 pullup_disable(udc);
1807 DBG("disconnect, gadget %s\n",
1808 udc->driver->driver.name);
1809 if (udc->driver->disconnect) {
1810 spin_unlock(&udc->lock);
1811 udc->driver->disconnect(&udc->gadget);
1812 spin_lock(&udc->lock);
1813 }
1814 }
1815 change &= ~UDC_ATT;
1816 }
1817
1818 if (change & UDC_USB_RESET) {
1819 if (devstat & UDC_USB_RESET) {
1820 VDBG("RESET=1\n");
1821 } else {
1822 udc->gadget.speed = USB_SPEED_FULL;
1823 INFO("USB reset done, gadget %s\n",
1824 udc->driver->driver.name);
1825 /* ep0 traffic is legal from now on */
1826 omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
1827 UDC_IRQ_EN);
1828 }
1829 change &= ~UDC_USB_RESET;
1830 }
1831 }
1832 if (change & UDC_SUS) {
1833 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1834 // FIXME tell isp1301 to suspend/resume (?)
1835 if (devstat & UDC_SUS) {
1836 VDBG("suspend\n");
1837 update_otg(udc);
1838 /* HNP could be under way already */
1839 if (udc->gadget.speed == USB_SPEED_FULL
1840 && udc->driver->suspend) {
1841 spin_unlock(&udc->lock);
1842 udc->driver->suspend(&udc->gadget);
1843 spin_lock(&udc->lock);
1844 }
1845 if (udc->transceiver)
1846 otg_set_suspend(udc->transceiver, 1);
1847 } else {
1848 VDBG("resume\n");
1849 if (udc->transceiver)
1850 otg_set_suspend(udc->transceiver, 0);
1851 if (udc->gadget.speed == USB_SPEED_FULL
1852 && udc->driver->resume) {
1853 spin_unlock(&udc->lock);
1854 udc->driver->resume(&udc->gadget);
1855 spin_lock(&udc->lock);
1856 }
1857 }
1858 }
1859 change &= ~UDC_SUS;
1860 }
1861 if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1862 update_otg(udc);
1863 change &= ~OTG_FLAGS;
1864 }
1865
1866 change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1867 if (change)
1868 VDBG("devstat %03x, ignore change %03x\n",
1869 devstat, change);
1870
1871 omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
1872 }
1873
1874 static irqreturn_t omap_udc_irq(int irq, void *_udc)
1875 {
1876 struct omap_udc *udc = _udc;
1877 u16 irq_src;
1878 irqreturn_t status = IRQ_NONE;
1879 unsigned long flags;
1880
1881 spin_lock_irqsave(&udc->lock, flags);
1882 irq_src = omap_readw(UDC_IRQ_SRC);
1883
1884 /* Device state change (usb ch9 stuff) */
1885 if (irq_src & UDC_DS_CHG) {
1886 devstate_irq(_udc, irq_src);
1887 status = IRQ_HANDLED;
1888 irq_src &= ~UDC_DS_CHG;
1889 }
1890
1891 /* EP0 control transfers */
1892 if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1893 ep0_irq(_udc, irq_src);
1894 status = IRQ_HANDLED;
1895 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1896 }
1897
1898 /* DMA transfer completion */
1899 if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1900 dma_irq(_udc, irq_src);
1901 status = IRQ_HANDLED;
1902 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1903 }
1904
1905 irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
1906 if (irq_src)
1907 DBG("udc_irq, unhandled %03x\n", irq_src);
1908 spin_unlock_irqrestore(&udc->lock, flags);
1909
1910 return status;
1911 }
1912
1913 /* workaround for seemingly-lost IRQs for RX ACKs... */
1914 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1915 #define HALF_FULL(f) (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1916
1917 static void pio_out_timer(unsigned long _ep)
1918 {
1919 struct omap_ep *ep = (void *) _ep;
1920 unsigned long flags;
1921 u16 stat_flg;
1922
1923 spin_lock_irqsave(&ep->udc->lock, flags);
1924 if (!list_empty(&ep->queue) && ep->ackwait) {
1925 use_ep(ep, UDC_EP_SEL);
1926 stat_flg = omap_readw(UDC_STAT_FLG);
1927
1928 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1929 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1930 struct omap_req *req;
1931
1932 VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1933 req = container_of(ep->queue.next,
1934 struct omap_req, queue);
1935 (void) read_fifo(ep, req);
1936 omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
1937 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1938 ep->ackwait = 1 + ep->double_buf;
1939 } else
1940 deselect_ep();
1941 }
1942 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1943 spin_unlock_irqrestore(&ep->udc->lock, flags);
1944 }
1945
1946 static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1947 {
1948 u16 epn_stat, irq_src;
1949 irqreturn_t status = IRQ_NONE;
1950 struct omap_ep *ep;
1951 int epnum;
1952 struct omap_udc *udc = _dev;
1953 struct omap_req *req;
1954 unsigned long flags;
1955
1956 spin_lock_irqsave(&udc->lock, flags);
1957 epn_stat = omap_readw(UDC_EPN_STAT);
1958 irq_src = omap_readw(UDC_IRQ_SRC);
1959
1960 /* handle OUT first, to avoid some wasteful NAKs */
1961 if (irq_src & UDC_EPN_RX) {
1962 epnum = (epn_stat >> 8) & 0x0f;
1963 omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
1964 status = IRQ_HANDLED;
1965 ep = &udc->ep[epnum];
1966 ep->irqs++;
1967
1968 omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
1969 ep->fnf = 0;
1970 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1971 ep->ackwait--;
1972 if (!list_empty(&ep->queue)) {
1973 int stat;
1974 req = container_of(ep->queue.next,
1975 struct omap_req, queue);
1976 stat = read_fifo(ep, req);
1977 if (!ep->double_buf)
1978 ep->fnf = 1;
1979 }
1980 }
1981 /* min 6 clock delay before clearing EP_SEL ... */
1982 epn_stat = omap_readw(UDC_EPN_STAT);
1983 epn_stat = omap_readw(UDC_EPN_STAT);
1984 omap_writew(epnum, UDC_EP_NUM);
1985
1986 /* enabling fifo _after_ clearing ACK, contrary to docs,
1987 * reduces lossage; timer still needed though (sigh).
1988 */
1989 if (ep->fnf) {
1990 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1991 ep->ackwait = 1 + ep->double_buf;
1992 }
1993 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1994 }
1995
1996 /* then IN transfers */
1997 else if (irq_src & UDC_EPN_TX) {
1998 epnum = epn_stat & 0x0f;
1999 omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
2000 status = IRQ_HANDLED;
2001 ep = &udc->ep[16 + epnum];
2002 ep->irqs++;
2003
2004 omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
2005 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
2006 ep->ackwait = 0;
2007 if (!list_empty(&ep->queue)) {
2008 req = container_of(ep->queue.next,
2009 struct omap_req, queue);
2010 (void) write_fifo(ep, req);
2011 }
2012 }
2013 /* min 6 clock delay before clearing EP_SEL ... */
2014 epn_stat = omap_readw(UDC_EPN_STAT);
2015 epn_stat = omap_readw(UDC_EPN_STAT);
2016 omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
2017 /* then 6 clocks before it'd tx */
2018 }
2019
2020 spin_unlock_irqrestore(&udc->lock, flags);
2021 return status;
2022 }
2023
2024 #ifdef USE_ISO
2025 static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
2026 {
2027 struct omap_udc *udc = _dev;
2028 struct omap_ep *ep;
2029 int pending = 0;
2030 unsigned long flags;
2031
2032 spin_lock_irqsave(&udc->lock, flags);
2033
2034 /* handle all non-DMA ISO transfers */
2035 list_for_each_entry (ep, &udc->iso, iso) {
2036 u16 stat;
2037 struct omap_req *req;
2038
2039 if (ep->has_dma || list_empty(&ep->queue))
2040 continue;
2041 req = list_entry(ep->queue.next, struct omap_req, queue);
2042
2043 use_ep(ep, UDC_EP_SEL);
2044 stat = omap_readw(UDC_STAT_FLG);
2045
2046 /* NOTE: like the other controller drivers, this isn't
2047 * currently reporting lost or damaged frames.
2048 */
2049 if (ep->bEndpointAddress & USB_DIR_IN) {
2050 if (stat & UDC_MISS_IN)
2051 /* done(ep, req, -EPROTO) */;
2052 else
2053 write_fifo(ep, req);
2054 } else {
2055 int status = 0;
2056
2057 if (stat & UDC_NO_RXPACKET)
2058 status = -EREMOTEIO;
2059 else if (stat & UDC_ISO_ERR)
2060 status = -EILSEQ;
2061 else if (stat & UDC_DATA_FLUSH)
2062 status = -ENOSR;
2063
2064 if (status)
2065 /* done(ep, req, status) */;
2066 else
2067 read_fifo(ep, req);
2068 }
2069 deselect_ep();
2070 /* 6 wait states before next EP */
2071
2072 ep->irqs++;
2073 if (!list_empty(&ep->queue))
2074 pending = 1;
2075 }
2076 if (!pending) {
2077 u16 w;
2078
2079 w = omap_readw(UDC_IRQ_EN);
2080 w &= ~UDC_SOF_IE;
2081 omap_writew(w, UDC_IRQ_EN);
2082 }
2083 omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
2084
2085 spin_unlock_irqrestore(&udc->lock, flags);
2086 return IRQ_HANDLED;
2087 }
2088 #endif
2089
2090 /*-------------------------------------------------------------------------*/
2091
2092 static inline int machine_without_vbus_sense(void)
2093 {
2094 return (machine_is_omap_innovator()
2095 || machine_is_omap_osk()
2096 || machine_is_omap_apollon()
2097 #ifndef CONFIG_MACH_OMAP_H4_OTG
2098 || machine_is_omap_h4()
2099 #endif
2100 || machine_is_sx1()
2101 );
2102 }
2103
2104 int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2105 {
2106 int status = -ENODEV;
2107 struct omap_ep *ep;
2108 unsigned long flags;
2109
2110 /* basic sanity tests */
2111 if (!udc)
2112 return -ENODEV;
2113 if (!driver
2114 // FIXME if otg, check: driver->is_otg
2115 || driver->speed < USB_SPEED_FULL
2116 || !driver->bind
2117 || !driver->setup)
2118 return -EINVAL;
2119
2120 spin_lock_irqsave(&udc->lock, flags);
2121 if (udc->driver) {
2122 spin_unlock_irqrestore(&udc->lock, flags);
2123 return -EBUSY;
2124 }
2125
2126 /* reset state */
2127 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2128 ep->irqs = 0;
2129 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2130 continue;
2131 use_ep(ep, 0);
2132 omap_writew(UDC_SET_HALT, UDC_CTRL);
2133 }
2134 udc->ep0_pending = 0;
2135 udc->ep[0].irqs = 0;
2136 udc->softconnect = 1;
2137
2138 /* hook up the driver */
2139 driver->driver.bus = NULL;
2140 udc->driver = driver;
2141 udc->gadget.dev.driver = &driver->driver;
2142 spin_unlock_irqrestore(&udc->lock, flags);
2143
2144 if (udc->dc_clk != NULL)
2145 omap_udc_enable_clock(1);
2146
2147 status = driver->bind (&udc->gadget);
2148 if (status) {
2149 DBG("bind to %s --> %d\n", driver->driver.name, status);
2150 udc->gadget.dev.driver = NULL;
2151 udc->driver = NULL;
2152 goto done;
2153 }
2154 DBG("bound to driver %s\n", driver->driver.name);
2155
2156 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2157
2158 /* connect to bus through transceiver */
2159 if (udc->transceiver) {
2160 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2161 if (status < 0) {
2162 ERR("can't bind to transceiver\n");
2163 if (driver->unbind) {
2164 driver->unbind (&udc->gadget);
2165 udc->gadget.dev.driver = NULL;
2166 udc->driver = NULL;
2167 }
2168 goto done;
2169 }
2170 } else {
2171 if (can_pullup(udc))
2172 pullup_enable (udc);
2173 else
2174 pullup_disable (udc);
2175 }
2176
2177 /* boards that don't have VBUS sensing can't autogate 48MHz;
2178 * can't enter deep sleep while a gadget driver is active.
2179 */
2180 if (machine_without_vbus_sense())
2181 omap_vbus_session(&udc->gadget, 1);
2182
2183 done:
2184 if (udc->dc_clk != NULL)
2185 omap_udc_enable_clock(0);
2186 return status;
2187 }
2188 EXPORT_SYMBOL(usb_gadget_register_driver);
2189
2190 int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
2191 {
2192 unsigned long flags;
2193 int status = -ENODEV;
2194
2195 if (!udc)
2196 return -ENODEV;
2197 if (!driver || driver != udc->driver || !driver->unbind)
2198 return -EINVAL;
2199
2200 if (udc->dc_clk != NULL)
2201 omap_udc_enable_clock(1);
2202
2203 if (machine_without_vbus_sense())
2204 omap_vbus_session(&udc->gadget, 0);
2205
2206 if (udc->transceiver)
2207 (void) otg_set_peripheral(udc->transceiver, NULL);
2208 else
2209 pullup_disable(udc);
2210
2211 spin_lock_irqsave(&udc->lock, flags);
2212 udc_quiesce(udc);
2213 spin_unlock_irqrestore(&udc->lock, flags);
2214
2215 driver->unbind(&udc->gadget);
2216 udc->gadget.dev.driver = NULL;
2217 udc->driver = NULL;
2218
2219 if (udc->dc_clk != NULL)
2220 omap_udc_enable_clock(0);
2221 DBG("unregistered driver '%s'\n", driver->driver.name);
2222 return status;
2223 }
2224 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2225
2226
2227 /*-------------------------------------------------------------------------*/
2228
2229 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2230
2231 #include <linux/seq_file.h>
2232
2233 static const char proc_filename[] = "driver/udc";
2234
2235 #define FOURBITS "%s%s%s%s"
2236 #define EIGHTBITS FOURBITS FOURBITS
2237
2238 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2239 {
2240 u16 stat_flg;
2241 struct omap_req *req;
2242 char buf[20];
2243
2244 use_ep(ep, 0);
2245
2246 if (use_dma && ep->has_dma)
2247 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2248 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2249 ep->dma_channel - 1, ep->lch);
2250 else
2251 buf[0] = 0;
2252
2253 stat_flg = omap_readw(UDC_STAT_FLG);
2254 seq_printf(s,
2255 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2256 ep->name, buf,
2257 ep->double_buf ? "dbuf " : "",
2258 ({char *s; switch(ep->ackwait){
2259 case 0: s = ""; break;
2260 case 1: s = "(ackw) "; break;
2261 case 2: s = "(ackw2) "; break;
2262 default: s = "(?) "; break;
2263 } s;}),
2264 ep->irqs, stat_flg,
2265 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2266 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2267 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2268 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2269 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2270 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2271 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2272 (stat_flg & UDC_STALL) ? "STALL " : "",
2273 (stat_flg & UDC_NAK) ? "NAK " : "",
2274 (stat_flg & UDC_ACK) ? "ACK " : "",
2275 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2276 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2277 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2278
2279 if (list_empty (&ep->queue))
2280 seq_printf(s, "\t(queue empty)\n");
2281 else
2282 list_for_each_entry (req, &ep->queue, queue) {
2283 unsigned length = req->req.actual;
2284
2285 if (use_dma && buf[0]) {
2286 length += ((ep->bEndpointAddress & USB_DIR_IN)
2287 ? dma_src_len : dma_dest_len)
2288 (ep, req->req.dma + length);
2289 buf[0] = 0;
2290 }
2291 seq_printf(s, "\treq %p len %d/%d buf %p\n",
2292 &req->req, length,
2293 req->req.length, req->req.buf);
2294 }
2295 }
2296
2297 static char *trx_mode(unsigned m, int enabled)
2298 {
2299 switch (m) {
2300 case 0: return enabled ? "*6wire" : "unused";
2301 case 1: return "4wire";
2302 case 2: return "3wire";
2303 case 3: return "6wire";
2304 default: return "unknown";
2305 }
2306 }
2307
2308 static int proc_otg_show(struct seq_file *s)
2309 {
2310 u32 tmp;
2311 u32 trans;
2312 char *ctrl_name;
2313
2314 tmp = omap_readw(OTG_REV);
2315 if (cpu_is_omap24xx()) {
2316 /*
2317 * REVISIT: Not clear how this works on OMAP2. trans
2318 * is ANDed to produce bits 7 and 8, which might make
2319 * sense for USB_TRANSCEIVER_CTRL on OMAP1,
2320 * but with CONTROL_DEVCONF, these bits have something to
2321 * do with the frame adjustment counter and McBSP2.
2322 */
2323 ctrl_name = "control_devconf";
2324 trans = omap_ctrl_readb(OMAP2_CONTROL_DEVCONF0);
2325 } else {
2326 ctrl_name = "tranceiver_ctrl";
2327 trans = omap_readw(USB_TRANSCEIVER_CTRL);
2328 }
2329 seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2330 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2331 tmp = omap_readw(OTG_SYSCON_1);
2332 seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2333 FOURBITS "\n", tmp,
2334 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2335 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2336 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2337 ? "internal"
2338 : trx_mode(USB0_TRX_MODE(tmp), 1),
2339 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2340 (tmp & HST_IDLE_EN) ? " !host" : "",
2341 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2342 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2343 tmp = omap_readl(OTG_SYSCON_2);
2344 seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2345 " b_ase_brst=%d hmc=%d\n", tmp,
2346 (tmp & OTG_EN) ? " otg_en" : "",
2347 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2348 // much more SRP stuff
2349 (tmp & SRP_DATA) ? " srp_data" : "",
2350 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2351 (tmp & OTG_PADEN) ? " otg_paden" : "",
2352 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2353 (tmp & UHOST_EN) ? " uhost_en" : "",
2354 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2355 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2356 B_ASE_BRST(tmp),
2357 OTG_HMC(tmp));
2358 tmp = omap_readl(OTG_CTRL);
2359 seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2360 (tmp & OTG_ASESSVLD) ? " asess" : "",
2361 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2362 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2363 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2364 (tmp & OTG_ID) ? " id" : "",
2365 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2366 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2367 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2368 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2369 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2370 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2371 (tmp & OTG_PULLDOWN) ? " down" : "",
2372 (tmp & OTG_PULLUP) ? " up" : "",
2373 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2374 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2375 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2376 (tmp & OTG_PU_ID) ? " pu_id" : ""
2377 );
2378 tmp = omap_readw(OTG_IRQ_EN);
2379 seq_printf(s, "otg_irq_en %04x" "\n", tmp);
2380 tmp = omap_readw(OTG_IRQ_SRC);
2381 seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2382 tmp = omap_readw(OTG_OUTCTRL);
2383 seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2384 tmp = omap_readw(OTG_TEST);
2385 seq_printf(s, "otg_test %04x" "\n", tmp);
2386 return 0;
2387 }
2388
2389 static int proc_udc_show(struct seq_file *s, void *_)
2390 {
2391 u32 tmp;
2392 struct omap_ep *ep;
2393 unsigned long flags;
2394
2395 spin_lock_irqsave(&udc->lock, flags);
2396
2397 seq_printf(s, "%s, version: " DRIVER_VERSION
2398 #ifdef USE_ISO
2399 " (iso)"
2400 #endif
2401 "%s\n",
2402 driver_desc,
2403 use_dma ? " (dma)" : "");
2404
2405 tmp = omap_readw(UDC_REV) & 0xff;
2406 seq_printf(s,
2407 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2408 "hmc %d, transceiver %s\n",
2409 tmp >> 4, tmp & 0xf,
2410 fifo_mode,
2411 udc->driver ? udc->driver->driver.name : "(none)",
2412 HMC,
2413 udc->transceiver
2414 ? udc->transceiver->label
2415 : ((cpu_is_omap1710() || cpu_is_omap24xx())
2416 ? "external" : "(none)"));
2417 if (cpu_class_is_omap1()) {
2418 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2419 omap_readw(ULPD_CLOCK_CTRL),
2420 omap_readw(ULPD_SOFT_REQ),
2421 omap_readw(ULPD_STATUS_REQ));
2422 }
2423
2424 /* OTG controller registers */
2425 if (!cpu_is_omap15xx())
2426 proc_otg_show(s);
2427
2428 tmp = omap_readw(UDC_SYSCON1);
2429 seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp,
2430 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2431 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2432 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2433 (tmp & UDC_NAK_EN) ? " nak" : "",
2434 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2435 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2436 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2437 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2438 // syscon2 is write-only
2439
2440 /* UDC controller registers */
2441 if (!(tmp & UDC_PULLUP_EN)) {
2442 seq_printf(s, "(suspended)\n");
2443 spin_unlock_irqrestore(&udc->lock, flags);
2444 return 0;
2445 }
2446
2447 tmp = omap_readw(UDC_DEVSTAT);
2448 seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp,
2449 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2450 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2451 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2452 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2453 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2454 (tmp & UDC_SUS) ? " SUS" : "",
2455 (tmp & UDC_CFG) ? " CFG" : "",
2456 (tmp & UDC_ADD) ? " ADD" : "",
2457 (tmp & UDC_DEF) ? " DEF" : "",
2458 (tmp & UDC_ATT) ? " ATT" : "");
2459 seq_printf(s, "sof %04x\n", omap_readw(UDC_SOF));
2460 tmp = omap_readw(UDC_IRQ_EN);
2461 seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp,
2462 (tmp & UDC_SOF_IE) ? " sof" : "",
2463 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2464 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2465 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2466 (tmp & UDC_EP0_IE) ? " ep0" : "");
2467 tmp = omap_readw(UDC_IRQ_SRC);
2468 seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp,
2469 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2470 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2471 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2472 (tmp & UDC_IRQ_SOF) ? " sof" : "",
2473 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2474 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2475 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2476 (tmp & UDC_SETUP) ? " setup" : "",
2477 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2478 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2479 if (use_dma) {
2480 unsigned i;
2481
2482 tmp = omap_readw(UDC_DMA_IRQ_EN);
2483 seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp,
2484 (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2485 (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2486 (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2487
2488 (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2489 (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2490 (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2491
2492 (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2493 (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2494 (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2495
2496 tmp = omap_readw(UDC_RXDMA_CFG);
2497 seq_printf(s, "rxdma_cfg %04x\n", tmp);
2498 if (tmp) {
2499 for (i = 0; i < 3; i++) {
2500 if ((tmp & (0x0f << (i * 4))) == 0)
2501 continue;
2502 seq_printf(s, "rxdma[%d] %04x\n", i,
2503 omap_readw(UDC_RXDMA(i + 1)));
2504 }
2505 }
2506 tmp = omap_readw(UDC_TXDMA_CFG);
2507 seq_printf(s, "txdma_cfg %04x\n", tmp);
2508 if (tmp) {
2509 for (i = 0; i < 3; i++) {
2510 if (!(tmp & (0x0f << (i * 4))))
2511 continue;
2512 seq_printf(s, "txdma[%d] %04x\n", i,
2513 omap_readw(UDC_TXDMA(i + 1)));
2514 }
2515 }
2516 }
2517
2518 tmp = omap_readw(UDC_DEVSTAT);
2519 if (tmp & UDC_ATT) {
2520 proc_ep_show(s, &udc->ep[0]);
2521 if (tmp & UDC_ADD) {
2522 list_for_each_entry (ep, &udc->gadget.ep_list,
2523 ep.ep_list) {
2524 if (ep->desc)
2525 proc_ep_show(s, ep);
2526 }
2527 }
2528 }
2529 spin_unlock_irqrestore(&udc->lock, flags);
2530 return 0;
2531 }
2532
2533 static int proc_udc_open(struct inode *inode, struct file *file)
2534 {
2535 return single_open(file, proc_udc_show, NULL);
2536 }
2537
2538 static const struct file_operations proc_ops = {
2539 .owner = THIS_MODULE,
2540 .open = proc_udc_open,
2541 .read = seq_read,
2542 .llseek = seq_lseek,
2543 .release = single_release,
2544 };
2545
2546 static void create_proc_file(void)
2547 {
2548 proc_create(proc_filename, 0, NULL, &proc_ops);
2549 }
2550
2551 static void remove_proc_file(void)
2552 {
2553 remove_proc_entry(proc_filename, NULL);
2554 }
2555
2556 #else
2557
2558 static inline void create_proc_file(void) {}
2559 static inline void remove_proc_file(void) {}
2560
2561 #endif
2562
2563 /*-------------------------------------------------------------------------*/
2564
2565 /* Before this controller can enumerate, we need to pick an endpoint
2566 * configuration, or "fifo_mode" That involves allocating 2KB of packet
2567 * buffer space among the endpoints we'll be operating.
2568 *
2569 * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2570 * UDC_SYSCON_1.CFG_LOCK is set can now work. We won't use that
2571 * capability yet though.
2572 */
2573 static unsigned __init
2574 omap_ep_setup(char *name, u8 addr, u8 type,
2575 unsigned buf, unsigned maxp, int dbuf)
2576 {
2577 struct omap_ep *ep;
2578 u16 epn_rxtx = 0;
2579
2580 /* OUT endpoints first, then IN */
2581 ep = &udc->ep[addr & 0xf];
2582 if (addr & USB_DIR_IN)
2583 ep += 16;
2584
2585 /* in case of ep init table bugs */
2586 BUG_ON(ep->name[0]);
2587
2588 /* chip setup ... bit values are same for IN, OUT */
2589 if (type == USB_ENDPOINT_XFER_ISOC) {
2590 switch (maxp) {
2591 case 8: epn_rxtx = 0 << 12; break;
2592 case 16: epn_rxtx = 1 << 12; break;
2593 case 32: epn_rxtx = 2 << 12; break;
2594 case 64: epn_rxtx = 3 << 12; break;
2595 case 128: epn_rxtx = 4 << 12; break;
2596 case 256: epn_rxtx = 5 << 12; break;
2597 case 512: epn_rxtx = 6 << 12; break;
2598 default: BUG();
2599 }
2600 epn_rxtx |= UDC_EPN_RX_ISO;
2601 dbuf = 1;
2602 } else {
2603 /* double-buffering "not supported" on 15xx,
2604 * and ignored for PIO-IN on newer chips
2605 * (for more reliable behavior)
2606 */
2607 if ((!use_dma && (addr & USB_DIR_IN))
2608 || machine_is_omap_apollon()
2609 || cpu_is_omap15xx())
2610 dbuf = 0;
2611
2612 switch (maxp) {
2613 case 8: epn_rxtx = 0 << 12; break;
2614 case 16: epn_rxtx = 1 << 12; break;
2615 case 32: epn_rxtx = 2 << 12; break;
2616 case 64: epn_rxtx = 3 << 12; break;
2617 default: BUG();
2618 }
2619 if (dbuf && addr)
2620 epn_rxtx |= UDC_EPN_RX_DB;
2621 init_timer(&ep->timer);
2622 ep->timer.function = pio_out_timer;
2623 ep->timer.data = (unsigned long) ep;
2624 }
2625 if (addr)
2626 epn_rxtx |= UDC_EPN_RX_VALID;
2627 BUG_ON(buf & 0x07);
2628 epn_rxtx |= buf >> 3;
2629
2630 DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2631 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2632
2633 if (addr & USB_DIR_IN)
2634 omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
2635 else
2636 omap_writew(epn_rxtx, UDC_EP_RX(addr));
2637
2638 /* next endpoint's buffer starts after this one's */
2639 buf += maxp;
2640 if (dbuf)
2641 buf += maxp;
2642 BUG_ON(buf > 2048);
2643
2644 /* set up driver data structures */
2645 BUG_ON(strlen(name) >= sizeof ep->name);
2646 strlcpy(ep->name, name, sizeof ep->name);
2647 INIT_LIST_HEAD(&ep->queue);
2648 INIT_LIST_HEAD(&ep->iso);
2649 ep->bEndpointAddress = addr;
2650 ep->bmAttributes = type;
2651 ep->double_buf = dbuf;
2652 ep->udc = udc;
2653
2654 ep->ep.name = ep->name;
2655 ep->ep.ops = &omap_ep_ops;
2656 ep->ep.maxpacket = ep->maxpacket = maxp;
2657 list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2658
2659 return buf;
2660 }
2661
2662 static void omap_udc_release(struct device *dev)
2663 {
2664 complete(udc->done);
2665 kfree (udc);
2666 udc = NULL;
2667 }
2668
2669 static int __init
2670 omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2671 {
2672 unsigned tmp, buf;
2673
2674 /* abolish any previous hardware state */
2675 omap_writew(0, UDC_SYSCON1);
2676 omap_writew(0, UDC_IRQ_EN);
2677 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2678 omap_writew(0, UDC_DMA_IRQ_EN);
2679 omap_writew(0, UDC_RXDMA_CFG);
2680 omap_writew(0, UDC_TXDMA_CFG);
2681
2682 /* UDC_PULLUP_EN gates the chip clock */
2683 // OTG_SYSCON_1 |= DEV_IDLE_EN;
2684
2685 udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2686 if (!udc)
2687 return -ENOMEM;
2688
2689 spin_lock_init (&udc->lock);
2690
2691 udc->gadget.ops = &omap_gadget_ops;
2692 udc->gadget.ep0 = &udc->ep[0].ep;
2693 INIT_LIST_HEAD(&udc->gadget.ep_list);
2694 INIT_LIST_HEAD(&udc->iso);
2695 udc->gadget.speed = USB_SPEED_UNKNOWN;
2696 udc->gadget.name = driver_name;
2697
2698 device_initialize(&udc->gadget.dev);
2699 strcpy (udc->gadget.dev.bus_id, "gadget");
2700 udc->gadget.dev.release = omap_udc_release;
2701 udc->gadget.dev.parent = &odev->dev;
2702 if (use_dma)
2703 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2704
2705 udc->transceiver = xceiv;
2706
2707 /* ep0 is special; put it right after the SETUP buffer */
2708 buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2709 8 /* after SETUP */, 64 /* maxpacket */, 0);
2710 list_del_init(&udc->ep[0].ep.ep_list);
2711
2712 /* initially disable all non-ep0 endpoints */
2713 for (tmp = 1; tmp < 15; tmp++) {
2714 omap_writew(0, UDC_EP_RX(tmp));
2715 omap_writew(0, UDC_EP_TX(tmp));
2716 }
2717
2718 #define OMAP_BULK_EP(name,addr) \
2719 buf = omap_ep_setup(name "-bulk", addr, \
2720 USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2721 #define OMAP_INT_EP(name,addr, maxp) \
2722 buf = omap_ep_setup(name "-int", addr, \
2723 USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2724 #define OMAP_ISO_EP(name,addr, maxp) \
2725 buf = omap_ep_setup(name "-iso", addr, \
2726 USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2727
2728 switch (fifo_mode) {
2729 case 0:
2730 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2731 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2732 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2733 break;
2734 case 1:
2735 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2736 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2737 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2738
2739 OMAP_BULK_EP("ep3in", USB_DIR_IN | 3);
2740 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2741 OMAP_INT_EP("ep10in", USB_DIR_IN | 10, 16);
2742
2743 OMAP_BULK_EP("ep5in", USB_DIR_IN | 5);
2744 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2745 OMAP_INT_EP("ep11in", USB_DIR_IN | 11, 16);
2746
2747 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2748 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2749 OMAP_INT_EP("ep12in", USB_DIR_IN | 12, 16);
2750
2751 OMAP_BULK_EP("ep7in", USB_DIR_IN | 7);
2752 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2753 OMAP_INT_EP("ep13in", USB_DIR_IN | 13, 16);
2754 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2755
2756 OMAP_BULK_EP("ep8in", USB_DIR_IN | 8);
2757 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2758 OMAP_INT_EP("ep14in", USB_DIR_IN | 14, 16);
2759 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2760
2761 OMAP_BULK_EP("ep15in", USB_DIR_IN | 15);
2762 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2763
2764 break;
2765
2766 #ifdef USE_ISO
2767 case 2: /* mixed iso/bulk */
2768 OMAP_ISO_EP("ep1in", USB_DIR_IN | 1, 256);
2769 OMAP_ISO_EP("ep2out", USB_DIR_OUT | 2, 256);
2770 OMAP_ISO_EP("ep3in", USB_DIR_IN | 3, 128);
2771 OMAP_ISO_EP("ep4out", USB_DIR_OUT | 4, 128);
2772
2773 OMAP_INT_EP("ep5in", USB_DIR_IN | 5, 16);
2774
2775 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2776 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2777 OMAP_INT_EP("ep8in", USB_DIR_IN | 8, 16);
2778 break;
2779 case 3: /* mixed bulk/iso */
2780 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2781 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2782 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2783
2784 OMAP_BULK_EP("ep4in", USB_DIR_IN | 4);
2785 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2786 OMAP_INT_EP("ep6in", USB_DIR_IN | 6, 16);
2787
2788 OMAP_ISO_EP("ep7in", USB_DIR_IN | 7, 256);
2789 OMAP_ISO_EP("ep8out", USB_DIR_OUT | 8, 256);
2790 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2791 break;
2792 #endif
2793
2794 /* add more modes as needed */
2795
2796 default:
2797 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2798 return -ENODEV;
2799 }
2800 omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
2801 INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2802 return 0;
2803 }
2804
2805 static int __init omap_udc_probe(struct platform_device *pdev)
2806 {
2807 int status = -ENODEV;
2808 int hmc;
2809 struct otg_transceiver *xceiv = NULL;
2810 const char *type = NULL;
2811 struct omap_usb_config *config = pdev->dev.platform_data;
2812 struct clk *dc_clk;
2813 struct clk *hhc_clk;
2814
2815 /* NOTE: "knows" the order of the resources! */
2816 if (!request_mem_region(pdev->resource[0].start,
2817 pdev->resource[0].end - pdev->resource[0].start + 1,
2818 driver_name)) {
2819 DBG("request_mem_region failed\n");
2820 return -EBUSY;
2821 }
2822
2823 if (cpu_is_omap16xx()) {
2824 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2825 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2826 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2827 /* can't use omap_udc_enable_clock yet */
2828 clk_enable(dc_clk);
2829 clk_enable(hhc_clk);
2830 udelay(100);
2831 }
2832
2833 if (cpu_is_omap24xx()) {
2834 dc_clk = clk_get(&pdev->dev, "usb_fck");
2835 hhc_clk = clk_get(&pdev->dev, "usb_l4_ick");
2836 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2837 /* can't use omap_udc_enable_clock yet */
2838 clk_enable(dc_clk);
2839 clk_enable(hhc_clk);
2840 udelay(100);
2841 }
2842
2843 INFO("OMAP UDC rev %d.%d%s\n",
2844 omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
2845 config->otg ? ", Mini-AB" : "");
2846
2847 /* use the mode given to us by board init code */
2848 if (cpu_is_omap15xx()) {
2849 hmc = HMC_1510;
2850 type = "(unknown)";
2851
2852 if (machine_without_vbus_sense()) {
2853 /* just set up software VBUS detect, and then
2854 * later rig it so we always report VBUS.
2855 * FIXME without really sensing VBUS, we can't
2856 * know when to turn PULLUP_EN on/off; and that
2857 * means we always "need" the 48MHz clock.
2858 */
2859 u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
2860 tmp &= ~VBUS_CTRL_1510;
2861 omap_writel(tmp, FUNC_MUX_CTRL_0);
2862 tmp |= VBUS_MODE_1510;
2863 tmp &= ~VBUS_CTRL_1510;
2864 omap_writel(tmp, FUNC_MUX_CTRL_0);
2865 }
2866 } else {
2867 /* The transceiver may package some GPIO logic or handle
2868 * loopback and/or transceiverless setup; if we find one,
2869 * use it. Except for OTG, we don't _need_ to talk to one;
2870 * but not having one probably means no VBUS detection.
2871 */
2872 xceiv = otg_get_transceiver();
2873 if (xceiv)
2874 type = xceiv->label;
2875 else if (config->otg) {
2876 DBG("OTG requires external transceiver!\n");
2877 goto cleanup0;
2878 }
2879
2880 hmc = HMC_1610;
2881
2882 if (cpu_is_omap24xx()) {
2883 /* this could be transceiverless in one of the
2884 * "we don't need to know" modes.
2885 */
2886 type = "external";
2887 goto known;
2888 }
2889
2890 switch (hmc) {
2891 case 0: /* POWERUP DEFAULT == 0 */
2892 case 4:
2893 case 12:
2894 case 20:
2895 if (!cpu_is_omap1710()) {
2896 type = "integrated";
2897 break;
2898 }
2899 /* FALL THROUGH */
2900 case 3:
2901 case 11:
2902 case 16:
2903 case 19:
2904 case 25:
2905 if (!xceiv) {
2906 DBG("external transceiver not registered!\n");
2907 type = "unknown";
2908 }
2909 break;
2910 case 21: /* internal loopback */
2911 type = "loopback";
2912 break;
2913 case 14: /* transceiverless */
2914 if (cpu_is_omap1710())
2915 goto bad_on_1710;
2916 /* FALL THROUGH */
2917 case 13:
2918 case 15:
2919 type = "no";
2920 break;
2921
2922 default:
2923 bad_on_1710:
2924 ERR("unrecognized UDC HMC mode %d\n", hmc);
2925 goto cleanup0;
2926 }
2927 }
2928 known:
2929 INFO("hmc mode %d, %s transceiver\n", hmc, type);
2930
2931 /* a "gadget" abstracts/virtualizes the controller */
2932 status = omap_udc_setup(pdev, xceiv);
2933 if (status) {
2934 goto cleanup0;
2935 }
2936 xceiv = NULL;
2937 // "udc" is now valid
2938 pullup_disable(udc);
2939 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2940 udc->gadget.is_otg = (config->otg != 0);
2941 #endif
2942
2943 /* starting with omap1710 es2.0, clear toggle is a separate bit */
2944 if (omap_readw(UDC_REV) >= 0x61)
2945 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2946 else
2947 udc->clr_halt = UDC_RESET_EP;
2948
2949 /* USB general purpose IRQ: ep0, state changes, dma, etc */
2950 status = request_irq(pdev->resource[1].start, omap_udc_irq,
2951 IRQF_SAMPLE_RANDOM, driver_name, udc);
2952 if (status != 0) {
2953 ERR("can't get irq %d, err %d\n",
2954 (int) pdev->resource[1].start, status);
2955 goto cleanup1;
2956 }
2957
2958 /* USB "non-iso" IRQ (PIO for all but ep0) */
2959 status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2960 IRQF_SAMPLE_RANDOM, "omap_udc pio", udc);
2961 if (status != 0) {
2962 ERR("can't get irq %d, err %d\n",
2963 (int) pdev->resource[2].start, status);
2964 goto cleanup2;
2965 }
2966 #ifdef USE_ISO
2967 status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2968 IRQF_DISABLED, "omap_udc iso", udc);
2969 if (status != 0) {
2970 ERR("can't get irq %d, err %d\n",
2971 (int) pdev->resource[3].start, status);
2972 goto cleanup3;
2973 }
2974 #endif
2975 if (cpu_is_omap16xx()) {
2976 udc->dc_clk = dc_clk;
2977 udc->hhc_clk = hhc_clk;
2978 clk_disable(hhc_clk);
2979 clk_disable(dc_clk);
2980 }
2981
2982 if (cpu_is_omap24xx()) {
2983 udc->dc_clk = dc_clk;
2984 udc->hhc_clk = hhc_clk;
2985 /* FIXME OMAP2 don't release hhc & dc clock */
2986 #if 0
2987 clk_disable(hhc_clk);
2988 clk_disable(dc_clk);
2989 #endif
2990 }
2991
2992 create_proc_file();
2993 status = device_add(&udc->gadget.dev);
2994 if (!status)
2995 return status;
2996 /* If fail, fall through */
2997 #ifdef USE_ISO
2998 cleanup3:
2999 free_irq(pdev->resource[2].start, udc);
3000 #endif
3001
3002 cleanup2:
3003 free_irq(pdev->resource[1].start, udc);
3004
3005 cleanup1:
3006 kfree (udc);
3007 udc = NULL;
3008
3009 cleanup0:
3010 if (xceiv)
3011 put_device(xceiv->dev);
3012
3013 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
3014 clk_disable(hhc_clk);
3015 clk_disable(dc_clk);
3016 clk_put(hhc_clk);
3017 clk_put(dc_clk);
3018 }
3019
3020 release_mem_region(pdev->resource[0].start,
3021 pdev->resource[0].end - pdev->resource[0].start + 1);
3022
3023 return status;
3024 }
3025
3026 static int __exit omap_udc_remove(struct platform_device *pdev)
3027 {
3028 DECLARE_COMPLETION_ONSTACK(done);
3029
3030 if (!udc)
3031 return -ENODEV;
3032 if (udc->driver)
3033 return -EBUSY;
3034
3035 udc->done = &done;
3036
3037 pullup_disable(udc);
3038 if (udc->transceiver) {
3039 put_device(udc->transceiver->dev);
3040 udc->transceiver = NULL;
3041 }
3042 omap_writew(0, UDC_SYSCON1);
3043
3044 remove_proc_file();
3045
3046 #ifdef USE_ISO
3047 free_irq(pdev->resource[3].start, udc);
3048 #endif
3049 free_irq(pdev->resource[2].start, udc);
3050 free_irq(pdev->resource[1].start, udc);
3051
3052 if (udc->dc_clk) {
3053 if (udc->clk_requested)
3054 omap_udc_enable_clock(0);
3055 clk_put(udc->hhc_clk);
3056 clk_put(udc->dc_clk);
3057 }
3058
3059 release_mem_region(pdev->resource[0].start,
3060 pdev->resource[0].end - pdev->resource[0].start + 1);
3061
3062 device_unregister(&udc->gadget.dev);
3063 wait_for_completion(&done);
3064
3065 return 0;
3066 }
3067
3068 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3069 * system is forced into deep sleep
3070 *
3071 * REVISIT we should probably reject suspend requests when there's a host
3072 * session active, rather than disconnecting, at least on boards that can
3073 * report VBUS irqs (UDC_DEVSTAT.UDC_ATT). And in any case, we need to
3074 * make host resumes and VBUS detection trigger OMAP wakeup events; that
3075 * may involve talking to an external transceiver (e.g. isp1301).
3076 */
3077
3078 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3079 {
3080 u32 devstat;
3081
3082 devstat = omap_readw(UDC_DEVSTAT);
3083
3084 /* we're requesting 48 MHz clock if the pullup is enabled
3085 * (== we're attached to the host) and we're not suspended,
3086 * which would prevent entry to deep sleep...
3087 */
3088 if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3089 WARN("session active; suspend requires disconnect\n");
3090 omap_pullup(&udc->gadget, 0);
3091 }
3092
3093 return 0;
3094 }
3095
3096 static int omap_udc_resume(struct platform_device *dev)
3097 {
3098 DBG("resume + wakeup/SRP\n");
3099 omap_pullup(&udc->gadget, 1);
3100
3101 /* maybe the host would enumerate us if we nudged it */
3102 msleep(100);
3103 return omap_wakeup(&udc->gadget);
3104 }
3105
3106 /*-------------------------------------------------------------------------*/
3107
3108 static struct platform_driver udc_driver = {
3109 .probe = omap_udc_probe,
3110 .remove = __exit_p(omap_udc_remove),
3111 .suspend = omap_udc_suspend,
3112 .resume = omap_udc_resume,
3113 .driver = {
3114 .owner = THIS_MODULE,
3115 .name = (char *) driver_name,
3116 },
3117 };
3118
3119 static int __init udc_init(void)
3120 {
3121 INFO("%s, version: " DRIVER_VERSION
3122 #ifdef USE_ISO
3123 " (iso)"
3124 #endif
3125 "%s\n", driver_desc,
3126 use_dma ? " (dma)" : "");
3127 return platform_driver_register(&udc_driver);
3128 }
3129 module_init(udc_init);
3130
3131 static void __exit udc_exit(void)
3132 {
3133 platform_driver_unregister(&udc_driver);
3134 }
3135 module_exit(udc_exit);
3136
3137 MODULE_DESCRIPTION(DRIVER_DESC);
3138 MODULE_LICENSE("GPL");
3139 MODULE_ALIAS("platform:omap_udc");
Linux for Ginger Game Console