arch/mips/au1000/common/dbg_io.c

   1 #include <linux/types.h>
   2
   3 #include <asm/mach-au1x00/au1000.h>
   4
   5 #ifdef CONFIG_KGDB
   6
   7 /*
   8  * FIXME the user should be able to select the
   9  * uart to be used for debugging.
  10  */
  11 #define DEBUG_BASE  UART_DEBUG_BASE
  12
  13 #define         UART16550_BAUD_2400             2400
  14 #define         UART16550_BAUD_4800             4800
  15 #define         UART16550_BAUD_9600             9600
  16 #define         UART16550_BAUD_19200            19200
  17 #define         UART16550_BAUD_38400            38400
  18 #define         UART16550_BAUD_57600            57600
  19 #define         UART16550_BAUD_115200           115200
  20
  21 #define         UART16550_PARITY_NONE           0
  22 #define         UART16550_PARITY_ODD            0x08
  23 #define         UART16550_PARITY_EVEN           0x18
  24 #define         UART16550_PARITY_MARK           0x28
  25 #define         UART16550_PARITY_SPACE          0x38
  26
  27 #define         UART16550_DATA_5BIT             0x0
  28 #define         UART16550_DATA_6BIT             0x1
  29 #define         UART16550_DATA_7BIT             0x2
  30 #define         UART16550_DATA_8BIT             0x3
  31
  32 #define         UART16550_STOP_1BIT             0x0
  33 #define         UART16550_STOP_2BIT             0x4
  34
  35
  36 #define UART_RX         0       /* Receive buffer */
  37 #define UART_TX         4       /* Transmit buffer */
  38 #define UART_IER        8       /* Interrupt Enable Register */
  39 #define UART_IIR        0xC     /* Interrupt ID Register */
  40 #define UART_FCR        0x10    /* FIFO Control Register */
  41 #define UART_LCR        0x14    /* Line Control Register */
  42 #define UART_MCR        0x18    /* Modem Control Register */
  43 #define UART_LSR        0x1C    /* Line Status Register */
  44 #define UART_MSR        0x20    /* Modem Status Register */
  45 #define UART_CLK        0x28    /* Baud Rat4e Clock Divider */
  46 #define UART_MOD_CNTRL  0x100   /* Module Control */
  47
  48 /* memory-mapped read/write of the port */
  49 #define UART16550_READ(y)     (au_readl(DEBUG_BASE + y) & 0xff)
  50 #define UART16550_WRITE(y, z) (au_writel(z & 0xff, DEBUG_BASE + y))
  51
  52 extern unsigned long calc_clock(void);
  53
  54 void debugInit(u32 baud, u8 data, u8 parity, u8 stop)
  55 {
  56         if (UART16550_READ(UART_MOD_CNTRL) != 0x3)
  57                 UART16550_WRITE(UART_MOD_CNTRL, 3);
  58         calc_clock();
  59
  60         /* disable interrupts */
  61         UART16550_WRITE(UART_IER, 0);
  62
  63         /* set up baud rate */
  64         {
  65                 u32 divisor;
  66
  67                 /* set divisor */
  68                 divisor = get_au1x00_uart_baud_base() / baud;
  69                 UART16550_WRITE(UART_CLK, divisor & 0xffff);
  70         }
  71
  72         /* set data format */
  73         UART16550_WRITE(UART_LCR, (data | parity | stop));
  74 }
  75
  76 static int remoteDebugInitialized;
  77
  78 u8 getDebugChar(void)
  79 {
  80         if (!remoteDebugInitialized) {
  81                 remoteDebugInitialized = 1;
  82                 debugInit(UART16550_BAUD_115200,
  83                           UART16550_DATA_8BIT,
  84                           UART16550_PARITY_NONE,
  85                           UART16550_STOP_1BIT);
  86         }
  87
  88         while ((UART16550_READ(UART_LSR) & 0x1) == 0);
  89         return UART16550_READ(UART_RX);
  90 }
  91
  92
  93 int putDebugChar(u8 byte)
  94 {
  95         if (!remoteDebugInitialized) {
  96                 remoteDebugInitialized = 1;
  97                 debugInit(UART16550_BAUD_115200,
  98                           UART16550_DATA_8BIT,
  99                           UART16550_PARITY_NONE,
 100                           UART16550_STOP_1BIT);
 101         }
 102
 103         while ((UART16550_READ(UART_LSR) & 0x40) == 0);
 104         UART16550_WRITE(UART_TX, byte);
 105
 106         return 1;
 107 }
 108
 109 #endif