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[MIPS] DBAu1xx0 code style cleanup
[linux-ginger.git] / arch / mips / au1000 / common / irq.c
blob40c6ceceb5f9149f4f5a352c504cb6301b22a6fc
1 /*
2 * Copyright 2001, 2007-2008 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc. <source@mvista.com>
4 *
5 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27 #include <linux/bitops.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/irq.h>
31
32 #include <asm/irq_cpu.h>
33 #include <asm/mipsregs.h>
34 #include <asm/mach-au1x00/au1000.h>
35 #ifdef CONFIG_MIPS_PB1000
36 #include <asm/mach-pb1x00/pb1000.h>
37 #endif
38
39 #define EXT_INTC0_REQ0 2 /* IP 2 */
40 #define EXT_INTC0_REQ1 3 /* IP 3 */
41 #define EXT_INTC1_REQ0 4 /* IP 4 */
42 #define EXT_INTC1_REQ1 5 /* IP 5 */
43 #define MIPS_TIMER_IP 7 /* IP 7 */
44
45 void (*board_init_irq)(void) __initdata = NULL;
46
47 static DEFINE_SPINLOCK(irq_lock);
48
49 #ifdef CONFIG_PM
50
51 /*
52 * Save/restore the interrupt controller state.
53 * Called from the save/restore core registers as part of the
54 * au_sleep function in power.c.....maybe I should just pm_register()
55 * them instead?
56 */
57 static unsigned int sleep_intctl_config0[2];
58 static unsigned int sleep_intctl_config1[2];
59 static unsigned int sleep_intctl_config2[2];
60 static unsigned int sleep_intctl_src[2];
61 static unsigned int sleep_intctl_assign[2];
62 static unsigned int sleep_intctl_wake[2];
63 static unsigned int sleep_intctl_mask[2];
64
65 void save_au1xxx_intctl(void)
66 {
67 sleep_intctl_config0[0] = au_readl(IC0_CFG0RD);
68 sleep_intctl_config1[0] = au_readl(IC0_CFG1RD);
69 sleep_intctl_config2[0] = au_readl(IC0_CFG2RD);
70 sleep_intctl_src[0] = au_readl(IC0_SRCRD);
71 sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD);
72 sleep_intctl_wake[0] = au_readl(IC0_WAKERD);
73 sleep_intctl_mask[0] = au_readl(IC0_MASKRD);
74
75 sleep_intctl_config0[1] = au_readl(IC1_CFG0RD);
76 sleep_intctl_config1[1] = au_readl(IC1_CFG1RD);
77 sleep_intctl_config2[1] = au_readl(IC1_CFG2RD);
78 sleep_intctl_src[1] = au_readl(IC1_SRCRD);
79 sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD);
80 sleep_intctl_wake[1] = au_readl(IC1_WAKERD);
81 sleep_intctl_mask[1] = au_readl(IC1_MASKRD);
82 }
83
84 /*
85 * For most restore operations, we clear the entire register and
86 * then set the bits we found during the save.
87 */
88 void restore_au1xxx_intctl(void)
89 {
90 au_writel(0xffffffff, IC0_MASKCLR); au_sync();
91
92 au_writel(0xffffffff, IC0_CFG0CLR); au_sync();
93 au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync();
94 au_writel(0xffffffff, IC0_CFG1CLR); au_sync();
95 au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync();
96 au_writel(0xffffffff, IC0_CFG2CLR); au_sync();
97 au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync();
98 au_writel(0xffffffff, IC0_SRCCLR); au_sync();
99 au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync();
100 au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync();
101 au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync();
102 au_writel(0xffffffff, IC0_WAKECLR); au_sync();
103 au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync();
104 au_writel(0xffffffff, IC0_RISINGCLR); au_sync();
105 au_writel(0xffffffff, IC0_FALLINGCLR); au_sync();
106 au_writel(0x00000000, IC0_TESTBIT); au_sync();
107
108 au_writel(0xffffffff, IC1_MASKCLR); au_sync();
109
110 au_writel(0xffffffff, IC1_CFG0CLR); au_sync();
111 au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync();
112 au_writel(0xffffffff, IC1_CFG1CLR); au_sync();
113 au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync();
114 au_writel(0xffffffff, IC1_CFG2CLR); au_sync();
115 au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync();
116 au_writel(0xffffffff, IC1_SRCCLR); au_sync();
117 au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync();
118 au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync();
119 au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync();
120 au_writel(0xffffffff, IC1_WAKECLR); au_sync();
121 au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync();
122 au_writel(0xffffffff, IC1_RISINGCLR); au_sync();
123 au_writel(0xffffffff, IC1_FALLINGCLR); au_sync();
124 au_writel(0x00000000, IC1_TESTBIT); au_sync();
125
126 au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync();
127
128 au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync();
129 }
130 #endif /* CONFIG_PM */
131
132
133 inline void local_enable_irq(unsigned int irq_nr)
134 {
135 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
136
137 if (bit >= 32) {
138 au_writel(1 << (bit - 32), IC1_MASKSET);
139 au_writel(1 << (bit - 32), IC1_WAKESET);
140 } else {
141 au_writel(1 << bit, IC0_MASKSET);
142 au_writel(1 << bit, IC0_WAKESET);
143 }
144 au_sync();
145 }
146
147
148 inline void local_disable_irq(unsigned int irq_nr)
149 {
150 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
151
152 if (bit >= 32) {
153 au_writel(1 << (bit - 32), IC1_MASKCLR);
154 au_writel(1 << (bit - 32), IC1_WAKECLR);
155 } else {
156 au_writel(1 << bit, IC0_MASKCLR);
157 au_writel(1 << bit, IC0_WAKECLR);
158 }
159 au_sync();
160 }
161
162
163 static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
164 {
165 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
166
167 if (bit >= 32) {
168 au_writel(1 << (bit - 32), IC1_RISINGCLR);
169 au_writel(1 << (bit - 32), IC1_MASKCLR);
170 } else {
171 au_writel(1 << bit, IC0_RISINGCLR);
172 au_writel(1 << bit, IC0_MASKCLR);
173 }
174 au_sync();
175 }
176
177
178 static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
179 {
180 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
181
182 if (bit >= 32) {
183 au_writel(1 << (bit - 32), IC1_FALLINGCLR);
184 au_writel(1 << (bit - 32), IC1_MASKCLR);
185 } else {
186 au_writel(1 << bit, IC0_FALLINGCLR);
187 au_writel(1 << bit, IC0_MASKCLR);
188 }
189 au_sync();
190 }
191
192
193 static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr)
194 {
195 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
196
197 /*
198 * This may assume that we don't get interrupts from
199 * both edges at once, or if we do, that we don't care.
200 */
201 if (bit >= 32) {
202 au_writel(1 << (bit - 32), IC1_FALLINGCLR);
203 au_writel(1 << (bit - 32), IC1_RISINGCLR);
204 au_writel(1 << (bit - 32), IC1_MASKCLR);
205 } else {
206 au_writel(1 << bit, IC0_FALLINGCLR);
207 au_writel(1 << bit, IC0_RISINGCLR);
208 au_writel(1 << bit, IC0_MASKCLR);
209 }
210 au_sync();
211 }
212
213 static inline void mask_and_ack_level_irq(unsigned int irq_nr)
214 {
215 local_disable_irq(irq_nr);
216 au_sync();
217 #if defined(CONFIG_MIPS_PB1000)
218 if (irq_nr == AU1000_GPIO_15) {
219 au_writel(0x8000, PB1000_MDR); /* ack int */
220 au_sync();
221 }
222 #endif
223 }
224
225 static void end_irq(unsigned int irq_nr)
226 {
227 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
228 local_enable_irq(irq_nr);
229
230 #if defined(CONFIG_MIPS_PB1000)
231 if (irq_nr == AU1000_GPIO_15) {
232 au_writel(0x4000, PB1000_MDR); /* enable int */
233 au_sync();
234 }
235 #endif
236 }
237
238 unsigned long save_local_and_disable(int controller)
239 {
240 int i;
241 unsigned long flags, mask;
242
243 spin_lock_irqsave(&irq_lock, flags);
244 if (controller) {
245 mask = au_readl(IC1_MASKSET);
246 for (i = 32; i < 64; i++)
247 local_disable_irq(i);
248 } else {
249 mask = au_readl(IC0_MASKSET);
250 for (i = 0; i < 32; i++)
251 local_disable_irq(i);
252 }
253 spin_unlock_irqrestore(&irq_lock, flags);
254
255 return mask;
256 }
257
258 void restore_local_and_enable(int controller, unsigned long mask)
259 {
260 int i;
261 unsigned long flags, new_mask;
262
263 spin_lock_irqsave(&irq_lock, flags);
264 for (i = 0; i < 32; i++)
265 if (mask & (1 << i)) {
266 if (controller)
267 local_enable_irq(i + 32);
268 else
269 local_enable_irq(i);
270 }
271
272 if (controller)
273 new_mask = au_readl(IC1_MASKSET);
274 else
275 new_mask = au_readl(IC0_MASKSET);
276
277 spin_unlock_irqrestore(&irq_lock, flags);
278 }
279
280
281 static struct irq_chip rise_edge_irq_type = {
282 .name = "Au1000 Rise Edge",
283 .ack = mask_and_ack_rise_edge_irq,
284 .mask = local_disable_irq,
285 .mask_ack = mask_and_ack_rise_edge_irq,
286 .unmask = local_enable_irq,
287 .end = end_irq,
288 };
289
290 static struct irq_chip fall_edge_irq_type = {
291 .name = "Au1000 Fall Edge",
292 .ack = mask_and_ack_fall_edge_irq,
293 .mask = local_disable_irq,
294 .mask_ack = mask_and_ack_fall_edge_irq,
295 .unmask = local_enable_irq,
296 .end = end_irq,
297 };
298
299 static struct irq_chip either_edge_irq_type = {
300 .name = "Au1000 Rise or Fall Edge",
301 .ack = mask_and_ack_either_edge_irq,
302 .mask = local_disable_irq,
303 .mask_ack = mask_and_ack_either_edge_irq,
304 .unmask = local_enable_irq,
305 .end = end_irq,
306 };
307
308 static struct irq_chip level_irq_type = {
309 .name = "Au1000 Level",
310 .ack = mask_and_ack_level_irq,
311 .mask = local_disable_irq,
312 .mask_ack = mask_and_ack_level_irq,
313 .unmask = local_enable_irq,
314 .end = end_irq,
315 };
316
317 static void __init setup_local_irq(unsigned int irq_nr, int type, int int_req)
318 {
319 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
320
321 if (irq_nr > AU1000_MAX_INTR)
322 return;
323
324 /* Config2[n], Config1[n], Config0[n] */
325 if (bit >= 32) {
326 switch (type) {
327 case INTC_INT_RISE_EDGE: /* 0:0:1 */
328 au_writel(1 << (bit - 32), IC1_CFG2CLR);
329 au_writel(1 << (bit - 32), IC1_CFG1CLR);
330 au_writel(1 << (bit - 32), IC1_CFG0SET);
331 set_irq_chip(irq_nr, &rise_edge_irq_type);
332 break;
333 case INTC_INT_FALL_EDGE: /* 0:1:0 */
334 au_writel(1 << (bit - 32), IC1_CFG2CLR);
335 au_writel(1 << (bit - 32), IC1_CFG1SET);
336 au_writel(1 << (bit - 32), IC1_CFG0CLR);
337 set_irq_chip(irq_nr, &fall_edge_irq_type);
338 break;
339 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
340 au_writel(1 << (bit - 32), IC1_CFG2CLR);
341 au_writel(1 << (bit - 32), IC1_CFG1SET);
342 au_writel(1 << (bit - 32), IC1_CFG0SET);
343 set_irq_chip(irq_nr, &either_edge_irq_type);
344 break;
345 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
346 au_writel(1 << (bit - 32), IC1_CFG2SET);
347 au_writel(1 << (bit - 32), IC1_CFG1CLR);
348 au_writel(1 << (bit - 32), IC1_CFG0SET);
349 set_irq_chip(irq_nr, &level_irq_type);
350 break;
351 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
352 au_writel(1 << (bit - 32), IC1_CFG2SET);
353 au_writel(1 << (bit - 32), IC1_CFG1SET);
354 au_writel(1 << (bit - 32), IC1_CFG0CLR);
355 set_irq_chip(irq_nr, &level_irq_type);
356 break;
357 case INTC_INT_DISABLED: /* 0:0:0 */
358 au_writel(1 << (bit - 32), IC1_CFG0CLR);
359 au_writel(1 << (bit - 32), IC1_CFG1CLR);
360 au_writel(1 << (bit - 32), IC1_CFG2CLR);
361 break;
362 default: /* disable the interrupt */
363 printk(KERN_WARNING "unexpected int type %d (irq %d)\n",
364 type, irq_nr);
365 au_writel(1 << (bit - 32), IC1_CFG0CLR);
366 au_writel(1 << (bit - 32), IC1_CFG1CLR);
367 au_writel(1 << (bit - 32), IC1_CFG2CLR);
368 return;
369 }
370 if (int_req) /* assign to interrupt request 1 */
371 au_writel(1 << (bit - 32), IC1_ASSIGNCLR);
372 else /* assign to interrupt request 0 */
373 au_writel(1 << (bit - 32), IC1_ASSIGNSET);
374 au_writel(1 << (bit - 32), IC1_SRCSET);
375 au_writel(1 << (bit - 32), IC1_MASKCLR);
376 au_writel(1 << (bit - 32), IC1_WAKECLR);
377 } else {
378 switch (type) {
379 case INTC_INT_RISE_EDGE: /* 0:0:1 */
380 au_writel(1 << bit, IC0_CFG2CLR);
381 au_writel(1 << bit, IC0_CFG1CLR);
382 au_writel(1 << bit, IC0_CFG0SET);
383 set_irq_chip(irq_nr, &rise_edge_irq_type);
384 break;
385 case INTC_INT_FALL_EDGE: /* 0:1:0 */
386 au_writel(1 << bit, IC0_CFG2CLR);
387 au_writel(1 << bit, IC0_CFG1SET);
388 au_writel(1 << bit, IC0_CFG0CLR);
389 set_irq_chip(irq_nr, &fall_edge_irq_type);
390 break;
391 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
392 au_writel(1 << bit, IC0_CFG2CLR);
393 au_writel(1 << bit, IC0_CFG1SET);
394 au_writel(1 << bit, IC0_CFG0SET);
395 set_irq_chip(irq_nr, &either_edge_irq_type);
396 break;
397 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
398 au_writel(1 << bit, IC0_CFG2SET);
399 au_writel(1 << bit, IC0_CFG1CLR);
400 au_writel(1 << bit, IC0_CFG0SET);
401 set_irq_chip(irq_nr, &level_irq_type);
402 break;
403 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
404 au_writel(1 << bit, IC0_CFG2SET);
405 au_writel(1 << bit, IC0_CFG1SET);
406 au_writel(1 << bit, IC0_CFG0CLR);
407 set_irq_chip(irq_nr, &level_irq_type);
408 break;
409 case INTC_INT_DISABLED: /* 0:0:0 */
410 au_writel(1 << bit, IC0_CFG0CLR);
411 au_writel(1 << bit, IC0_CFG1CLR);
412 au_writel(1 << bit, IC0_CFG2CLR);
413 break;
414 default: /* disable the interrupt */
415 printk(KERN_WARNING "unexpected int type %d (irq %d)\n",
416 type, irq_nr);
417 au_writel(1 << bit, IC0_CFG0CLR);
418 au_writel(1 << bit, IC0_CFG1CLR);
419 au_writel(1 << bit, IC0_CFG2CLR);
420 return;
421 }
422 if (int_req) /* assign to interrupt request 1 */
423 au_writel(1 << bit, IC0_ASSIGNCLR);
424 else /* assign to interrupt request 0 */
425 au_writel(1 << bit, IC0_ASSIGNSET);
426 au_writel(1 << bit, IC0_SRCSET);
427 au_writel(1 << bit, IC0_MASKCLR);
428 au_writel(1 << bit, IC0_WAKECLR);
429 }
430 au_sync();
431 }
432
433 /*
434 * Interrupts are nested. Even if an interrupt handler is registered
435 * as "fast", we might get another interrupt before we return from
436 * intcX_reqX_irqdispatch().
437 */
438
439 static void intc0_req0_irqdispatch(void)
440 {
441 static unsigned long intc0_req0;
442 unsigned int bit;
443
444 intc0_req0 |= au_readl(IC0_REQ0INT);
445
446 if (!intc0_req0)
447 return;
448
449 #ifdef AU1000_USB_DEV_REQ_INT
450 /*
451 * Because of the tight timing of SETUP token to reply
452 * transactions, the USB devices-side packet complete
453 * interrupt needs the highest priority.
454 */
455 if ((intc0_req0 & (1 << AU1000_USB_DEV_REQ_INT))) {
456 intc0_req0 &= ~(1 << AU1000_USB_DEV_REQ_INT);
457 do_IRQ(AU1000_USB_DEV_REQ_INT);
458 return;
459 }
460 #endif
461 bit = __ffs(intc0_req0);
462 intc0_req0 &= ~(1 << bit);
463 do_IRQ(AU1000_INTC0_INT_BASE + bit);
464 }
465
466
467 static void intc0_req1_irqdispatch(void)
468 {
469 static unsigned long intc0_req1;
470 unsigned int bit;
471
472 intc0_req1 |= au_readl(IC0_REQ1INT);
473
474 if (!intc0_req1)
475 return;
476
477 bit = __ffs(intc0_req1);
478 intc0_req1 &= ~(1 << bit);
479 do_IRQ(AU1000_INTC0_INT_BASE + bit);
480 }
481
482
483 /*
484 * Interrupt Controller 1:
485 * interrupts 32 - 63
486 */
487 static void intc1_req0_irqdispatch(void)
488 {
489 static unsigned long intc1_req0;
490 unsigned int bit;
491
492 intc1_req0 |= au_readl(IC1_REQ0INT);
493
494 if (!intc1_req0)
495 return;
496
497 bit = __ffs(intc1_req0);
498 intc1_req0 &= ~(1 << bit);
499 do_IRQ(AU1000_INTC1_INT_BASE + bit);
500 }
501
502
503 static void intc1_req1_irqdispatch(void)
504 {
505 static unsigned long intc1_req1;
506 unsigned int bit;
507
508 intc1_req1 |= au_readl(IC1_REQ1INT);
509
510 if (!intc1_req1)
511 return;
512
513 bit = __ffs(intc1_req1);
514 intc1_req1 &= ~(1 << bit);
515 do_IRQ(AU1000_INTC1_INT_BASE + bit);
516 }
517
518 asmlinkage void plat_irq_dispatch(void)
519 {
520 unsigned int pending = read_c0_status() & read_c0_cause();
521
522 if (pending & CAUSEF_IP7)
523 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
524 else if (pending & CAUSEF_IP2)
525 intc0_req0_irqdispatch();
526 else if (pending & CAUSEF_IP3)
527 intc0_req1_irqdispatch();
528 else if (pending & CAUSEF_IP4)
529 intc1_req0_irqdispatch();
530 else if (pending & CAUSEF_IP5)
531 intc1_req1_irqdispatch();
532 else
533 spurious_interrupt();
534 }
535
536 void __init arch_init_irq(void)
537 {
538 int i;
539 struct au1xxx_irqmap *imp;
540 extern struct au1xxx_irqmap au1xxx_irq_map[];
541 extern struct au1xxx_irqmap au1xxx_ic0_map[];
542 extern int au1xxx_nr_irqs;
543 extern int au1xxx_ic0_nr_irqs;
544
545 /*
546 * Initialize interrupt controllers to a safe state.
547 */
548 au_writel(0xffffffff, IC0_CFG0CLR);
549 au_writel(0xffffffff, IC0_CFG1CLR);
550 au_writel(0xffffffff, IC0_CFG2CLR);
551 au_writel(0xffffffff, IC0_MASKCLR);
552 au_writel(0xffffffff, IC0_ASSIGNSET);
553 au_writel(0xffffffff, IC0_WAKECLR);
554 au_writel(0xffffffff, IC0_SRCSET);
555 au_writel(0xffffffff, IC0_FALLINGCLR);
556 au_writel(0xffffffff, IC0_RISINGCLR);
557 au_writel(0x00000000, IC0_TESTBIT);
558
559 au_writel(0xffffffff, IC1_CFG0CLR);
560 au_writel(0xffffffff, IC1_CFG1CLR);
561 au_writel(0xffffffff, IC1_CFG2CLR);
562 au_writel(0xffffffff, IC1_MASKCLR);
563 au_writel(0xffffffff, IC1_ASSIGNSET);
564 au_writel(0xffffffff, IC1_WAKECLR);
565 au_writel(0xffffffff, IC1_SRCSET);
566 au_writel(0xffffffff, IC1_FALLINGCLR);
567 au_writel(0xffffffff, IC1_RISINGCLR);
568 au_writel(0x00000000, IC1_TESTBIT);
569
570 mips_cpu_irq_init();
571
572 /*
573 * Initialize IC0, which is fixed per processor.
574 */
575 imp = au1xxx_ic0_map;
576 for (i = 0; i < au1xxx_ic0_nr_irqs; i++) {
577 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
578 imp++;
579 }
580
581 /*
582 * Now set up the irq mapping for the board.
583 */
584 imp = au1xxx_irq_map;
585 for (i = 0; i < au1xxx_nr_irqs; i++) {
586 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
587 imp++;
588 }
589
590 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4);
591
592 /* Board specific IRQ initialization.
593 */
594 if (board_init_irq)
595 board_init_irq();
596 }
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