arch/arm/plat-omap/sram.c

   1 /*
   2  * linux/arch/arm/plat-omap/sram.c
   3  *
   4  * OMAP SRAM detection and management
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * Copyright (C) 2009 Texas Instruments
  10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16 #undef DEBUG
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/tlb.h>
  24 #include <asm/cacheflush.h>
  25
  26 #include <asm/mach/map.h>
  27
  28 #include <mach/sram.h>
  29 #include <mach/board.h>
  30 #include <mach/cpu.h>
  31
  32 #include <mach/control.h>
  33
  34 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
  35 # include "../mach-omap2/prm.h"
  36 # include "../mach-omap2/cm.h"
  37 # include "../mach-omap2/sdrc.h"
  38 #endif
  39
  40 #define OMAP1_SRAM_PA           0x20000000
  41 #define OMAP1_SRAM_VA           VMALLOC_END
  42 #define OMAP2_SRAM_PA           0x40200000
  43 #define OMAP2_SRAM_PUB_PA       0x4020f800
  44 #define OMAP2_SRAM_VA           0xe3000000
  45 #define OMAP2_SRAM_PUB_VA       (OMAP2_SRAM_VA + 0x800)
  46 #define OMAP3_SRAM_PA           0x40200000
  47 #define OMAP3_SRAM_VA           0xe3000000
  48 #define OMAP3_SRAM_PUB_PA       0x40208000
  49 #define OMAP3_SRAM_PUB_VA       (OMAP3_SRAM_VA + 0x8000)
  50 #define OMAP4_SRAM_PA           0x40200000              /*0x402f0000*/
  51 #define OMAP4_SRAM_VA           0xd7000000              /*0xd70f0000*/
  52
  53 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
  54 #define SRAM_BOOTLOADER_SZ      0x00
  55 #else
  56 #define SRAM_BOOTLOADER_SZ      0x80
  57 #endif
  58
  59 #define OMAP24XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68005048)
  60 #define OMAP24XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68005050)
  61 #define OMAP24XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68005058)
  62
  63 #define OMAP34XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68012848)
  64 #define OMAP34XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68012850)
  65 #define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
  66 #define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
  67 #define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
  68 #define OMAP34XX_VA_CONTROL_STAT        OMAP2_L4_IO_ADDRESS(0x480022F0)
  69
  70 #define GP_DEVICE               0x300
  71
  72 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
  73
  74 static unsigned long omap_sram_start;
  75 static unsigned long omap_sram_base;
  76 static unsigned long omap_sram_size;
  77 static unsigned long omap_sram_ceil;
  78
  79 extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
  80                                          unsigned long sram_vstart,
  81                                          unsigned long sram_size,
  82                                          unsigned long pstart_avail,
  83                                          unsigned long size_avail);
  84
  85 /*
  86  * Depending on the target RAMFS firewall setup, the public usable amount of
  87  * SRAM varies.  The default accessible size for all device types is 2k. A GP
  88  * device allows ARM11 but not other initiators for full size. This
  89  * functionality seems ok until some nice security API happens.
  90  */
  91 static int is_sram_locked(void)
  92 {
  93         int type = 0;
  94
  95         if (cpu_is_omap44xx())
  96                 /* Not yet supported */
  97                 return 0;
  98
  99         if (cpu_is_omap242x())
 100                 type = omap_rev() & OMAP2_DEVICETYPE_MASK;
 101
 102         if (type == GP_DEVICE) {
 103                 /* RAMFW: R/W access to all initiators for all qualifier sets */
 104                 if (cpu_is_omap242x()) {
 105                         __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
 106                         __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
 107                         __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
 108                 }
 109                 if (cpu_is_omap34xx()) {
 110                         __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
 111                         __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
 112                         __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
 113                         __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
 114                         __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
 115                 }
 116                 return 0;
 117         } else
 118                 return 1; /* assume locked with no PPA or security driver */
 119 }
 120
 121 /*
 122  * The amount of SRAM depends on the core type.
 123  * Note that we cannot try to test for SRAM here because writes
 124  * to secure SRAM will hang the system. Also the SRAM is not
 125  * yet mapped at this point.
 126  */
 127 void __init omap_detect_sram(void)
 128 {
 129         unsigned long reserved;
 130
 131         if (cpu_class_is_omap2()) {
 132                 if (is_sram_locked()) {
 133                         if (cpu_is_omap34xx()) {
 134                                 omap_sram_base = OMAP3_SRAM_PUB_VA;
 135                                 omap_sram_start = OMAP3_SRAM_PUB_PA;
 136                                 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
 137                                     (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
 138                                         omap_sram_size = 0x7000; /* 28K */
 139                                 } else {
 140                                         omap_sram_size = 0x8000; /* 32K */
 141                                 }
 142                         } else {
 143                                 omap_sram_base = OMAP2_SRAM_PUB_VA;
 144                                 omap_sram_start = OMAP2_SRAM_PUB_PA;
 145                                 omap_sram_size = 0x800; /* 2K */
 146                         }
 147                 } else {
 148                         if (cpu_is_omap34xx()) {
 149                                 omap_sram_base = OMAP3_SRAM_VA;
 150                                 omap_sram_start = OMAP3_SRAM_PA;
 151                                 omap_sram_size = 0x10000; /* 64K */
 152                         } else if (cpu_is_omap44xx()) {
 153                                 omap_sram_base = OMAP4_SRAM_VA;
 154                                 omap_sram_start = OMAP4_SRAM_PA;
 155                                 omap_sram_size = 0x8000; /* 32K */
 156                         } else {
 157                                 omap_sram_base = OMAP2_SRAM_VA;
 158                                 omap_sram_start = OMAP2_SRAM_PA;
 159                                 if (cpu_is_omap242x())
 160                                         omap_sram_size = 0xa0000; /* 640K */
 161                                 else if (cpu_is_omap243x())
 162                                         omap_sram_size = 0x10000; /* 64K */
 163                         }
 164                 }
 165         } else {
 166                 omap_sram_base = OMAP1_SRAM_VA;
 167                 omap_sram_start = OMAP1_SRAM_PA;
 168
 169                 if (cpu_is_omap7xx())
 170                         omap_sram_size = 0x32000;       /* 200K */
 171                 else if (cpu_is_omap15xx())
 172                         omap_sram_size = 0x30000;       /* 192K */
 173                 else if (cpu_is_omap1610() || cpu_is_omap1621() ||
 174                      cpu_is_omap1710())
 175                         omap_sram_size = 0x4000;        /* 16K */
 176                 else if (cpu_is_omap1611())
 177                         omap_sram_size = 0x3e800;       /* 250K */
 178                 else {
 179                         printk(KERN_ERR "Could not detect SRAM size\n");
 180                         omap_sram_size = 0x4000;
 181                 }
 182         }
 183         reserved = omapfb_reserve_sram(omap_sram_start, omap_sram_base,
 184                                        omap_sram_size,
 185                                        omap_sram_start + SRAM_BOOTLOADER_SZ,
 186                                        omap_sram_size - SRAM_BOOTLOADER_SZ);
 187         omap_sram_size -= reserved;
 188         omap_sram_ceil = omap_sram_base + omap_sram_size;
 189 }
 190
 191 static struct map_desc omap_sram_io_desc[] __initdata = {
 192         {       /* .length gets filled in at runtime */
 193                 .virtual        = OMAP1_SRAM_VA,
 194                 .pfn            = __phys_to_pfn(OMAP1_SRAM_PA),
 195                 .type           = MT_MEMORY
 196         }
 197 };
 198
 199 /*
 200  * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
 201  */
 202 void __init omap_map_sram(void)
 203 {
 204         unsigned long base;
 205
 206         if (omap_sram_size == 0)
 207                 return;
 208
 209         if (cpu_is_omap24xx()) {
 210                 omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA;
 211
 212                 base = OMAP2_SRAM_PA;
 213                 base = ROUND_DOWN(base, PAGE_SIZE);
 214                 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
 215         }
 216
 217         if (cpu_is_omap34xx()) {
 218                 omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA;
 219                 base = OMAP3_SRAM_PA;
 220                 base = ROUND_DOWN(base, PAGE_SIZE);
 221                 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
 222
 223                 /*
 224                  * SRAM must be marked as non-cached on OMAP3 since the
 225                  * CORE DPLL M2 divider change code (in SRAM) runs with the
 226                  * SDRAM controller disabled, and if it is marked cached,
 227                  * the ARM may attempt to write cache lines back to SDRAM
 228                  * which will cause the system to hang.
 229                  */
 230                 omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
 231         }
 232
 233         if (cpu_is_omap44xx()) {
 234                 omap_sram_io_desc[0].virtual = OMAP4_SRAM_VA;
 235                 base = OMAP4_SRAM_PA;
 236                 base = ROUND_DOWN(base, PAGE_SIZE);
 237                 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
 238         }
 239         omap_sram_io_desc[0].length = 1024 * 1024;      /* Use section desc */
 240         iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
 241
 242         printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
 243         __pfn_to_phys(omap_sram_io_desc[0].pfn),
 244         omap_sram_io_desc[0].virtual,
 245                omap_sram_io_desc[0].length);
 246
 247         /*
 248          * Normally devicemaps_init() would flush caches and tlb after
 249          * mdesc->map_io(), but since we're called from map_io(), we
 250          * must do it here.
 251          */
 252         local_flush_tlb_all();
 253         flush_cache_all();
 254
 255         /*
 256          * Looks like we need to preserve some bootloader code at the
 257          * beginning of SRAM for jumping to flash for reboot to work...
 258          */
 259         memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
 260                omap_sram_size - SRAM_BOOTLOADER_SZ);
 261 }
 262
 263 void * omap_sram_push(void * start, unsigned long size)
 264 {
 265         if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) {
 266                 printk(KERN_ERR "Not enough space in SRAM\n");
 267                 return NULL;
 268         }
 269
 270         omap_sram_ceil -= size;
 271         omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
 272         memcpy((void *)omap_sram_ceil, start, size);
 273         flush_icache_range((unsigned long)omap_sram_ceil,
 274                 (unsigned long)(omap_sram_ceil + size));
 275
 276         return (void *)omap_sram_ceil;
 277 }
 278
 279 #ifdef CONFIG_ARCH_OMAP1
 280
 281 static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
 282
 283 void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
 284 {
 285         BUG_ON(!_omap_sram_reprogram_clock);
 286         _omap_sram_reprogram_clock(dpllctl, ckctl);
 287 }
 288
 289 int __init omap1_sram_init(void)
 290 {
 291         _omap_sram_reprogram_clock =
 292                         omap_sram_push(omap1_sram_reprogram_clock,
 293                                         omap1_sram_reprogram_clock_sz);
 294
 295         return 0;
 296 }
 297
 298 #else
 299 #define omap1_sram_init()       do {} while (0)
 300 #endif
 301
 302 #if defined(CONFIG_ARCH_OMAP2)
 303
 304 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 305                               u32 base_cs, u32 force_unlock);
 306
 307 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 308                    u32 base_cs, u32 force_unlock)
 309 {
 310         BUG_ON(!_omap2_sram_ddr_init);
 311         _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
 312                              base_cs, force_unlock);
 313 }
 314
 315 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
 316                                           u32 mem_type);
 317
 318 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
 319 {
 320         BUG_ON(!_omap2_sram_reprogram_sdrc);
 321         _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
 322 }
 323
 324 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 325
 326 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
 327 {
 328         BUG_ON(!_omap2_set_prcm);
 329         return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
 330 }
 331 #endif
 332
 333 #ifdef CONFIG_ARCH_OMAP2420
 334 int __init omap242x_sram_init(void)
 335 {
 336         _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
 337                                         omap242x_sram_ddr_init_sz);
 338
 339         _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
 340                                             omap242x_sram_reprogram_sdrc_sz);
 341
 342         _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
 343                                          omap242x_sram_set_prcm_sz);
 344
 345         return 0;
 346 }
 347 #else
 348 static inline int omap242x_sram_init(void)
 349 {
 350         return 0;
 351 }
 352 #endif
 353
 354 #ifdef CONFIG_ARCH_OMAP2430
 355 int __init omap243x_sram_init(void)
 356 {
 357         _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
 358                                         omap243x_sram_ddr_init_sz);
 359
 360         _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
 361                                             omap243x_sram_reprogram_sdrc_sz);
 362
 363         _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
 364                                          omap243x_sram_set_prcm_sz);
 365
 366         return 0;
 367 }
 368 #else
 369 static inline int omap243x_sram_init(void)
 370 {
 371         return 0;
 372 }
 373 #endif
 374
 375 #ifdef CONFIG_ARCH_OMAP3
 376
 377 static u32 (*_omap3_sram_configure_core_dpll)(
 378                         u32 m2, u32 unlock_dll, u32 f, u32 inc,
 379                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 380                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 381                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 382                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 383
 384 u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
 385                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 386                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 387                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 388                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
 389 {
 390         BUG_ON(!_omap3_sram_configure_core_dpll);
 391         return _omap3_sram_configure_core_dpll(
 392                         m2, unlock_dll, f, inc,
 393                         sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
 394                         sdrc_actim_ctrl_b_0, sdrc_mr_0,
 395                         sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
 396                         sdrc_actim_ctrl_b_1, sdrc_mr_1);
 397 }
 398
 399 /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
 400 void restore_sram_functions(void)
 401 {
 402         omap_sram_ceil = omap_sram_base + omap_sram_size;
 403
 404         _omap3_sram_configure_core_dpll =
 405                 omap_sram_push(omap3_sram_configure_core_dpll,
 406                                omap3_sram_configure_core_dpll_sz);
 407 }
 408
 409 int __init omap34xx_sram_init(void)
 410 {
 411         _omap3_sram_configure_core_dpll =
 412                 omap_sram_push(omap3_sram_configure_core_dpll,
 413                                omap3_sram_configure_core_dpll_sz);
 414
 415         return 0;
 416 }
 417 #else
 418 static inline int omap34xx_sram_init(void)
 419 {
 420         return 0;
 421 }
 422 #endif
 423
 424 int __init omap_sram_init(void)
 425 {
 426         omap_detect_sram();
 427         omap_map_sram();
 428
 429         if (!(cpu_class_is_omap2()))
 430                 omap1_sram_init();
 431         else if (cpu_is_omap242x())
 432                 omap242x_sram_init();
 433         else if (cpu_is_omap2430())
 434                 omap243x_sram_init();
 435         else if (cpu_is_omap34xx())
 436                 omap34xx_sram_init();
 437         else if (cpu_is_omap44xx())
 438                 omap34xx_sram_init(); /* FIXME: */
 439
 440         return 0;
 441 }