arch/x86/pci/visws.c

   1 /*
   2  *      Low-Level PCI Support for SGI Visual Workstation
   3  *
   4  *      (c) 1999--2000 Martin Mares <mj@ucw.cz>
   5  */
   6
   7 #include <linux/kernel.h>
   8 #include <linux/pci.h>
   9 #include <linux/init.h>
  10
  11 #include "cobalt.h"
  12 #include "lithium.h"
  13
  14 #include "pci.h"
  15
  16 static int pci_visws_enable_irq(struct pci_dev *dev) { return 0; }
  17 static void pci_visws_disable_irq(struct pci_dev *dev) { }
  18
  19 int (*pcibios_enable_irq)(struct pci_dev *dev) = &pci_visws_enable_irq;
  20 void (*pcibios_disable_irq)(struct pci_dev *dev) = &pci_visws_disable_irq;
  21
  22 void __init pcibios_penalize_isa_irq(int irq, int active) {}
  23
  24
  25 unsigned int pci_bus0, pci_bus1;
  26
  27 static inline u8 bridge_swizzle(u8 pin, u8 slot)
  28 {
  29         return (((pin - 1) + slot) % 4) + 1;
  30 }
  31
  32 static u8 __init visws_swizzle(struct pci_dev *dev, u8 *pinp)
  33 {
  34         u8 pin = *pinp;
  35
  36         while (dev->bus->self) {        /* Move up the chain of bridges. */
  37                 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
  38                 dev = dev->bus->self;
  39         }
  40         *pinp = pin;
  41
  42         return PCI_SLOT(dev->devfn);
  43 }
  44
  45 static int __init visws_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
  46 {
  47         int irq, bus = dev->bus->number;
  48
  49         pin--;
  50
  51         /* Nothing useful at PIIX4 pin 1 */
  52         if (bus == pci_bus0 && slot == 4 && pin == 0)
  53                 return -1;
  54
  55         /* PIIX4 USB is on Bus 0, Slot 4, Line 3 */
  56         if (bus == pci_bus0 && slot == 4 && pin == 3) {
  57                 irq = CO_IRQ(CO_APIC_PIIX4_USB);
  58                 goto out;
  59         }
  60
  61         /* First pin spread down 1 APIC entry per slot */
  62         if (pin == 0) {
  63                 irq = CO_IRQ((bus == pci_bus0 ? CO_APIC_PCIB_BASE0 :
  64                                                 CO_APIC_PCIA_BASE0) + slot);
  65                 goto out;
  66         }
  67
  68         /* lines 1,2,3 from any slot is shared in this twirly pattern */
  69         if (bus == pci_bus1) {
  70                 /* lines 1-3 from devices 0 1 rotate over 2 apic entries */
  71                 irq = CO_IRQ(CO_APIC_PCIA_BASE123 + ((slot + (pin - 1)) % 2));
  72         } else { /* bus == pci_bus0 */
  73                 /* lines 1-3 from devices 0-3 rotate over 3 apic entries */
  74                 if (slot == 0)
  75                         slot = 3; /* same pattern */
  76                 irq = CO_IRQ(CO_APIC_PCIA_BASE123 + ((3 - slot) + (pin - 1) % 3));
  77         }
  78 out:
  79         printk(KERN_DEBUG "PCI: Bus %d Slot %d Line %d -> IRQ %d\n", bus, slot, pin, irq);
  80         return irq;
  81 }
  82
  83 void __init pcibios_update_irq(struct pci_dev *dev, int irq)
  84 {
  85         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
  86 }
  87
  88 static int __init pcibios_init(void)
  89 {
  90         /* The VISWS supports configuration access type 1 only */
  91         pci_probe = (pci_probe | PCI_PROBE_CONF1) &
  92                     ~(PCI_PROBE_BIOS | PCI_PROBE_CONF2);
  93
  94         pci_bus0 = li_pcib_read16(LI_PCI_BUSNUM) & 0xff;
  95         pci_bus1 = li_pcia_read16(LI_PCI_BUSNUM) & 0xff;
  96
  97         printk(KERN_INFO "PCI: Lithium bridge A bus: %u, "
  98                 "bridge B (PIIX4) bus: %u\n", pci_bus1, pci_bus0);
  99
 100         raw_pci_ops = &pci_direct_conf1;
 101         pci_scan_bus_with_sysdata(pci_bus0);
 102         pci_scan_bus_with_sysdata(pci_bus1);
 103         pci_fixup_irqs(visws_swizzle, visws_map_irq);
 104         pcibios_resource_survey();
 105         return 0;
 106 }
 107
 108 subsys_initcall(pcibios_init);