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OMAP3: PM: Added resource refresh to OPP unlock requests
[linux-ginger.git] / arch / arm / mach-omap2 / pm-debug.c
blob767ebbc9dfc34f353ab928b10c76b29f2e041190
1 /*
2 * OMAP Power Management debug routines
3 *
4 * Copyright (C) 2005 Texas Instruments, Inc.
5 * Copyright (C) 2006-2008 Nokia Corporation
6 *
7 * Written by:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Tony Lindgren
10 * Juha Yrjola
11 * Amit Kucheria <amit.kucheria@nokia.com>
12 * Igor Stoppa <igor.stoppa@nokia.com>
13 * Jouni Hogander
14 *
15 * Based on pm.c for omap2
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22 #include <linux/kernel.h>
23 #include <linux/sched.h>
24 #include <linux/clk.h>
25 #include <linux/err.h>
26 #include <linux/io.h>
27 #include <linux/module.h>
28
29 #include <plat/clock.h>
30 #include <plat/board.h>
31 #include <plat/powerdomain.h>
32 #include <plat/clockdomain.h>
33
34 #include "prm.h"
35 #include "cm.h"
36 #include "pm.h"
37 #include "prm-regbits-34xx.h"
38
39 int omap2_pm_debug;
40
41 #define DUMP_PRM_MOD_REG(mod, reg) \
42 regs[reg_count].name = #mod "." #reg; \
43 regs[reg_count++].val = prm_read_mod_reg(mod, reg)
44 #define DUMP_CM_MOD_REG(mod, reg) \
45 regs[reg_count].name = #mod "." #reg; \
46 regs[reg_count++].val = cm_read_mod_reg(mod, reg)
47 #define DUMP_PRM_REG(reg) \
48 regs[reg_count].name = #reg; \
49 regs[reg_count++].val = __raw_readl(reg)
50 #define DUMP_CM_REG(reg) \
51 regs[reg_count].name = #reg; \
52 regs[reg_count++].val = __raw_readl(reg)
53 #define DUMP_INTC_REG(reg, off) \
54 regs[reg_count].name = #reg; \
55 regs[reg_count++].val = \
56 __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off)))
57
58 static int __init pm_dbg_init(void);
59
60 void omap2_pm_dump(int mode, int resume, unsigned int us)
61 {
62 struct reg {
63 const char *name;
64 u32 val;
65 } regs[32];
66 int reg_count = 0, i;
67 const char *s1 = NULL, *s2 = NULL;
68
69 if (!resume) {
70 #if 0
71 /* MPU */
72 DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
73 DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL);
74 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL);
75 DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST);
76 DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
77 #endif
78 #if 0
79 /* INTC */
80 DUMP_INTC_REG(INTC_MIR0, 0x0084);
81 DUMP_INTC_REG(INTC_MIR1, 0x00a4);
82 DUMP_INTC_REG(INTC_MIR2, 0x00c4);
83 #endif
84 #if 0
85 DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
86 if (cpu_is_omap24xx()) {
87 DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2);
88 DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
89 OMAP2_PRCM_CLKEMUL_CTRL_OFFSET);
90 DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
91 OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
92 }
93 DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
94 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
95 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
96 DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
97 DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN);
98 DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
99 DUMP_PRM_MOD_REG(CORE_MOD, PM_PWSTST);
100 #endif
101 #if 0
102 /* DSP */
103 if (cpu_is_omap24xx()) {
104 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
105 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
106 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
107 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
108 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
109 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
110 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL);
111 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST);
112 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL);
113 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST);
114 }
115 #endif
116 } else {
117 DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
118 if (cpu_is_omap24xx())
119 DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2);
120 DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
121 DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
122 #if 1
123 DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
124 DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
125 DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
126 #endif
127 }
128
129 switch (mode) {
130 case 0:
131 s1 = "full";
132 s2 = "retention";
133 break;
134 case 1:
135 s1 = "MPU";
136 s2 = "retention";
137 break;
138 case 2:
139 s1 = "MPU";
140 s2 = "idle";
141 break;
142 }
143
144 if (!resume)
145 #ifdef CONFIG_NO_HZ
146 printk(KERN_INFO
147 "--- Going to %s %s (next timer after %u ms)\n", s1, s2,
148 jiffies_to_msecs(get_next_timer_interrupt(jiffies) -
149 jiffies));
150 #else
151 printk(KERN_INFO "--- Going to %s %s\n", s1, s2);
152 #endif
153 else
154 printk(KERN_INFO "--- Woke up (slept for %u.%03u ms)\n",
155 us / 1000, us % 1000);
156
157 for (i = 0; i < reg_count; i++)
158 printk(KERN_INFO "%-20s: 0x%08x\n", regs[i].name, regs[i].val);
159 }
160
161 #ifdef CONFIG_DEBUG_FS
162 #include <linux/debugfs.h>
163 #include <linux/seq_file.h>
164
165 static void pm_dbg_regset_store(u32 *ptr);
166
167 struct dentry *pm_dbg_dir;
168
169 static int pm_dbg_init_done;
170
171 enum {
172 DEBUG_FILE_COUNTERS = 0,
173 DEBUG_FILE_TIMERS,
174 };
175
176 struct pm_module_def {
177 char name[8]; /* Name of the module */
178 short type; /* CM or PRM */
179 unsigned short offset;
180 int low; /* First register address on this module */
181 int high; /* Last register address on this module */
182 };
183
184 #define MOD_CM 0
185 #define MOD_PRM 1
186
187 static const struct pm_module_def *pm_dbg_reg_modules;
188 static const struct pm_module_def omap3_pm_reg_modules[] = {
189 { "IVA2", MOD_CM, OMAP3430_IVA2_MOD, 0, 0x4c },
190 { "OCP", MOD_CM, OCP_MOD, 0, 0x10 },
191 { "MPU", MOD_CM, MPU_MOD, 4, 0x4c },
192 { "CORE", MOD_CM, CORE_MOD, 0, 0x4c },
193 { "SGX", MOD_CM, OMAP3430ES2_SGX_MOD, 0, 0x4c },
194 { "WKUP", MOD_CM, WKUP_MOD, 0, 0x40 },
195 { "CCR", MOD_CM, PLL_MOD, 0, 0x70 },
196 { "DSS", MOD_CM, OMAP3430_DSS_MOD, 0, 0x4c },
197 { "CAM", MOD_CM, OMAP3430_CAM_MOD, 0, 0x4c },
198 { "PER", MOD_CM, OMAP3430_PER_MOD, 0, 0x4c },
199 { "EMU", MOD_CM, OMAP3430_EMU_MOD, 0x40, 0x54 },
200 { "NEON", MOD_CM, OMAP3430_NEON_MOD, 0x20, 0x48 },
201 { "USB", MOD_CM, OMAP3430ES2_USBHOST_MOD, 0, 0x4c },
202
203 { "IVA2", MOD_PRM, OMAP3430_IVA2_MOD, 0x50, 0xfc },
204 { "OCP", MOD_PRM, OCP_MOD, 4, 0x1c },
205 { "MPU", MOD_PRM, MPU_MOD, 0x58, 0xe8 },
206 { "CORE", MOD_PRM, CORE_MOD, 0x58, 0xf8 },
207 { "SGX", MOD_PRM, OMAP3430ES2_SGX_MOD, 0x58, 0xe8 },
208 { "WKUP", MOD_PRM, WKUP_MOD, 0xa0, 0xb0 },
209 { "CCR", MOD_PRM, PLL_MOD, 0x40, 0x70 },
210 { "DSS", MOD_PRM, OMAP3430_DSS_MOD, 0x58, 0xe8 },
211 { "CAM", MOD_PRM, OMAP3430_CAM_MOD, 0x58, 0xe8 },
212 { "PER", MOD_PRM, OMAP3430_PER_MOD, 0x58, 0xe8 },
213 { "EMU", MOD_PRM, OMAP3430_EMU_MOD, 0x58, 0xe4 },
214 { "GLBL", MOD_PRM, OMAP3430_GR_MOD, 0x20, 0xe4 },
215 { "NEON", MOD_PRM, OMAP3430_NEON_MOD, 0x58, 0xe8 },
216 { "USB", MOD_PRM, OMAP3430ES2_USBHOST_MOD, 0x58, 0xe8 },
217 { "", 0, 0, 0, 0 },
218 };
219
220 #define PM_DBG_MAX_REG_SETS 4
221
222 static void *pm_dbg_reg_set[PM_DBG_MAX_REG_SETS];
223
224 static int pm_dbg_get_regset_size(void)
225 {
226 static int regset_size;
227
228 if (regset_size == 0) {
229 int i = 0;
230
231 while (pm_dbg_reg_modules[i].name[0] != 0) {
232 regset_size += pm_dbg_reg_modules[i].high +
233 4 - pm_dbg_reg_modules[i].low;
234 i++;
235 }
236 }
237 return regset_size;
238 }
239
240 static int pm_dbg_show_regs(struct seq_file *s, void *unused)
241 {
242 int i, j;
243 unsigned long val;
244 int reg_set = (int)s->private;
245 u32 *ptr;
246 void *store = NULL;
247 int regs;
248 int linefeed;
249
250 if (reg_set == 0) {
251 store = kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
252 ptr = store;
253 pm_dbg_regset_store(ptr);
254 } else {
255 ptr = pm_dbg_reg_set[reg_set - 1];
256 }
257
258 i = 0;
259
260 while (pm_dbg_reg_modules[i].name[0] != 0) {
261 regs = 0;
262 linefeed = 0;
263 if (pm_dbg_reg_modules[i].type == MOD_CM)
264 seq_printf(s, "MOD: CM_%s (%08x)\n",
265 pm_dbg_reg_modules[i].name,
266 (u32)(OMAP3430_CM_BASE +
267 pm_dbg_reg_modules[i].offset));
268 else
269 seq_printf(s, "MOD: PRM_%s (%08x)\n",
270 pm_dbg_reg_modules[i].name,
271 (u32)(OMAP3430_PRM_BASE +
272 pm_dbg_reg_modules[i].offset));
273
274 for (j = pm_dbg_reg_modules[i].low;
275 j <= pm_dbg_reg_modules[i].high; j += 4) {
276 val = *(ptr++);
277 if (val != 0) {
278 regs++;
279 if (linefeed) {
280 seq_printf(s, "\n");
281 linefeed = 0;
282 }
283 seq_printf(s, " %02x => %08lx", j, val);
284 if (regs % 4 == 0)
285 linefeed = 1;
286 }
287 }
288 seq_printf(s, "\n");
289 i++;
290 }
291
292 if (store != NULL)
293 kfree(store);
294
295 return 0;
296 }
297
298 static void pm_dbg_regset_store(u32 *ptr)
299 {
300 int i, j;
301 u32 val;
302
303 i = 0;
304
305 while (pm_dbg_reg_modules[i].name[0] != 0) {
306 for (j = pm_dbg_reg_modules[i].low;
307 j <= pm_dbg_reg_modules[i].high; j += 4) {
308 if (pm_dbg_reg_modules[i].type == MOD_CM)
309 val = cm_read_mod_reg(
310 pm_dbg_reg_modules[i].offset, j);
311 else
312 val = prm_read_mod_reg(
313 pm_dbg_reg_modules[i].offset, j);
314 *(ptr++) = val;
315 }
316 i++;
317 }
318 }
319
320 int pm_dbg_regset_save(int reg_set)
321 {
322 if (pm_dbg_reg_set[reg_set-1] == NULL)
323 return -EINVAL;
324
325 pm_dbg_regset_store(pm_dbg_reg_set[reg_set-1]);
326
327 return 0;
328 }
329
330 static const char pwrdm_state_names[][4] = {
331 "OFF",
332 "RET",
333 "INA",
334 "ON"
335 };
336
337 void pm_dbg_update_time(struct powerdomain *pwrdm, int prev)
338 {
339 s64 t;
340
341 if (!pm_dbg_init_done)
342 return ;
343
344 /* Update timer for previous state */
345 t = sched_clock();
346
347 pwrdm->state_timer[prev] += t - pwrdm->timer;
348
349 pwrdm->timer = t;
350 }
351
352 static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user)
353 {
354 struct seq_file *s = (struct seq_file *)user;
355
356 if (strcmp(clkdm->name, "emu_clkdm") == 0 ||
357 strcmp(clkdm->name, "wkup_clkdm") == 0 ||
358 strncmp(clkdm->name, "dpll", 4) == 0)
359 return 0;
360
361 seq_printf(s, "%s->%s (%d)", clkdm->name,
362 clkdm->pwrdm.ptr->name,
363 atomic_read(&clkdm->usecount));
364 seq_printf(s, "\n");
365
366 return 0;
367 }
368
369 static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user)
370 {
371 struct seq_file *s = (struct seq_file *)user;
372 int i;
373
374 if (strcmp(pwrdm->name, "emu_pwrdm") == 0 ||
375 strcmp(pwrdm->name, "wkup_pwrdm") == 0 ||
376 strncmp(pwrdm->name, "dpll", 4) == 0)
377 return 0;
378
379 if (pwrdm->state != pwrdm_read_pwrst(pwrdm))
380 printk(KERN_ERR "pwrdm state mismatch(%s) %d != %d\n",
381 pwrdm->name, pwrdm->state, pwrdm_read_pwrst(pwrdm));
382
383 seq_printf(s, "%s (%s)", pwrdm->name,
384 pwrdm_state_names[pwrdm->state]);
385 for (i = 0; i < 4; i++)
386 seq_printf(s, ",%s:%d", pwrdm_state_names[i],
387 pwrdm->state_counter[i]);
388
389 seq_printf(s, "\n");
390
391 return 0;
392 }
393
394 static int pwrdm_dbg_show_timer(struct powerdomain *pwrdm, void *user)
395 {
396 struct seq_file *s = (struct seq_file *)user;
397 int i;
398
399 if (strcmp(pwrdm->name, "emu_pwrdm") == 0 ||
400 strcmp(pwrdm->name, "wkup_pwrdm") == 0 ||
401 strncmp(pwrdm->name, "dpll", 4) == 0)
402 return 0;
403
404 pwrdm_state_switch(pwrdm);
405
406 seq_printf(s, "%s (%s)", pwrdm->name,
407 pwrdm_state_names[pwrdm->state]);
408
409 for (i = 0; i < 4; i++)
410 seq_printf(s, ",%s:%lld", pwrdm_state_names[i],
411 pwrdm->state_timer[i]);
412
413 seq_printf(s, "\n");
414 return 0;
415 }
416
417 static int pm_dbg_show_counters(struct seq_file *s, void *unused)
418 {
419 pwrdm_for_each(pwrdm_dbg_show_counter, s);
420 clkdm_for_each(clkdm_dbg_show_counter, s);
421
422 return 0;
423 }
424
425 static int pm_dbg_show_timers(struct seq_file *s, void *unused)
426 {
427 pwrdm_for_each(pwrdm_dbg_show_timer, s);
428 return 0;
429 }
430
431 static int pm_dbg_open(struct inode *inode, struct file *file)
432 {
433 switch ((int)inode->i_private) {
434 case DEBUG_FILE_COUNTERS:
435 return single_open(file, pm_dbg_show_counters,
436 &inode->i_private);
437 case DEBUG_FILE_TIMERS:
438 default:
439 return single_open(file, pm_dbg_show_timers,
440 &inode->i_private);
441 };
442 }
443
444 static int pm_dbg_reg_open(struct inode *inode, struct file *file)
445 {
446 return single_open(file, pm_dbg_show_regs, inode->i_private);
447 }
448
449 static const struct file_operations debug_fops = {
450 .open = pm_dbg_open,
451 .read = seq_read,
452 .llseek = seq_lseek,
453 .release = single_release,
454 };
455
456 static const struct file_operations debug_reg_fops = {
457 .open = pm_dbg_reg_open,
458 .read = seq_read,
459 .llseek = seq_lseek,
460 .release = single_release,
461 };
462
463 int pm_dbg_regset_init(int reg_set)
464 {
465 char name[2];
466
467 if (!pm_dbg_init_done)
468 pm_dbg_init();
469
470 if (reg_set < 1 || reg_set > PM_DBG_MAX_REG_SETS ||
471 pm_dbg_reg_set[reg_set-1] != NULL)
472 return -EINVAL;
473
474 pm_dbg_reg_set[reg_set-1] =
475 kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
476
477 if (pm_dbg_reg_set[reg_set-1] == NULL)
478 return -ENOMEM;
479
480 if (pm_dbg_dir != NULL) {
481 sprintf(name, "%d", reg_set);
482
483 (void) debugfs_create_file(name, S_IRUGO,
484 pm_dbg_dir, (void *)reg_set, &debug_reg_fops);
485 }
486
487 return 0;
488 }
489
490 static int pwrdm_suspend_get(void *data, u64 *val)
491 {
492 *val = omap3_pm_get_suspend_state((struct powerdomain *)data);
493
494 if (*val >= 0)
495 return 0;
496 return *val;
497 }
498
499 static int pwrdm_suspend_set(void *data, u64 val)
500 {
501 return omap3_pm_set_suspend_state((struct powerdomain *)data, (int)val);
502 }
503
504 DEFINE_SIMPLE_ATTRIBUTE(pwrdm_suspend_fops, pwrdm_suspend_get,
505 pwrdm_suspend_set, "%llu\n");
506
507 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *dir)
508 {
509 int i;
510 s64 t;
511 struct dentry *d;
512
513 t = sched_clock();
514
515 for (i = 0; i < 4; i++)
516 pwrdm->state_timer[i] = 0;
517
518 pwrdm->timer = t;
519
520 if (strncmp(pwrdm->name, "dpll", 4) == 0)
521 return 0;
522
523 d = debugfs_create_dir(pwrdm->name, (struct dentry *)dir);
524
525 (void) debugfs_create_file("suspend", S_IRUGO|S_IWUSR, d,
526 (void *)pwrdm, &pwrdm_suspend_fops);
527
528 return 0;
529 }
530
531 static int option_get(void *data, u64 *val)
532 {
533 u32 *option = data;
534
535 *val = *option;
536
537 return 0;
538 }
539
540 static int option_set(void *data, u64 val)
541 {
542 u32 *option = data;
543
544 *option = val;
545
546 if (option == &enable_off_mode)
547 omap3_pm_off_mode_enable(val);
548 if (option == &voltage_off_while_idle) {
549 if (voltage_off_while_idle)
550 prm_set_mod_reg_bits(OMAP3430_SEL_OFF, OMAP3430_GR_MOD,
551 OMAP3_PRM_VOLTCTRL_OFFSET);
552 else
553 prm_clear_mod_reg_bits(OMAP3430_SEL_OFF,
554 OMAP3430_GR_MOD,
555 OMAP3_PRM_VOLTCTRL_OFFSET);
556 }
557
558 return 0;
559 }
560
561 DEFINE_SIMPLE_ATTRIBUTE(pm_dbg_option_fops, option_get, option_set, "%llu\n");
562
563 static int __init pm_dbg_init(void)
564 {
565 int i;
566 struct dentry *d;
567 char name[2];
568
569 if (pm_dbg_init_done)
570 return 0;
571
572 if (cpu_is_omap34xx())
573 pm_dbg_reg_modules = omap3_pm_reg_modules;
574 else {
575 printk(KERN_ERR "%s: only OMAP3 supported\n", __func__);
576 return -ENODEV;
577 }
578
579 d = debugfs_create_dir("pm_debug", NULL);
580 if (IS_ERR(d))
581 return PTR_ERR(d);
582
583 (void) debugfs_create_file("count", S_IRUGO,
584 d, (void *)DEBUG_FILE_COUNTERS, &debug_fops);
585 (void) debugfs_create_file("time", S_IRUGO,
586 d, (void *)DEBUG_FILE_TIMERS, &debug_fops);
587
588 pwrdm_for_each_nolock(pwrdms_setup, (void *)d);
589
590 pm_dbg_dir = debugfs_create_dir("registers", d);
591 if (IS_ERR(pm_dbg_dir))
592 return PTR_ERR(pm_dbg_dir);
593
594 (void) debugfs_create_file("current", S_IRUGO,
595 pm_dbg_dir, (void *)0, &debug_reg_fops);
596
597 for (i = 0; i < PM_DBG_MAX_REG_SETS; i++)
598 if (pm_dbg_reg_set[i] != NULL) {
599 sprintf(name, "%d", i+1);
600 (void) debugfs_create_file(name, S_IRUGO,
601 pm_dbg_dir, (void *)(i+1), &debug_reg_fops);
602
603 }
604
605 (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUGO, d,
606 &enable_off_mode, &pm_dbg_option_fops);
607 (void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUGO, d,
608 &sleep_while_idle, &pm_dbg_option_fops);
609 (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d,
610 &wakeup_timer_seconds, &pm_dbg_option_fops);
611
612 /* Only enable for >= ES2.1 . Going to 0V on anything under
613 * ES2.1 will eventually cause a crash */
614 if (omap_rev() > OMAP3430_REV_ES2_0)
615 (void) debugfs_create_file("voltage_off_while_idle",
616 S_IRUGO | S_IWUGO, d,
617 &voltage_off_while_idle,
618 &pm_dbg_option_fops);
619
620 pm_dbg_init_done = 1;
621
622 return 0;
623 }
624 arch_initcall(pm_dbg_init);
625
626 #else
627 void pm_dbg_update_time(struct powerdomain *pwrdm, int prev) {}
628 #endif
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