drivers/scsi/mvsas/mv_94xx.h

   1 /*
   2  * Marvell 88SE94xx hardware specific head file
   3  *
   4  * Copyright 2007 Red Hat, Inc.
   5  * Copyright 2008 Marvell. <kewei@marvell.com>
   6  *
   7  * This file is licensed under GPLv2.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; version 2 of the
  12  * License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  22  * USA
  23 */
  24
  25 #ifndef _MVS94XX_REG_H_
  26 #define _MVS94XX_REG_H_
  27
  28 #include <linux/types.h>
  29
  30 #define MAX_LINK_RATE           SAS_LINK_RATE_6_0_GBPS
  31
  32 enum hw_registers {
  33         MVS_GBL_CTL             = 0x04,  /* global control */
  34         MVS_GBL_INT_STAT        = 0x00,  /* global irq status */
  35         MVS_GBL_PI              = 0x0C,  /* ports implemented bitmask */
  36
  37         MVS_PHY_CTL             = 0x40,  /* SOC PHY Control */
  38         MVS_PORTS_IMP           = 0x9C,  /* SOC Port Implemented */
  39
  40         MVS_GBL_PORT_TYPE       = 0xa0,  /* port type */
  41
  42         MVS_CTL                 = 0x100, /* SAS/SATA port configuration */
  43         MVS_PCS                 = 0x104, /* SAS/SATA port control/status */
  44         MVS_CMD_LIST_LO         = 0x108, /* cmd list addr */
  45         MVS_CMD_LIST_HI         = 0x10C,
  46         MVS_RX_FIS_LO           = 0x110, /* RX FIS list addr */
  47         MVS_RX_FIS_HI           = 0x114,
  48         MVS_STP_REG_SET_0       = 0x118, /* STP/SATA Register Set Enable */
  49         MVS_STP_REG_SET_1       = 0x11C,
  50         MVS_TX_CFG              = 0x120, /* TX configuration */
  51         MVS_TX_LO               = 0x124, /* TX (delivery) ring addr */
  52         MVS_TX_HI               = 0x128,
  53
  54         MVS_TX_PROD_IDX         = 0x12C, /* TX producer pointer */
  55         MVS_TX_CONS_IDX         = 0x130, /* TX consumer pointer (RO) */
  56         MVS_RX_CFG              = 0x134, /* RX configuration */
  57         MVS_RX_LO               = 0x138, /* RX (completion) ring addr */
  58         MVS_RX_HI               = 0x13C,
  59         MVS_RX_CONS_IDX         = 0x140, /* RX consumer pointer (RO) */
  60
  61         MVS_INT_COAL            = 0x148, /* Int coalescing config */
  62         MVS_INT_COAL_TMOUT      = 0x14C, /* Int coalescing timeout */
  63         MVS_INT_STAT            = 0x150, /* Central int status */
  64         MVS_INT_MASK            = 0x154, /* Central int enable */
  65         MVS_INT_STAT_SRS_0      = 0x158, /* SATA register set status */
  66         MVS_INT_MASK_SRS_0      = 0x15C,
  67         MVS_INT_STAT_SRS_1      = 0x160,
  68         MVS_INT_MASK_SRS_1      = 0x164,
  69         MVS_NON_NCQ_ERR_0       = 0x168, /* SRS Non-specific NCQ Error */
  70         MVS_NON_NCQ_ERR_1       = 0x16C,
  71         MVS_CMD_ADDR            = 0x170, /* Command register port (addr) */
  72         MVS_CMD_DATA            = 0x174, /* Command register port (data) */
  73         MVS_MEM_PARITY_ERR      = 0x178, /* Memory parity error */
  74
  75                                          /* ports 1-3 follow after this */
  76         MVS_P0_INT_STAT         = 0x180, /* port0 interrupt status */
  77         MVS_P0_INT_MASK         = 0x184, /* port0 interrupt mask */
  78                                          /* ports 5-7 follow after this */
  79         MVS_P4_INT_STAT         = 0x1A0, /* Port4 interrupt status */
  80         MVS_P4_INT_MASK         = 0x1A4, /* Port4 interrupt enable mask */
  81
  82                                          /* ports 1-3 follow after this */
  83         MVS_P0_SER_CTLSTAT      = 0x1D0, /* port0 serial control/status */
  84                                          /* ports 5-7 follow after this */
  85         MVS_P4_SER_CTLSTAT      = 0x1E0, /* port4 serial control/status */
  86
  87                                          /* ports 1-3 follow after this */
  88         MVS_P0_CFG_ADDR         = 0x200, /* port0 phy register address */
  89         MVS_P0_CFG_DATA         = 0x204, /* port0 phy register data */
  90                                          /* ports 5-7 follow after this */
  91         MVS_P4_CFG_ADDR         = 0x220, /* Port4 config address */
  92         MVS_P4_CFG_DATA         = 0x224, /* Port4 config data */
  93
  94                                          /* phys 1-3 follow after this */
  95         MVS_P0_VSR_ADDR         = 0x250, /* phy0 VSR address */
  96         MVS_P0_VSR_DATA         = 0x254, /* phy0 VSR data */
  97                                          /* phys 1-3 follow after this */
  98                                          /* multiplexing */
  99         MVS_P4_VSR_ADDR         = 0x250, /* phy4 VSR address */
 100         MVS_P4_VSR_DATA         = 0x254, /* phy4 VSR data */
 101         MVS_PA_VSR_ADDR         = 0x290, /* All port VSR addr */
 102         MVS_PA_VSR_PORT         = 0x294, /* All port VSR data */
 103 };
 104
 105 enum pci_cfg_registers {
 106         PCR_PHY_CTL             = 0x40,
 107         PCR_PHY_CTL2            = 0x90,
 108         PCR_DEV_CTRL            = 0x78,
 109         PCR_LINK_STAT           = 0x82,
 110 };
 111
 112 /*  SAS/SATA Vendor Specific Port Registers */
 113 enum sas_sata_vsp_regs {
 114         VSR_PHY_STAT            = 0x00 * 4, /* Phy Status */
 115         VSR_PHY_MODE1           = 0x01 * 4, /* phy tx */
 116         VSR_PHY_MODE2           = 0x02 * 4, /* tx scc */
 117         VSR_PHY_MODE3           = 0x03 * 4, /* pll */
 118         VSR_PHY_MODE4           = 0x04 * 4, /* VCO */
 119         VSR_PHY_MODE5           = 0x05 * 4, /* Rx */
 120         VSR_PHY_MODE6           = 0x06 * 4, /* CDR */
 121         VSR_PHY_MODE7           = 0x07 * 4, /* Impedance */
 122         VSR_PHY_MODE8           = 0x08 * 4, /* Voltage */
 123         VSR_PHY_MODE9           = 0x09 * 4, /* Test */
 124         VSR_PHY_MODE10          = 0x0A * 4, /* Power */
 125         VSR_PHY_MODE11          = 0x0B * 4, /* Phy Mode */
 126         VSR_PHY_VS0             = 0x0C * 4, /* Vednor Specific 0 */
 127         VSR_PHY_VS1             = 0x0D * 4, /* Vednor Specific 1 */
 128 };
 129
 130 enum chip_register_bits {
 131         PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0x7 << 8),
 132         PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0x7 << 8),
 133         PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (12),
 134         PHY_NEG_SPP_PHYS_LINK_RATE_MASK =
 135                         (0x3 << PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET),
 136 };
 137
 138 enum pci_interrupt_cause {
 139         /*  MAIN_IRQ_CAUSE (R10200) Bits*/
 140         IRQ_COM_IN_I2O_IOP0            = (1 << 0),
 141         IRQ_COM_IN_I2O_IOP1            = (1 << 1),
 142         IRQ_COM_IN_I2O_IOP2            = (1 << 2),
 143         IRQ_COM_IN_I2O_IOP3            = (1 << 3),
 144         IRQ_COM_OUT_I2O_HOS0           = (1 << 4),
 145         IRQ_COM_OUT_I2O_HOS1           = (1 << 5),
 146         IRQ_COM_OUT_I2O_HOS2           = (1 << 6),
 147         IRQ_COM_OUT_I2O_HOS3           = (1 << 7),
 148         IRQ_PCIF_TO_CPU_DRBL0          = (1 << 8),
 149         IRQ_PCIF_TO_CPU_DRBL1          = (1 << 9),
 150         IRQ_PCIF_TO_CPU_DRBL2          = (1 << 10),
 151         IRQ_PCIF_TO_CPU_DRBL3          = (1 << 11),
 152         IRQ_PCIF_DRBL0                 = (1 << 12),
 153         IRQ_PCIF_DRBL1                 = (1 << 13),
 154         IRQ_PCIF_DRBL2                 = (1 << 14),
 155         IRQ_PCIF_DRBL3                 = (1 << 15),
 156         IRQ_XOR_A                      = (1 << 16),
 157         IRQ_XOR_B                      = (1 << 17),
 158         IRQ_SAS_A                      = (1 << 18),
 159         IRQ_SAS_B                      = (1 << 19),
 160         IRQ_CPU_CNTRL                  = (1 << 20),
 161         IRQ_GPIO                       = (1 << 21),
 162         IRQ_UART                       = (1 << 22),
 163         IRQ_SPI                        = (1 << 23),
 164         IRQ_I2C                        = (1 << 24),
 165         IRQ_SGPIO                      = (1 << 25),
 166         IRQ_COM_ERR                    = (1 << 29),
 167         IRQ_I2O_ERR                    = (1 << 30),
 168         IRQ_PCIE_ERR                   = (1 << 31),
 169 };
 170
 171 #define MAX_SG_ENTRY            255
 172
 173 struct mvs_prd_imt {
 174         __le32                  len:22;
 175         u8                      _r_a:2;
 176         u8                      misc_ctl:4;
 177         u8                      inter_sel:4;
 178 };
 179
 180 struct mvs_prd {
 181         /* 64-bit buffer address */
 182         __le64                  addr;
 183         /* 22-bit length */
 184         struct mvs_prd_imt      im_len;
 185 } __attribute__ ((packed));
 186
 187 #define SPI_CTRL_REG_94XX               0xc800
 188 #define SPI_ADDR_REG_94XX               0xc804
 189 #define SPI_WR_DATA_REG_94XX         0xc808
 190 #define SPI_RD_DATA_REG_94XX            0xc80c
 191 #define SPI_CTRL_READ_94XX              (1U << 2)
 192 #define SPI_ADDR_VLD_94XX               (1U << 1)
 193 #define SPI_CTRL_SpiStart_94XX          (1U << 0)
 194
 195 #define mv_ffc(x)   ffz(x)
 196
 197 static inline int
 198 mv_ffc64(u64 v)
 199 {
 200         int i;
 201         i = mv_ffc((u32)v);
 202         if (i >= 0)
 203                 return i;
 204         i = mv_ffc((u32)(v>>32));
 205
 206         if (i != 0)
 207                 return 32 + i;
 208
 209         return -1;
 210 }
 211
 212 #define r_reg_set_enable(i) \
 213         (((i) > 31) ? mr32(MVS_STP_REG_SET_1) : \
 214         mr32(MVS_STP_REG_SET_0))
 215
 216 #define w_reg_set_enable(i, tmp) \
 217         (((i) > 31) ? mw32(MVS_STP_REG_SET_1, tmp) : \
 218         mw32(MVS_STP_REG_SET_0, tmp))
 219
 220 extern const struct mvs_dispatch mvs_94xx_dispatch;
 221 #endif
 222