arch/arm/mach-at91/at91cap9.c

   1 /*
   2  * arch/arm/mach-at91/at91cap9.c
   3  *
   4  *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
   5  *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
   6  *  Copyright (C) 2007 Atmel Corporation.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/pm.h>
  17
  18 #include <asm/mach/arch.h>
  19 #include <asm/mach/map.h>
  20 #include <mach/at91cap9.h>
  21 #include <mach/at91_pmc.h>
  22 #include <mach/at91_rstc.h>
  23 #include <mach/at91_shdwc.h>
  24
  25 #include "generic.h"
  26 #include "clock.h"
  27
  28 static struct map_desc at91cap9_io_desc[] __initdata = {
  29         {
  30                 .virtual        = AT91_VA_BASE_SYS,
  31                 .pfn            = __phys_to_pfn(AT91_BASE_SYS),
  32                 .length         = SZ_16K,
  33                 .type           = MT_DEVICE,
  34         }, {
  35                 .virtual        = AT91_IO_VIRT_BASE - AT91CAP9_SRAM_SIZE,
  36                 .pfn            = __phys_to_pfn(AT91CAP9_SRAM_BASE),
  37                 .length         = AT91CAP9_SRAM_SIZE,
  38                 .type           = MT_DEVICE,
  39         },
  40 };
  41
  42 /* --------------------------------------------------------------------
  43  *  Clocks
  44  * -------------------------------------------------------------------- */
  45
  46 /*
  47  * The peripheral clocks.
  48  */
  49 static struct clk pioABCD_clk = {
  50         .name           = "pioABCD_clk",
  51         .pmc_mask       = 1 << AT91CAP9_ID_PIOABCD,
  52         .type           = CLK_TYPE_PERIPHERAL,
  53 };
  54 static struct clk mpb0_clk = {
  55         .name           = "mpb0_clk",
  56         .pmc_mask       = 1 << AT91CAP9_ID_MPB0,
  57         .type           = CLK_TYPE_PERIPHERAL,
  58 };
  59 static struct clk mpb1_clk = {
  60         .name           = "mpb1_clk",
  61         .pmc_mask       = 1 << AT91CAP9_ID_MPB1,
  62         .type           = CLK_TYPE_PERIPHERAL,
  63 };
  64 static struct clk mpb2_clk = {
  65         .name           = "mpb2_clk",
  66         .pmc_mask       = 1 << AT91CAP9_ID_MPB2,
  67         .type           = CLK_TYPE_PERIPHERAL,
  68 };
  69 static struct clk mpb3_clk = {
  70         .name           = "mpb3_clk",
  71         .pmc_mask       = 1 << AT91CAP9_ID_MPB3,
  72         .type           = CLK_TYPE_PERIPHERAL,
  73 };
  74 static struct clk mpb4_clk = {
  75         .name           = "mpb4_clk",
  76         .pmc_mask       = 1 << AT91CAP9_ID_MPB4,
  77         .type           = CLK_TYPE_PERIPHERAL,
  78 };
  79 static struct clk usart0_clk = {
  80         .name           = "usart0_clk",
  81         .pmc_mask       = 1 << AT91CAP9_ID_US0,
  82         .type           = CLK_TYPE_PERIPHERAL,
  83 };
  84 static struct clk usart1_clk = {
  85         .name           = "usart1_clk",
  86         .pmc_mask       = 1 << AT91CAP9_ID_US1,
  87         .type           = CLK_TYPE_PERIPHERAL,
  88 };
  89 static struct clk usart2_clk = {
  90         .name           = "usart2_clk",
  91         .pmc_mask       = 1 << AT91CAP9_ID_US2,
  92         .type           = CLK_TYPE_PERIPHERAL,
  93 };
  94 static struct clk mmc0_clk = {
  95         .name           = "mci0_clk",
  96         .pmc_mask       = 1 << AT91CAP9_ID_MCI0,
  97         .type           = CLK_TYPE_PERIPHERAL,
  98 };
  99 static struct clk mmc1_clk = {
 100         .name           = "mci1_clk",
 101         .pmc_mask       = 1 << AT91CAP9_ID_MCI1,
 102         .type           = CLK_TYPE_PERIPHERAL,
 103 };
 104 static struct clk can_clk = {
 105         .name           = "can_clk",
 106         .pmc_mask       = 1 << AT91CAP9_ID_CAN,
 107         .type           = CLK_TYPE_PERIPHERAL,
 108 };
 109 static struct clk twi_clk = {
 110         .name           = "twi_clk",
 111         .pmc_mask       = 1 << AT91CAP9_ID_TWI,
 112         .type           = CLK_TYPE_PERIPHERAL,
 113 };
 114 static struct clk spi0_clk = {
 115         .name           = "spi0_clk",
 116         .pmc_mask       = 1 << AT91CAP9_ID_SPI0,
 117         .type           = CLK_TYPE_PERIPHERAL,
 118 };
 119 static struct clk spi1_clk = {
 120         .name           = "spi1_clk",
 121         .pmc_mask       = 1 << AT91CAP9_ID_SPI1,
 122         .type           = CLK_TYPE_PERIPHERAL,
 123 };
 124 static struct clk ssc0_clk = {
 125         .name           = "ssc0_clk",
 126         .pmc_mask       = 1 << AT91CAP9_ID_SSC0,
 127         .type           = CLK_TYPE_PERIPHERAL,
 128 };
 129 static struct clk ssc1_clk = {
 130         .name           = "ssc1_clk",
 131         .pmc_mask       = 1 << AT91CAP9_ID_SSC1,
 132         .type           = CLK_TYPE_PERIPHERAL,
 133 };
 134 static struct clk ac97_clk = {
 135         .name           = "ac97_clk",
 136         .pmc_mask       = 1 << AT91CAP9_ID_AC97C,
 137         .type           = CLK_TYPE_PERIPHERAL,
 138 };
 139 static struct clk tcb_clk = {
 140         .name           = "tcb_clk",
 141         .pmc_mask       = 1 << AT91CAP9_ID_TCB,
 142         .type           = CLK_TYPE_PERIPHERAL,
 143 };
 144 static struct clk pwmc_clk = {
 145         .name           = "pwmc_clk",
 146         .pmc_mask       = 1 << AT91CAP9_ID_PWMC,
 147         .type           = CLK_TYPE_PERIPHERAL,
 148 };
 149 static struct clk macb_clk = {
 150         .name           = "macb_clk",
 151         .pmc_mask       = 1 << AT91CAP9_ID_EMAC,
 152         .type           = CLK_TYPE_PERIPHERAL,
 153 };
 154 static struct clk aestdes_clk = {
 155         .name           = "aestdes_clk",
 156         .pmc_mask       = 1 << AT91CAP9_ID_AESTDES,
 157         .type           = CLK_TYPE_PERIPHERAL,
 158 };
 159 static struct clk adc_clk = {
 160         .name           = "adc_clk",
 161         .pmc_mask       = 1 << AT91CAP9_ID_ADC,
 162         .type           = CLK_TYPE_PERIPHERAL,
 163 };
 164 static struct clk isi_clk = {
 165         .name           = "isi_clk",
 166         .pmc_mask       = 1 << AT91CAP9_ID_ISI,
 167         .type           = CLK_TYPE_PERIPHERAL,
 168 };
 169 static struct clk lcdc_clk = {
 170         .name           = "lcdc_clk",
 171         .pmc_mask       = 1 << AT91CAP9_ID_LCDC,
 172         .type           = CLK_TYPE_PERIPHERAL,
 173 };
 174 static struct clk dma_clk = {
 175         .name           = "dma_clk",
 176         .pmc_mask       = 1 << AT91CAP9_ID_DMA,
 177         .type           = CLK_TYPE_PERIPHERAL,
 178 };
 179 static struct clk udphs_clk = {
 180         .name           = "udphs_clk",
 181         .pmc_mask       = 1 << AT91CAP9_ID_UDPHS,
 182         .type           = CLK_TYPE_PERIPHERAL,
 183 };
 184 static struct clk ohci_clk = {
 185         .name           = "ohci_clk",
 186         .pmc_mask       = 1 << AT91CAP9_ID_UHP,
 187         .type           = CLK_TYPE_PERIPHERAL,
 188 };
 189
 190 static struct clk *periph_clocks[] __initdata = {
 191         &pioABCD_clk,
 192         &mpb0_clk,
 193         &mpb1_clk,
 194         &mpb2_clk,
 195         &mpb3_clk,
 196         &mpb4_clk,
 197         &usart0_clk,
 198         &usart1_clk,
 199         &usart2_clk,
 200         &mmc0_clk,
 201         &mmc1_clk,
 202         &can_clk,
 203         &twi_clk,
 204         &spi0_clk,
 205         &spi1_clk,
 206         &ssc0_clk,
 207         &ssc1_clk,
 208         &ac97_clk,
 209         &tcb_clk,
 210         &pwmc_clk,
 211         &macb_clk,
 212         &aestdes_clk,
 213         &adc_clk,
 214         &isi_clk,
 215         &lcdc_clk,
 216         &dma_clk,
 217         &udphs_clk,
 218         &ohci_clk,
 219         // irq0 .. irq1
 220 };
 221
 222 /*
 223  * The four programmable clocks.
 224  * You must configure pin multiplexing to bring these signals out.
 225  */
 226 static struct clk pck0 = {
 227         .name           = "pck0",
 228         .pmc_mask       = AT91_PMC_PCK0,
 229         .type           = CLK_TYPE_PROGRAMMABLE,
 230         .id             = 0,
 231 };
 232 static struct clk pck1 = {
 233         .name           = "pck1",
 234         .pmc_mask       = AT91_PMC_PCK1,
 235         .type           = CLK_TYPE_PROGRAMMABLE,
 236         .id             = 1,
 237 };
 238 static struct clk pck2 = {
 239         .name           = "pck2",
 240         .pmc_mask       = AT91_PMC_PCK2,
 241         .type           = CLK_TYPE_PROGRAMMABLE,
 242         .id             = 2,
 243 };
 244 static struct clk pck3 = {
 245         .name           = "pck3",
 246         .pmc_mask       = AT91_PMC_PCK3,
 247         .type           = CLK_TYPE_PROGRAMMABLE,
 248         .id             = 3,
 249 };
 250
 251 static void __init at91cap9_register_clocks(void)
 252 {
 253         int i;
 254
 255         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 256                 clk_register(periph_clocks[i]);
 257
 258         clk_register(&pck0);
 259         clk_register(&pck1);
 260         clk_register(&pck2);
 261         clk_register(&pck3);
 262 }
 263
 264 /* --------------------------------------------------------------------
 265  *  GPIO
 266  * -------------------------------------------------------------------- */
 267
 268 static struct at91_gpio_bank at91cap9_gpio[] = {
 269         {
 270                 .id             = AT91CAP9_ID_PIOABCD,
 271                 .offset         = AT91_PIOA,
 272                 .clock          = &pioABCD_clk,
 273         }, {
 274                 .id             = AT91CAP9_ID_PIOABCD,
 275                 .offset         = AT91_PIOB,
 276                 .clock          = &pioABCD_clk,
 277         }, {
 278                 .id             = AT91CAP9_ID_PIOABCD,
 279                 .offset         = AT91_PIOC,
 280                 .clock          = &pioABCD_clk,
 281         }, {
 282                 .id             = AT91CAP9_ID_PIOABCD,
 283                 .offset         = AT91_PIOD,
 284                 .clock          = &pioABCD_clk,
 285         }
 286 };
 287
 288 static void at91cap9_reset(void)
 289 {
 290         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
 291 }
 292
 293 static void at91cap9_poweroff(void)
 294 {
 295         at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
 296 }
 297
 298
 299 /* --------------------------------------------------------------------
 300  *  AT91CAP9 processor initialization
 301  * -------------------------------------------------------------------- */
 302
 303 void __init at91cap9_initialize(unsigned long main_clock)
 304 {
 305         /* Map peripherals */
 306         iotable_init(at91cap9_io_desc, ARRAY_SIZE(at91cap9_io_desc));
 307
 308         at91_arch_reset = at91cap9_reset;
 309         pm_power_off = at91cap9_poweroff;
 310         at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
 311
 312         /* Init clock subsystem */
 313         at91_clock_init(main_clock);
 314
 315         /* Register the processor-specific clocks */
 316         at91cap9_register_clocks();
 317
 318         /* Register GPIO subsystem */
 319         at91_gpio_init(at91cap9_gpio, 4);
 320 }
 321
 322 /* --------------------------------------------------------------------
 323  *  Interrupt initialization
 324  * -------------------------------------------------------------------- */
 325
 326 /*
 327  * The default interrupt priority levels (0 = lowest, 7 = highest).
 328  */
 329 static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
 330         7,      /* Advanced Interrupt Controller (FIQ) */
 331         7,      /* System Peripherals */
 332         1,      /* Parallel IO Controller A, B, C and D */
 333         0,      /* MP Block Peripheral 0 */
 334         0,      /* MP Block Peripheral 1 */
 335         0,      /* MP Block Peripheral 2 */
 336         0,      /* MP Block Peripheral 3 */
 337         0,      /* MP Block Peripheral 4 */
 338         5,      /* USART 0 */
 339         5,      /* USART 1 */
 340         5,      /* USART 2 */
 341         0,      /* Multimedia Card Interface 0 */
 342         0,      /* Multimedia Card Interface 1 */
 343         3,      /* CAN */
 344         6,      /* Two-Wire Interface */
 345         5,      /* Serial Peripheral Interface 0 */
 346         5,      /* Serial Peripheral Interface 1 */
 347         4,      /* Serial Synchronous Controller 0 */
 348         4,      /* Serial Synchronous Controller 1 */
 349         5,      /* AC97 Controller */
 350         0,      /* Timer Counter 0, 1 and 2 */
 351         0,      /* Pulse Width Modulation Controller */
 352         3,      /* Ethernet */
 353         0,      /* Advanced Encryption Standard, Triple DES*/
 354         0,      /* Analog-to-Digital Converter */
 355         0,      /* Image Sensor Interface */
 356         3,      /* LCD Controller */
 357         0,      /* DMA Controller */
 358         2,      /* USB Device Port */
 359         2,      /* USB Host port */
 360         0,      /* Advanced Interrupt Controller (IRQ0) */
 361         0,      /* Advanced Interrupt Controller (IRQ1) */
 362 };
 363
 364 void __init at91cap9_init_interrupts(unsigned int priority[NR_AIC_IRQS])
 365 {
 366         if (!priority)
 367                 priority = at91cap9_default_irq_priority;
 368
 369         /* Initialize the AIC interrupt controller */
 370         at91_aic_init(priority);
 371
 372         /* Enable GPIO interrupts */
 373         at91_gpio_irq_setup();
 374 }