arch/arm/mach-at91/include/mach/at91cap9_matrix.h

   1 /*
   2  * arch/arm/mach-at91/include/mach/at91cap9_matrix.h
   3  *
   4  *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
   5  *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
   6  *  Copyright (C) 2006 Atmel Corporation.
   7  *
   8  * Memory Controllers (MATRIX, EBI) - System peripherals registers.
   9  * Based on AT91CAP9 datasheet revision B (Preliminary).
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #ifndef AT91CAP9_MATRIX_H
  18 #define AT91CAP9_MATRIX_H
  19
  20 #define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
  21 #define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
  22 #define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
  23 #define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
  24 #define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
  25 #define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
  26 #define AT91_MATRIX_MCFG6       (AT91_MATRIX + 0x18)    /* Master Configuration Register 6 */
  27 #define AT91_MATRIX_MCFG7       (AT91_MATRIX + 0x1C)    /* Master Configuration Register 7 */
  28 #define AT91_MATRIX_MCFG8       (AT91_MATRIX + 0x20)    /* Master Configuration Register 8 */
  29 #define AT91_MATRIX_MCFG9       (AT91_MATRIX + 0x24)    /* Master Configuration Register 9 */
  30 #define AT91_MATRIX_MCFG10      (AT91_MATRIX + 0x28)    /* Master Configuration Register 10 */
  31 #define AT91_MATRIX_MCFG11      (AT91_MATRIX + 0x2C)    /* Master Configuration Register 11 */
  32 #define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
  33 #define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
  34 #define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
  35 #define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
  36 #define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
  37 #define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
  38
  39 #define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
  40 #define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
  41 #define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
  42 #define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
  43 #define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
  44 #define AT91_MATRIX_SCFG5       (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
  45 #define AT91_MATRIX_SCFG6       (AT91_MATRIX + 0x58)    /* Slave Configuration Register 6 */
  46 #define AT91_MATRIX_SCFG7       (AT91_MATRIX + 0x5C)    /* Slave Configuration Register 7 */
  47 #define AT91_MATRIX_SCFG8       (AT91_MATRIX + 0x60)    /* Slave Configuration Register 8 */
  48 #define AT91_MATRIX_SCFG9       (AT91_MATRIX + 0x64)    /* Slave Configuration Register 9 */
  49 #define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
  50 #define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
  51 #define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
  52 #define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
  53 #define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
  54 #define         AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
  55 #define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
  56 #define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
  57 #define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
  58
  59 #define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
  60 #define AT91_MATRIX_PRBS0       (AT91_MATRIX + 0x84)    /* Priority Register B for Slave 0 */
  61 #define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
  62 #define AT91_MATRIX_PRBS1       (AT91_MATRIX + 0x8C)    /* Priority Register B for Slave 1 */
  63 #define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
  64 #define AT91_MATRIX_PRBS2       (AT91_MATRIX + 0x94)    /* Priority Register B for Slave 2 */
  65 #define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
  66 #define AT91_MATRIX_PRBS3       (AT91_MATRIX + 0x9C)    /* Priority Register B for Slave 3 */
  67 #define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
  68 #define AT91_MATRIX_PRBS4       (AT91_MATRIX + 0xA4)    /* Priority Register B for Slave 4 */
  69 #define AT91_MATRIX_PRAS5       (AT91_MATRIX + 0xA8)    /* Priority Register A for Slave 5 */
  70 #define AT91_MATRIX_PRBS5       (AT91_MATRIX + 0xAC)    /* Priority Register B for Slave 5 */
  71 #define AT91_MATRIX_PRAS6       (AT91_MATRIX + 0xB0)    /* Priority Register A for Slave 6 */
  72 #define AT91_MATRIX_PRBS6       (AT91_MATRIX + 0xB4)    /* Priority Register B for Slave 6 */
  73 #define AT91_MATRIX_PRAS7       (AT91_MATRIX + 0xB8)    /* Priority Register A for Slave 7 */
  74 #define AT91_MATRIX_PRBS7       (AT91_MATRIX + 0xBC)    /* Priority Register B for Slave 7 */
  75 #define AT91_MATRIX_PRAS8       (AT91_MATRIX + 0xC0)    /* Priority Register A for Slave 8 */
  76 #define AT91_MATRIX_PRBS8       (AT91_MATRIX + 0xC4)    /* Priority Register B for Slave 8 */
  77 #define AT91_MATRIX_PRAS9       (AT91_MATRIX + 0xC8)    /* Priority Register A for Slave 9 */
  78 #define AT91_MATRIX_PRBS9       (AT91_MATRIX + 0xCC)    /* Priority Register B for Slave 9 */
  79 #define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
  80 #define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
  81 #define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
  82 #define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
  83 #define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
  84 #define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
  85 #define         AT91_MATRIX_M6PR                (3 << 24)       /* Master 6 Priority */
  86 #define         AT91_MATRIX_M7PR                (3 << 28)       /* Master 7 Priority */
  87 #define         AT91_MATRIX_M8PR                (3 << 0)        /* Master 8 Priority (in Register B) */
  88 #define         AT91_MATRIX_M9PR                (3 << 4)        /* Master 9 Priority (in Register B) */
  89 #define         AT91_MATRIX_M10PR               (3 << 8)        /* Master 10 Priority (in Register B) */
  90 #define         AT91_MATRIX_M11PR               (3 << 12)       /* Master 11 Priority (in Register B) */
  91
  92 #define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
  93 #define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
  94 #define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
  95 #define         AT91_MATRIX_RCB2                (1 << 2)
  96 #define         AT91_MATRIX_RCB3                (1 << 3)
  97 #define         AT91_MATRIX_RCB4                (1 << 4)
  98 #define         AT91_MATRIX_RCB5                (1 << 5)
  99 #define         AT91_MATRIX_RCB6                (1 << 6)
 100 #define         AT91_MATRIX_RCB7                (1 << 7)
 101 #define         AT91_MATRIX_RCB8                (1 << 8)
 102 #define         AT91_MATRIX_RCB9                (1 << 9)
 103 #define         AT91_MATRIX_RCB10               (1 << 10)
 104 #define         AT91_MATRIX_RCB11               (1 << 11)
 105
 106 #define AT91_MPBS0_SFR          (AT91_MATRIX + 0x114)   /* MPBlock Slave 0 Special Function Register */
 107 #define AT91_MPBS1_SFR          (AT91_MATRIX + 0x11C)   /* MPBlock Slave 1 Special Function Register */
 108
 109 #define AT91_MATRIX_UDPHS       (AT91_MATRIX + 0x118)   /* USBHS Special Function Register [AT91CAP9 only] */
 110 #define         AT91_MATRIX_SELECT_UDPHS        (0 << 31)       /* select High Speed UDP */
 111 #define         AT91_MATRIX_SELECT_UDP          (1 << 31)       /* select standard UDP */
 112 #define         AT91_MATRIX_UDPHS_BYPASS_LOCK   (1 << 30)       /* bypass lock bit */
 113
 114 #define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x120)   /* EBI Chip Select Assignment Register */
 115 #define         AT91_MATRIX_EBI_CS1A            (1 << 1)        /* Chip Select 1 Assignment */
 116 #define                 AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
 117 #define                 AT91_MATRIX_EBI_CS1A_BCRAMC             (1 << 1)
 118 #define         AT91_MATRIX_EBI_CS3A            (1 << 3)        /* Chip Select 3 Assignment */
 119 #define                 AT91_MATRIX_EBI_CS3A_SMC                (0 << 3)
 120 #define                 AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA     (1 << 3)
 121 #define         AT91_MATRIX_EBI_CS4A            (1 << 4)        /* Chip Select 4 Assignment */
 122 #define                 AT91_MATRIX_EBI_CS4A_SMC                (0 << 4)
 123 #define                 AT91_MATRIX_EBI_CS4A_SMC_CF1            (1 << 4)
 124 #define         AT91_MATRIX_EBI_CS5A            (1 << 5)        /* Chip Select 5 Assignment */
 125 #define                 AT91_MATRIX_EBI_CS5A_SMC                (0 << 5)
 126 #define                 AT91_MATRIX_EBI_CS5A_SMC_CF2            (1 << 5)
 127 #define         AT91_MATRIX_EBI_DBPUC           (1 << 8)        /* Data Bus Pull-up Configuration */
 128 #define         AT91_MATRIX_EBI_DQSPDC          (1 << 9)        /* Data Qualifier Strobe Pull-Down Configuration */
 129 #define         AT91_MATRIX_EBI_VDDIOMSEL       (1 << 16)       /* Memory voltage selection */
 130 #define                 AT91_MATRIX_EBI_VDDIOMSEL_1_8V          (0 << 16)
 131 #define                 AT91_MATRIX_EBI_VDDIOMSEL_3_3V          (1 << 16)
 132
 133 #define AT91_MPBS2_SFR          (AT91_MATRIX + 0x12C)   /* MPBlock Slave 2 Special Function Register */
 134 #define AT91_MPBS3_SFR          (AT91_MATRIX + 0x130)   /* MPBlock Slave 3 Special Function Register */
 135 #define AT91_APB_SFR            (AT91_MATRIX + 0x134)   /* APB Bridge Special Function Register */
 136
 137 #endif