arch/arm/mach-msm/irq.c

   1 /* linux/arch/arm/mach-msm/irq.c
   2  *
   3  * Copyright (C) 2007 Google, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/module.h>
  18 #include <linux/sched.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ptrace.h>
  21 #include <linux/timer.h>
  22
  23 #include <linux/irq.h>
  24 #include <mach/hardware.h>
  25
  26 #include <asm/io.h>
  27
  28 #include <mach/msm_iomap.h>
  29
  30 #define VIC_REG(off) (MSM_VIC_BASE + (off))
  31
  32 #define VIC_INT_SELECT0     VIC_REG(0x0000)  /* 1: FIQ, 0: IRQ */
  33 #define VIC_INT_SELECT1     VIC_REG(0x0004)  /* 1: FIQ, 0: IRQ */
  34 #define VIC_INT_EN0         VIC_REG(0x0010)
  35 #define VIC_INT_EN1         VIC_REG(0x0014)
  36 #define VIC_INT_ENCLEAR0    VIC_REG(0x0020)
  37 #define VIC_INT_ENCLEAR1    VIC_REG(0x0024)
  38 #define VIC_INT_ENSET0      VIC_REG(0x0030)
  39 #define VIC_INT_ENSET1      VIC_REG(0x0034)
  40 #define VIC_INT_TYPE0       VIC_REG(0x0040)  /* 1: EDGE, 0: LEVEL  */
  41 #define VIC_INT_TYPE1       VIC_REG(0x0044)  /* 1: EDGE, 0: LEVEL  */
  42 #define VIC_INT_POLARITY0   VIC_REG(0x0050)  /* 1: NEG, 0: POS */
  43 #define VIC_INT_POLARITY1   VIC_REG(0x0054)  /* 1: NEG, 0: POS */
  44 #define VIC_NO_PEND_VAL     VIC_REG(0x0060)
  45 #define VIC_INT_MASTEREN    VIC_REG(0x0064)  /* 1: IRQ, 2: FIQ     */
  46 #define VIC_PROTECTION      VIC_REG(0x006C)  /* 1: ENABLE          */
  47 #define VIC_CONFIG          VIC_REG(0x0068)  /* 1: USE ARM1136 VIC */
  48 #define VIC_IRQ_STATUS0     VIC_REG(0x0080)
  49 #define VIC_IRQ_STATUS1     VIC_REG(0x0084)
  50 #define VIC_FIQ_STATUS0     VIC_REG(0x0090)
  51 #define VIC_FIQ_STATUS1     VIC_REG(0x0094)
  52 #define VIC_RAW_STATUS0     VIC_REG(0x00A0)
  53 #define VIC_RAW_STATUS1     VIC_REG(0x00A4)
  54 #define VIC_INT_CLEAR0      VIC_REG(0x00B0)
  55 #define VIC_INT_CLEAR1      VIC_REG(0x00B4)
  56 #define VIC_SOFTINT0        VIC_REG(0x00C0)
  57 #define VIC_SOFTINT1        VIC_REG(0x00C4)
  58 #define VIC_IRQ_VEC_RD      VIC_REG(0x00D0)  /* pending int # */
  59 #define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4)  /* pending vector addr */
  60 #define VIC_IRQ_VEC_WR      VIC_REG(0x00D8)
  61 #define VIC_IRQ_IN_SERVICE  VIC_REG(0x00E0)
  62 #define VIC_IRQ_IN_STACK    VIC_REG(0x00E4)
  63 #define VIC_TEST_BUS_SEL    VIC_REG(0x00E8)
  64
  65 #define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4))
  66 #define VIC_VECTADDR(n)     VIC_REG(0x0400+((n) * 4))
  67
  68 static void msm_irq_ack(unsigned int irq)
  69 {
  70         unsigned reg = VIC_INT_CLEAR0 + ((irq & 32) ? 4 : 0);
  71         irq = 1 << (irq & 31);
  72         writel(irq, reg);
  73 }
  74
  75 static void msm_irq_mask(unsigned int irq)
  76 {
  77         unsigned reg = VIC_INT_ENCLEAR0 + ((irq & 32) ? 4 : 0);
  78         writel(1 << (irq & 31), reg);
  79 }
  80
  81 static void msm_irq_unmask(unsigned int irq)
  82 {
  83         unsigned reg = VIC_INT_ENSET0 + ((irq & 32) ? 4 : 0);
  84         writel(1 << (irq & 31), reg);
  85 }
  86
  87 static int msm_irq_set_wake(unsigned int irq, unsigned int on)
  88 {
  89         return -EINVAL;
  90 }
  91
  92 static int msm_irq_set_type(unsigned int irq, unsigned int flow_type)
  93 {
  94         unsigned treg = VIC_INT_TYPE0 + ((irq & 32) ? 4 : 0);
  95         unsigned preg = VIC_INT_POLARITY0 + ((irq & 32) ? 4 : 0);
  96         int b = 1 << (irq & 31);
  97
  98         if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW))
  99                 writel(readl(preg) | b, preg);
 100         if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
 101                 writel(readl(preg) & (~b), preg);
 102
 103         if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
 104                 writel(readl(treg) | b, treg);
 105                 set_irq_handler(irq, handle_edge_irq);
 106         }
 107         if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
 108                 writel(readl(treg) & (~b), treg);
 109                 set_irq_handler(irq, handle_level_irq);
 110         }
 111         return 0;
 112 }
 113
 114 static struct irq_chip msm_irq_chip = {
 115         .name      = "msm",
 116         .ack       = msm_irq_ack,
 117         .mask      = msm_irq_mask,
 118         .unmask    = msm_irq_unmask,
 119         .set_wake  = msm_irq_set_wake,
 120         .set_type  = msm_irq_set_type,
 121 };
 122
 123 void __init msm_init_irq(void)
 124 {
 125         unsigned n;
 126
 127         /* select level interrupts */
 128         writel(0, VIC_INT_TYPE0);
 129         writel(0, VIC_INT_TYPE1);
 130
 131         /* select highlevel interrupts */
 132         writel(0, VIC_INT_POLARITY0);
 133         writel(0, VIC_INT_POLARITY1);
 134
 135         /* select IRQ for all INTs */
 136         writel(0, VIC_INT_SELECT0);
 137         writel(0, VIC_INT_SELECT1);
 138
 139         /* disable all INTs */
 140         writel(0, VIC_INT_EN0);
 141         writel(0, VIC_INT_EN1);
 142
 143         /* don't use 1136 vic */
 144         writel(0, VIC_CONFIG);
 145
 146         /* enable interrupt controller */
 147         writel(1, VIC_INT_MASTEREN);
 148
 149         for (n = 0; n < NR_MSM_IRQS; n++) {
 150                 set_irq_chip(n, &msm_irq_chip);
 151                 set_irq_handler(n, handle_level_irq);
 152                 set_irq_flags(n, IRQF_VALID);
 153         }
 154 }