include/asm-mips/vr4181/vr4181.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1999 by Michael Klar
   7  *
   8  * Copyright 2001 MontaVista Software Inc.
   9  * Author: jsun@mvista.com or jsun@junsun.net
  10  *
  11  */
  12 #ifndef __ASM_VR4181_VR4181_H
  13 #define __ASM_VR4181_VR4181_H
  14
  15 #include <asm/addrspace.h>
  16
  17 #include <asm/vr4181/irq.h>
  18
  19 #ifndef __ASSEMBLY__
  20 #define __preg8         (volatile unsigned char*)
  21 #define __preg16        (volatile unsigned short*)
  22 #define __preg32        (volatile unsigned int*)
  23 #else
  24 #define __preg8
  25 #define __preg16
  26 #define __preg32
  27 #endif
  28
  29 // Embedded CPU peripheral registers
  30 // Note that many of the registers have different physical address for VR4181
  31
  32 // Bus Control Unit (BCU)
  33 #define VR4181_BCUCNTREG1       __preg16(KSEG1 + 0x0A000000)    /* BCU control register 1 (R/W) */
  34 #define VR4181_CMUCLKMSK        __preg16(KSEG1 + 0x0A000004)    /* Clock mask register (R/W) */
  35 #define VR4181_CMUCLKMSK_MSKCSUPCLK  0x0040
  36 #define VR4181_CMUCLKMSK_MSKAIUPCLK  0x0020
  37 #define VR4181_CMUCLKMSK_MSKPIUPCLK  0x0010
  38 #define VR4181_CMUCLKMSK_MSKADUPCLK  0x0008
  39 #define VR4181_CMUCLKMSK_MSKSIU18M   0x0004
  40 #define VR4181_CMUCLKMSK_MSKADU18M   0x0002
  41 #define VR4181_CMUCLKMSK_MSKUSB      0x0001
  42 #define VR4181_CMUCLKMSK_MSKSIU      VR4181_CMUCLKMSK_MSKSIU18M
  43 #define VR4181_BCUSPEEDREG      __preg16(KSEG1 + 0x0A00000C)    /* BCU access time parameter (R/W) */
  44 #define VR4181_BCURFCNTREG      __preg16(KSEG1 + 0x0A000010)    /* BCU refresh control register (R/W) */
  45 #define VR4181_REVIDREG         __preg16(KSEG1 + 0x0A000014)    /* Revision ID register (R) */
  46 #define VR4181_CLKSPEEDREG      __preg16(KSEG1 + 0x0A000018)    /* Clock speed register (R) */
  47 #define VR4181_EDOMCYTREG       __preg16(KSEG1 + 0x0A000300)    /* Memory cycle timing register (R/W) */
  48 #define VR4181_MEMCFG_REG       __preg16(KSEG1 + 0x0A000304)    /* Memory configuration register (R/W) */
  49 #define VR4181_MODE_REG         __preg16(KSEG1 + 0x0A000308)    /* SDRAM mode register (R/W) */
  50 #define VR4181_SDTIMINGREG      __preg16(KSEG1 + 0x0A00030C)    /* SDRAM timing register (R/W) */
  51
  52 // DMA Control Unit (DCU)
  53 #define VR4181_MICDEST1REG1     __preg16(KSEG1 + 0x0A000020)    /* Microphone destination 1 address register 1 (R/W) */
  54 #define VR4181_MICDEST1REG2     __preg16(KSEG1 + 0x0A000022)    /* Microphone destination 1 address register 2 (R/W) */
  55 #define VR4181_MICDEST2REG1     __preg16(KSEG1 + 0x0A000024)    /* Microphone destination 2 address register 1 (R/W) */
  56 #define VR4181_MICDEST2REG2     __preg16(KSEG1 + 0x0A000026)    /* Microphone destination 2 address register 2 (R/W) */
  57 #define VR4181_SPKRRC1REG1      __preg16(KSEG1 + 0x0A000028)    /* Speaker Source 1 address register 1 (R/W) */
  58 #define VR4181_SPKRRC1REG2      __preg16(KSEG1 + 0x0A00002A)    /* Speaker Source 1 address register 2 (R/W) */
  59 #define VR4181_SPKRRC2REG1      __preg16(KSEG1 + 0x0A00002C)    /* Speaker Source 2 address register 1 (R/W) */
  60 #define VR4181_SPKRRC2REG2      __preg16(KSEG1 + 0x0A00002E)    /* Speaker Source 2 address register 2 (R/W) */
  61 #define VR4181_DMARSTREG        __preg16(KSEG1 + 0x0A000040)    /* DMA Reset register (R/W) */
  62 #define VR4181_AIUDMAMSKREG     __preg16(KSEG1 + 0x0A000046)    /* Audio DMA mask register (R/W) */
  63 #define VR4181_USBDMAMSKREG     __preg16(KSEG1 + 0x0A000600)    /* USB DMA Mask register (R/W) */
  64 #define VR4181_USBRXS1AREG1     __preg16(KSEG1 + 0x0A000602)    /* USB Rx source 1 address register 1 (R/W) */
  65 #define VR4181_USBRXS1AREG2     __preg16(KSEG1 + 0x0A000604)    /* USB Rx source 1 address register 2 (R/W) */
  66 #define VR4181_USBRXS2AREG1     __preg16(KSEG1 + 0x0A000606)    /* USB Rx source 2 address register 1 (R/W) */
  67 #define VR4181_USBRXS2AREG2     __preg16(KSEG1 + 0x0A000608)    /* USB Rx source 2 address register 2 (R/W) */
  68 #define VR4181_USBTXS1AREG1     __preg16(KSEG1 + 0x0A00060A)    /* USB Tx source 1 address register 1 (R/W) */
  69 #define VR4181_USBTXS1AREG2     __preg16(KSEG1 + 0x0A00060C)    /* USB Tx source 1 address register 2 (R/W) */
  70 #define VR4181_USBTXS2AREG1     __preg16(KSEG1 + 0x0A00060E)    /* USB Tx source 2 address register 1 (R/W) */
  71 #define VR4181_USBTXS2AREG2     __preg16(KSEG1 + 0x0A000610)    /* USB Tx source 2 address register 2 (R/W) */
  72 #define VR4181_USBRXD1AREG1     __preg16(KSEG1 + 0x0A00062A)    /* USB Rx destination 1 address register 1 (R/W) */
  73 #define VR4181_USBRXD1AREG2     __preg16(KSEG1 + 0x0A00062C)    /* USB Rx destination 1 address register 2 (R/W) */
  74 #define VR4181_USBRXD2AREG1     __preg16(KSEG1 + 0x0A00062E)    /* USB Rx destination 2 address register 1 (R/W) */
  75 #define VR4181_USBRXD2AREG2     __preg16(KSEG1 + 0x0A000630)    /* USB Rx destination 2 address register 2 (R/W) */
  76 #define VR4181_USBTXD1AREG1     __preg16(KSEG1 + 0x0A000632)    /* USB Tx destination 1 address register 1 (R/W) */
  77 #define VR4181_USBTXD1AREG2     __preg16(KSEG1 + 0x0A000634)    /* USB Tx destination 1 address register 2 (R/W) */
  78 #define VR4181_USBTXD2AREG1     __preg16(KSEG1 + 0x0A000636)    /* USB Tx destination 2 address register 1 (R/W) */
  79 #define VR4181_USBTXD2AREG2     __preg16(KSEG1 + 0x0A000638)    /* USB Tx destination 2 address register 2 (R/W) */
  80 #define VR4181_RxRCLENREG       __preg16(KSEG1 + 0x0A000652)    /* USB Rx record length register (R/W) */
  81 #define VR4181_TxRCLENREG       __preg16(KSEG1 + 0x0A000654)    /* USB Tx record length register (R/W) */
  82 #define VR4181_MICRCLENREG      __preg16(KSEG1 + 0x0A000658)    /* Microphone record length register (R/W) */
  83 #define VR4181_SPKRCLENREG      __preg16(KSEG1 + 0x0A00065A)    /* Speaker record length register (R/W) */
  84 #define VR4181_USBCFGREG        __preg16(KSEG1 + 0x0A00065C)    /* USB configuration register (R/W) */
  85 #define VR4181_MICDMACFGREG     __preg16(KSEG1 + 0x0A00065E)    /* Microphone DMA configuration register (R/W) */
  86 #define VR4181_SPKDMACFGREG     __preg16(KSEG1 + 0x0A000660)    /* Speaker DMA configuration register (R/W) */
  87 #define VR4181_DMAITRQREG       __preg16(KSEG1 + 0x0A000662)    /* DMA interrupt request register (R/W) */
  88 #define VR4181_DMACLTREG        __preg16(KSEG1 + 0x0A000664)    /* DMA control register (R/W) */
  89 #define VR4181_DMAITMKREG       __preg16(KSEG1 + 0x0A000666)    /* DMA interrupt mask register (R/W) */
  90
  91 // ISA Bridge
  92 #define VR4181_ISABRGCTL        __preg16(KSEG1 + 0x0B0002C0)    /* ISA Bridge Control Register (R/W) */
  93 #define VR4181_ISABRGSTS        __preg16(KSEG1 + 0x0B0002C2)    /* ISA Bridge Status Register (R/W) */
  94 #define VR4181_XISACTL          __preg16(KSEG1 + 0x0B0002C4)    /* External ISA Control Register (R/W) */
  95
  96 // Clocked Serial Interface (CSI)
  97 #define VR4181_CSIMODE          __preg16(KSEG1 + 0x0B000900)    /* CSI Mode Register (R/W) */
  98 #define VR4181_CSIRXDATA        __preg16(KSEG1 + 0x0B000902)    /* CSI Receive Data Register (R) */
  99 #define VR4181_CSITXDATA        __preg16(KSEG1 + 0x0B000904)    /* CSI Transmit Data Register (R/W) */
 100 #define VR4181_CSILSTAT         __preg16(KSEG1 + 0x0B000906)    /* CSI Line Status Register (R/W) */
 101 #define VR4181_CSIINTMSK        __preg16(KSEG1 + 0x0B000908)    /* CSI Interrupt Mask Register (R/W) */
 102 #define VR4181_CSIINTSTAT       __preg16(KSEG1 + 0x0B00090a)    /* CSI Interrupt Status Register (R/W) */
 103 #define VR4181_CSITXBLEN        __preg16(KSEG1 + 0x0B00090c)    /* CSI Transmit Burst Length Register (R/W) */
 104 #define VR4181_CSIRXBLEN        __preg16(KSEG1 + 0x0B00090e)    /* CSI Receive Burst Length Register (R/W) */
 105
 106 // Interrupt Control Unit (ICU)
 107 #define VR4181_SYSINT1REG       __preg16(KSEG1 + 0x0A000080)    /* Level 1 System interrupt register 1 (R) */
 108 #define VR4181_MSYSINT1REG      __preg16(KSEG1 + 0x0A00008C)    /* Level 1 mask system interrupt register 1 (R/W) */
 109 #define VR4181_NMIREG           __preg16(KSEG1 + 0x0A000098)    /* NMI register (R/W) */
 110 #define VR4181_SOFTINTREG       __preg16(KSEG1 + 0x0A00009A)    /* Software interrupt register (R/W) */
 111 #define VR4181_SYSINT2REG       __preg16(KSEG1 + 0x0A000200)    /* Level 1 System interrupt register 2 (R) */
 112 #define VR4181_MSYSINT2REG      __preg16(KSEG1 + 0x0A000206)    /* Level 1 mask system interrupt register 2 (R/W) */
 113 #define VR4181_PIUINTREGro      __preg16(KSEG1 + 0x0B000082)    /* Level 2 PIU interrupt register (R) */
 114 #define VR4181_AIUINTREG        __preg16(KSEG1 + 0x0B000084)    /* Level 2 AIU interrupt register (R) */
 115 #define VR4181_MPIUINTREG       __preg16(KSEG1 + 0x0B00008E)    /* Level 2 mask PIU interrupt register (R/W) */
 116 #define VR4181_MAIUINTREG       __preg16(KSEG1 + 0x0B000090)    /* Level 2 mask AIU interrupt register (R/W) */
 117 #define VR4181_MKIUINTREG       __preg16(KSEG1 + 0x0B000092)    /* Level 2 mask KIU interrupt register (R/W) */
 118 #define VR4181_KIUINTREG        __preg16(KSEG1 + 0x0B000198)    /* Level 2 KIU interrupt register (R) */
 119
 120 // Power Management Unit (PMU)
 121 #define VR4181_PMUINTREG        __preg16(KSEG1 + 0x0B0000A0)    /* PMU Status Register (R/W) */
 122 #define VR4181_PMUINT_POWERSW  0x1      /* Power switch */
 123 #define VR4181_PMUINT_BATT     0x2      /* Low batt during normal operation */
 124 #define VR4181_PMUINT_DEADMAN  0x4      /* Deadman's switch */
 125 #define VR4181_PMUINT_RESET    0x8      /* Reset switch */
 126 #define VR4181_PMUINT_RTCRESET 0x10     /* RTC Reset */
 127 #define VR4181_PMUINT_TIMEOUT  0x20     /* HAL Timer Reset */
 128 #define VR4181_PMUINT_BATTLOW  0x100    /* Battery low */
 129 #define VR4181_PMUINT_RTC      0x200    /* RTC Alarm */
 130 #define VR4181_PMUINT_DCD      0x400    /* DCD# */
 131 #define VR4181_PMUINT_GPIO0    0x1000   /* GPIO0 */
 132 #define VR4181_PMUINT_GPIO1    0x2000   /* GPIO1 */
 133 #define VR4181_PMUINT_GPIO2    0x4000   /* GPIO2 */
 134 #define VR4181_PMUINT_GPIO3    0x8000   /* GPIO3 */
 135
 136 #define VR4181_PMUCNTREG        __preg16(KSEG1 + 0x0B0000A2)    /* PMU Control Register (R/W) */
 137 #define VR4181_PMUWAITREG       __preg16(KSEG1 + 0x0B0000A8)    /* PMU Wait Counter Register (R/W) */
 138 #define VR4181_PMUDIVREG        __preg16(KSEG1 + 0x0B0000AC)    /* PMU Divide Mode Register (R/W) */
 139 #define VR4181_DRAMHIBCTL       __preg16(KSEG1 + 0x0B0000B2)    /* DRAM Hibernate Control Register (R/W) */
 140
 141 // Real Time Clock Unit (RTC)
 142 #define VR4181_ETIMELREG        __preg16(KSEG1 + 0x0B0000C0)    /* Elapsed Time L Register (R/W) */
 143 #define VR4181_ETIMEMREG        __preg16(KSEG1 + 0x0B0000C2)    /* Elapsed Time M Register (R/W) */
 144 #define VR4181_ETIMEHREG        __preg16(KSEG1 + 0x0B0000C4)    /* Elapsed Time H Register (R/W) */
 145 #define VR4181_ECMPLREG         __preg16(KSEG1 + 0x0B0000C8)    /* Elapsed Compare L Register (R/W) */
 146 #define VR4181_ECMPMREG         __preg16(KSEG1 + 0x0B0000CA)    /* Elapsed Compare M Register (R/W) */
 147 #define VR4181_ECMPHREG         __preg16(KSEG1 + 0x0B0000CC)    /* Elapsed Compare H Register (R/W) */
 148 #define VR4181_RTCL1LREG        __preg16(KSEG1 + 0x0B0000D0)    /* RTC Long 1 L Register (R/W) */
 149 #define VR4181_RTCL1HREG        __preg16(KSEG1 + 0x0B0000D2)    /* RTC Long 1 H Register (R/W) */
 150 #define VR4181_RTCL1CNTLREG     __preg16(KSEG1 + 0x0B0000D4)    /* RTC Long 1 Count L Register (R) */
 151 #define VR4181_RTCL1CNTHREG     __preg16(KSEG1 + 0x0B0000D6)    /* RTC Long 1 Count H Register (R) */
 152 #define VR4181_RTCL2LREG        __preg16(KSEG1 + 0x0B0000D8)    /* RTC Long 2 L Register (R/W) */
 153 #define VR4181_RTCL2HREG        __preg16(KSEG1 + 0x0B0000DA)    /* RTC Long 2 H Register (R/W) */
 154 #define VR4181_RTCL2CNTLREG     __preg16(KSEG1 + 0x0B0000DC)    /* RTC Long 2 Count L Register (R) */
 155 #define VR4181_RTCL2CNTHREG     __preg16(KSEG1 + 0x0B0000DE)    /* RTC Long 2 Count H Register (R) */
 156 #define VR4181_RTCINTREG        __preg16(KSEG1 + 0x0B0001DE)    /* RTC Interrupt Register (R/W) */
 157
 158 // Deadman's Switch Unit (DSU)
 159 #define VR4181_DSUCNTREG        __preg16(KSEG1 + 0x0B0000E0)    /* DSU Control Register (R/W) */
 160 #define VR4181_DSUSETREG        __preg16(KSEG1 + 0x0B0000E2)    /* DSU Dead Time Set Register (R/W) */
 161 #define VR4181_DSUCLRREG        __preg16(KSEG1 + 0x0B0000E4)    /* DSU Clear Register (W) */
 162 #define VR4181_DSUTIMREG        __preg16(KSEG1 + 0x0B0000E6)    /* DSU Elapsed Time Register (R/W) */
 163
 164 // General Purpose I/O Unit (GIU)
 165 #define VR4181_GPMD0REG         __preg16(KSEG1 + 0x0B000300)    /* GPIO Mode 0 Register (R/W) */
 166 #define VR4181_GPMD1REG         __preg16(KSEG1 + 0x0B000302)    /* GPIO Mode 1 Register (R/W) */
 167 #define VR4181_GPMD2REG         __preg16(KSEG1 + 0x0B000304)    /* GPIO Mode 2 Register (R/W) */
 168 #define VR4181_GPMD3REG         __preg16(KSEG1 + 0x0B000306)    /* GPIO Mode 3 Register (R/W) */
 169 #define VR4181_GPDATHREG        __preg16(KSEG1 + 0x0B000308)    /* GPIO Data High Register (R/W) */
 170 #define VR4181_GPDATHREG_GPIO16  0x0001
 171 #define VR4181_GPDATHREG_GPIO17  0x0002
 172 #define VR4181_GPDATHREG_GPIO18  0x0004
 173 #define VR4181_GPDATHREG_GPIO19  0x0008
 174 #define VR4181_GPDATHREG_GPIO20  0x0010
 175 #define VR4181_GPDATHREG_GPIO21  0x0020
 176 #define VR4181_GPDATHREG_GPIO22  0x0040
 177 #define VR4181_GPDATHREG_GPIO23  0x0080
 178 #define VR4181_GPDATHREG_GPIO24  0x0100
 179 #define VR4181_GPDATHREG_GPIO25  0x0200
 180 #define VR4181_GPDATHREG_GPIO26  0x0400
 181 #define VR4181_GPDATHREG_GPIO27  0x0800
 182 #define VR4181_GPDATHREG_GPIO28  0x1000
 183 #define VR4181_GPDATHREG_GPIO29  0x2000
 184 #define VR4181_GPDATHREG_GPIO30  0x4000
 185 #define VR4181_GPDATHREG_GPIO31  0x8000
 186 #define VR4181_GPDATLREG        __preg16(KSEG1 + 0x0B00030A)    /* GPIO Data Low Register (R/W) */
 187 #define VR4181_GPDATLREG_GPIO0   0x0001
 188 #define VR4181_GPDATLREG_GPIO1   0x0002
 189 #define VR4181_GPDATLREG_GPIO2   0x0004
 190 #define VR4181_GPDATLREG_GPIO3   0x0008
 191 #define VR4181_GPDATLREG_GPIO4   0x0010
 192 #define VR4181_GPDATLREG_GPIO5   0x0020
 193 #define VR4181_GPDATLREG_GPIO6   0x0040
 194 #define VR4181_GPDATLREG_GPIO7   0x0080
 195 #define VR4181_GPDATLREG_GPIO8   0x0100
 196 #define VR4181_GPDATLREG_GPIO9   0x0200
 197 #define VR4181_GPDATLREG_GPIO10  0x0400
 198 #define VR4181_GPDATLREG_GPIO11  0x0800
 199 #define VR4181_GPDATLREG_GPIO12  0x1000
 200 #define VR4181_GPDATLREG_GPIO13  0x2000
 201 #define VR4181_GPDATLREG_GPIO14  0x4000
 202 #define VR4181_GPDATLREG_GPIO15  0x8000
 203 #define VR4181_GPINTEN          __preg16(KSEG1 + 0x0B00030C)    /* GPIO Interrupt Enable Register (R/W) */
 204 #define VR4181_GPINTMSK         __preg16(KSEG1 + 0x0B00030E)    /* GPIO Interrupt Mask Register (R/W) */
 205 #define VR4181_GPINTTYPH        __preg16(KSEG1 + 0x0B000310)    /* GPIO Interrupt Type High Register (R/W) */
 206 #define VR4181_GPINTTYPL        __preg16(KSEG1 + 0x0B000312)    /* GPIO Interrupt Type Low Register (R/W) */
 207 #define VR4181_GPINTSTAT        __preg16(KSEG1 + 0x0B000314)    /* GPIO Interrupt Status Register (R/W) */
 208 #define VR4181_GPHIBSTH         __preg16(KSEG1 + 0x0B000316)    /* GPIO Hibernate Pin State High Register (R/W) */
 209 #define VR4181_GPHIBSTL         __preg16(KSEG1 + 0x0B000318)    /* GPIO Hibernate Pin State Low Register (R/W) */
 210 #define VR4181_GPSICTL          __preg16(KSEG1 + 0x0B00031A)    /* GPIO Serial Interface Control Register (R/W) */
 211 #define VR4181_KEYEN            __preg16(KSEG1 + 0x0B00031C)    /* Keyboard Scan Pin Enable Register (R/W) */
 212 #define VR4181_PCS0STRA         __preg16(KSEG1 + 0x0B000320)    /* Programmable Chip Select [0] Start Address Register (R/W) */
 213 #define VR4181_PCS0STPA         __preg16(KSEG1 + 0x0B000322)    /* Programmable Chip Select [0] Stop Address Register (R/W) */
 214 #define VR4181_PCS0HIA          __preg16(KSEG1 + 0x0B000324)    /* Programmable Chip Select [0] High Address Register (R/W) */
 215 #define VR4181_PCS1STRA         __preg16(KSEG1 + 0x0B000326)    /* Programmable Chip Select [1] Start Address Register (R/W) */
 216 #define VR4181_PCS1STPA         __preg16(KSEG1 + 0x0B000328)    /* Programmable Chip Select [1] Stop Address Register (R/W) */
 217 #define VR4181_PCS1HIA          __preg16(KSEG1 + 0x0B00032A)    /* Programmable Chip Select [1] High Address Register (R/W) */
 218 #define VR4181_PCSMODE          __preg16(KSEG1 + 0x0B00032C)    /* Programmable Chip Select Mode Register (R/W) */
 219 #define VR4181_LCDGPMODE        __preg16(KSEG1 + 0x0B00032E)    /* LCD General Purpose Mode Register (R/W) */
 220 #define VR4181_MISCREG0         __preg16(KSEG1 + 0x0B000330)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
 221 #define VR4181_MISCREG1         __preg16(KSEG1 + 0x0B000332)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
 222 #define VR4181_MISCREG2         __preg16(KSEG1 + 0x0B000334)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
 223 #define VR4181_MISCREG3         __preg16(KSEG1 + 0x0B000336)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
 224 #define VR4181_MISCREG4         __preg16(KSEG1 + 0x0B000338)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
 225 #define VR4181_MISCREG5         __preg16(KSEG1 + 0x0B00033A)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
 226 #define VR4181_MISCREG6         __preg16(KSEG1 + 0x0B00033C)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
 227 #define VR4181_MISCREG7         __preg16(KSEG1 + 0x0B00033D)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
 228 #define VR4181_MISCREG8         __preg16(KSEG1 + 0x0B000340)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
 229 #define VR4181_MISCREG9         __preg16(KSEG1 + 0x0B000342)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
 230 #define VR4181_MISCREG10        __preg16(KSEG1 + 0x0B000344)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
 231 #define VR4181_MISCREG11        __preg16(KSEG1 + 0x0B000346)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
 232 #define VR4181_MISCREG12        __preg16(KSEG1 + 0x0B000348)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
 233 #define VR4181_MISCREG13        __preg16(KSEG1 + 0x0B00034A)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
 234 #define VR4181_MISCREG14        __preg16(KSEG1 + 0x0B00034C)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
 235 #define VR4181_MISCREG15        __preg16(KSEG1 + 0x0B00034E)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
 236 #define VR4181_SECIRQMASKL      VR4181_GPINTEN
 237 // No SECIRQMASKH for VR4181
 238
 239 // Touch Panel Interface Unit (PIU)
 240 #define VR4181_PIUCNTREG        __preg16(KSEG1 + 0x0B000122)    /* PIU Control register (R/W) */
 241 #define VR4181_PIUCNTREG_PIUSEQEN       0x0004
 242 #define VR4181_PIUCNTREG_PIUPWR         0x0002
 243 #define VR4181_PIUCNTREG_PADRST         0x0001
 244
 245 #define VR4181_PIUINTREG        __preg16(KSEG1 + 0x0B000124)    /* PIU Interrupt cause register (R/W) */
 246 #define VR4181_PIUINTREG_OVP            0x8000
 247 #define VR4181_PIUINTREG_PADCMD         0x0040
 248 #define VR4181_PIUINTREG_PADADP         0x0020
 249 #define VR4181_PIUINTREG_PADPAGE1       0x0010
 250 #define VR4181_PIUINTREG_PADPAGE0       0x0008
 251 #define VR4181_PIUINTREG_PADDLOST       0x0004
 252 #define VR4181_PIUINTREG_PENCHG         0x0001
 253
 254 #define VR4181_PIUSIVLREG       __preg16(KSEG1 + 0x0B000126)    /* PIU Data sampling interval register (R/W) */
 255 #define VR4181_PIUSTBLREG       __preg16(KSEG1 + 0x0B000128)    /* PIU A/D converter start delay register (R/W) */
 256 #define VR4181_PIUCMDREG        __preg16(KSEG1 + 0x0B00012A)    /* PIU A/D command register (R/W) */
 257 #define VR4181_PIUASCNREG       __preg16(KSEG1 + 0x0B000130)    /* PIU A/D port scan register (R/W) */
 258 #define VR4181_PIUAMSKREG       __preg16(KSEG1 + 0x0B000132)    /* PIU A/D scan mask register (R/W) */
 259 #define VR4181_PIUCIVLREG       __preg16(KSEG1 + 0x0B00013E)    /* PIU Check interval register (R) */
 260 #define VR4181_PIUPB00REG       __preg16(KSEG1 + 0x0B0002A0)    /* PIU Page 0 Buffer 0 register (R/W) */
 261 #define VR4181_PIUPB01REG       __preg16(KSEG1 + 0x0B0002A2)    /* PIU Page 0 Buffer 1 register (R/W) */
 262 #define VR4181_PIUPB02REG       __preg16(KSEG1 + 0x0B0002A4)    /* PIU Page 0 Buffer 2 register (R/W) */
 263 #define VR4181_PIUPB03REG       __preg16(KSEG1 + 0x0B0002A6)    /* PIU Page 0 Buffer 3 register (R/W) */
 264 #define VR4181_PIUPB10REG       __preg16(KSEG1 + 0x0B0002A8)    /* PIU Page 1 Buffer 0 register (R/W) */
 265 #define VR4181_PIUPB11REG       __preg16(KSEG1 + 0x0B0002AA)    /* PIU Page 1 Buffer 1 register (R/W) */
 266 #define VR4181_PIUPB12REG       __preg16(KSEG1 + 0x0B0002AC)    /* PIU Page 1 Buffer 2 register (R/W) */
 267 #define VR4181_PIUPB13REG       __preg16(KSEG1 + 0x0B0002AE)    /* PIU Page 1 Buffer 3 register (R/W) */
 268 #define VR4181_PIUAB0REG        __preg16(KSEG1 + 0x0B0002B0)    /* PIU A/D scan Buffer 0 register (R/W) */
 269 #define VR4181_PIUAB1REG        __preg16(KSEG1 + 0x0B0002B2)    /* PIU A/D scan Buffer 1 register (R/W) */
 270 #define VR4181_PIUAB2REG        __preg16(KSEG1 + 0x0B0002B4)    /* PIU A/D scan Buffer 2 register (R/W) */
 271 #define VR4181_PIUAB3REG        __preg16(KSEG1 + 0x0B0002B6)    /* PIU A/D scan Buffer 3 register (R/W) */
 272 #define VR4181_PIUPB04REG       __preg16(KSEG1 + 0x0B0002BC)    /* PIU Page 0 Buffer 4 register (R/W) */
 273 #define VR4181_PIUPB14REG       __preg16(KSEG1 + 0x0B0002BE)    /* PIU Page 1 Buffer 4 register (R/W) */
 274
 275 // Audio Interface Unit (AIU)
 276 #define VR4181_SODATREG         __preg16(KSEG1 + 0x0B000166)    /* Speaker Output Data Register (R/W) */
 277 #define VR4181_SCNTREG          __preg16(KSEG1 + 0x0B000168)    /* Speaker Output Control Register (R/W) */
 278 #define VR4181_MIDATREG         __preg16(KSEG1 + 0x0B000170)    /* Mike Input Data Register (R/W) */
 279 #define VR4181_MCNTREG          __preg16(KSEG1 + 0x0B000172)    /* Mike Input Control Register (R/W) */
 280 #define VR4181_DVALIDREG        __preg16(KSEG1 + 0x0B000178)    /* Data Valid Register (R/W) */
 281 #define VR4181_SEQREG           __preg16(KSEG1 + 0x0B00017A)    /* Sequential Register (R/W) */
 282 #define VR4181_INTREG           __preg16(KSEG1 + 0x0B00017C)    /* Interrupt Register (R/W) */
 283 #define VR4181_SDMADATREG       __preg16(KSEG1 + 0x0B000160)    /* Speaker DMA Data Register (R/W) */
 284 #define VR4181_MDMADATREG       __preg16(KSEG1 + 0x0B000162)    /* Microphone DMA Data Register (R/W) */
 285 #define VR4181_DAVREF_SETUP     __preg16(KSEG1 + 0x0B000164)    /* DAC Vref setup register (R/W) */
 286 #define VR4181_SCNVC_END        __preg16(KSEG1 + 0x0B00016E)    /* Speaker sample rate control (R/W) */
 287 #define VR4181_MIDATREG         __preg16(KSEG1 + 0x0B000170)    /* Microphone Input Data Register (R/W) */
 288 #define VR4181_MCNTREG          __preg16(KSEG1 + 0x0B000172)    /* Microphone Input Control Register (R/W) */
 289 #define VR4181_MCNVC_END        __preg16(KSEG1 + 0x0B00017E)    /* Microphone sample rate control (R/W) */
 290
 291 // Keyboard Interface Unit (KIU)
 292 #define VR4181_KIUDAT0          __preg16(KSEG1 + 0x0B000180)    /* KIU Data0 Register (R/W) */
 293 #define VR4181_KIUDAT1          __preg16(KSEG1 + 0x0B000182)    /* KIU Data1 Register (R/W) */
 294 #define VR4181_KIUDAT2          __preg16(KSEG1 + 0x0B000184)    /* KIU Data2 Register (R/W) */
 295 #define VR4181_KIUDAT3          __preg16(KSEG1 + 0x0B000186)    /* KIU Data3 Register (R/W) */
 296 #define VR4181_KIUDAT4          __preg16(KSEG1 + 0x0B000188)    /* KIU Data4 Register (R/W) */
 297 #define VR4181_KIUDAT5          __preg16(KSEG1 + 0x0B00018A)    /* KIU Data5 Register (R/W) */
 298 #define VR4181_KIUSCANREP       __preg16(KSEG1 + 0x0B000190)    /* KIU Scan/Repeat Register (R/W) */
 299 #define VR4181_KIUSCANREP_KEYEN      0x8000
 300 #define VR4181_KIUSCANREP_SCANSTP    0x0008
 301 #define VR4181_KIUSCANREP_SCANSTART  0x0004
 302 #define VR4181_KIUSCANREP_ATSTP      0x0002
 303 #define VR4181_KIUSCANREP_ATSCAN     0x0001
 304 #define VR4181_KIUSCANS         __preg16(KSEG1 + 0x0B000192)    /* KIU Scan Status Register (R) */
 305 #define VR4181_KIUWKS           __preg16(KSEG1 + 0x0B000194)    /* KIU Wait Keyscan Stable Register (R/W) */
 306 #define VR4181_KIUWKI           __preg16(KSEG1 + 0x0B000196)    /* KIU Wait Keyscan Interval Register (R/W) */
 307 #define VR4181_KIUINT           __preg16(KSEG1 + 0x0B000198)    /* KIU Interrupt Register (R/W) */
 308 #define VR4181_KIUINT_KDATLOST       0x0004
 309 #define VR4181_KIUINT_KDATRDY        0x0002
 310 #define VR4181_KIUINT_SCANINT        0x0001
 311 #define VR4181_KIUDAT6          __preg16(KSEG1 + 0x0B00018C)    /* Scan Line 6 Key Data Register (R) */
 312 #define VR4181_KIUDAT7          __preg16(KSEG1 + 0x0B00018E)    /* Scan Line 7 Key Data Register (R) */
 313
 314 // CompactFlash Controller
 315 #define VR4181_PCCARDINDEX      __preg8(KSEG1 + 0x0B0008E0)     /* PC Card Controller Index Register */
 316 #define VR4181_PCCARDDATA       __preg8(KSEG1 + 0x0B0008E1)     /* PC Card Controller Data Register */
 317 #define VR4181_INTSTATREG       __preg16(KSEG1 + 0x0B0008F8)    /* Interrupt Status Register (R/W) */
 318 #define VR4181_INTMSKREG        __preg16(KSEG1 + 0x0B0008FA)    /* Interrupt Mask Register (R/W) */
 319 #define VR4181_CFG_REG_1        __preg16(KSEG1 + 0x0B0008FE)    /* Configuration Register 1 */
 320
 321 // LED Control Unit (LED)
 322 #define VR4181_LEDHTSREG        __preg16(KSEG1 + 0x0B000240)    /* LED H Time Set register (R/W) */
 323 #define VR4181_LEDLTSREG        __preg16(KSEG1 + 0x0B000242)    /* LED L Time Set register (R/W) */
 324 #define VR4181_LEDCNTREG        __preg16(KSEG1 + 0x0B000248)    /* LED Control register (R/W) */
 325 #define VR4181_LEDASTCREG       __preg16(KSEG1 + 0x0B00024A)    /* LED Auto Stop Time Count register (R/W) */
 326 #define VR4181_LEDINTREG        __preg16(KSEG1 + 0x0B00024C)    /* LED Interrupt register (R/W) */
 327
 328 // Serial Interface Unit (SIU / SIU1 and SIU2)
 329 #define VR4181_SIURB            __preg8(KSEG1 + 0x0C000010)     /* Receiver Buffer Register (Read) DLAB = 0 (R) */
 330 #define VR4181_SIUTH            __preg8(KSEG1 + 0x0C000010)     /* Transmitter Holding Register (Write) DLAB = 0 (W) */
 331 #define VR4181_SIUDLL           __preg8(KSEG1 + 0x0C000010)     /* Divisor Latch (Least Significant Byte) DLAB = 1 (R/W) */
 332 #define VR4181_SIUIE            __preg8(KSEG1 + 0x0C000011)     /* Interrupt Enable DLAB = 0 (R/W) */
 333 #define VR4181_SIUDLM           __preg8(KSEG1 + 0x0C000011)     /* Divisor Latch (Most Significant Byte) DLAB = 1 (R/W) */
 334 #define VR4181_SIUIID           __preg8(KSEG1 + 0x0C000012)     /* Interrupt Identification Register (Read) (R) */
 335 #define VR4181_SIUFC            __preg8(KSEG1 + 0x0C000012)     /* FIFO Control Register (Write) (W) */
 336 #define VR4181_SIULC            __preg8(KSEG1 + 0x0C000013)     /* Line Control Register (R/W) */
 337 #define VR4181_SIUMC            __preg8(KSEG1 + 0x0C000014)     /* MODEM Control Register (R/W) */
 338 #define VR4181_SIULS            __preg8(KSEG1 + 0x0C000015)     /* Line Status Register (R/W) */
 339 #define VR4181_SIUMS            __preg8(KSEG1 + 0x0C000016)     /* MODEM Status Register (R/W) */
 340 #define VR4181_SIUSC            __preg8(KSEG1 + 0x0C000017)     /* Scratch Register (R/W) */
 341 #define VR4181_SIURESET         __preg8(KSEG1 + 0x0C000019)     /* SIU Reset Register (R/W) */
 342 #define VR4181_SIUACTMSK        __preg8(KSEG1 + 0x0C00001C)     /* SIU Activity Mask (R/W) */
 343 #define VR4181_SIUACTTMR        __preg8(KSEG1 + 0x0C00001E)     /* SIU Activity Timer (R/W) */
 344 #define VR4181_SIURB_2          __preg8(KSEG1 + 0x0C000000)     /* Receive Buffer Register (Read) (R) */
 345 #define VR4181_SIUTH_2          __preg8(KSEG1 + 0x0C000000)     /* Transmitter Holding Register (Write) (W) */
 346 #define VR4181_SIUDLL_2         __preg8(KSEG1 + 0x0C000000)     /* Divisor Latch (Least Significant Byte) (R/W) */
 347 #define VR4181_SIUIE_2          __preg8(KSEG1 + 0x0C000001)     /* Interrupt Enable (DLAB = 0) (R/W) */
 348 #define VR4181_SIUDLM_2         __preg8(KSEG1 + 0x0C000001)     /* Divisor Latch (Most Significant Byte) (DLAB = 1) (R/W) */
 349 #define VR4181_SIUIID_2         __preg8(KSEG1 + 0x0C000002)     /* Interrupt Identification Register (Read) (R) */
 350 #define VR4181_SIUFC_2          __preg8(KSEG1 + 0x0C000002)     /* FIFO Control Register (Write) (W) */
 351 #define VR4181_SIULC_2          __preg8(KSEG1 + 0x0C000003)     /* Line Control Register (R/W) */
 352 #define VR4181_SIUMC_2          __preg8(KSEG1 + 0x0C000004)     /* Modem Control Register (R/W) */
 353 #define VR4181_SIULS_2          __preg8(KSEG1 + 0x0C000005)     /* Line Status Register (R/W) */
 354 #define VR4181_SIUMS_2          __preg8(KSEG1 + 0x0C000006)     /* Modem Status Register (R/W) */
 355 #define VR4181_SIUSC_2          __preg8(KSEG1 + 0x0C000007)     /* Scratch Register (R/W) */
 356 #define VR4181_SIUIRSEL_2       __preg8(KSEG1 + 0x0C000008)     /* SIU IrDA Selectot (R/W) */
 357 #define VR4181_SIURESET_2       __preg8(KSEG1 + 0x0C000009)     /* SIU Reset Register (R/W) */
 358 #define VR4181_SIUCSEL_2        __preg8(KSEG1 + 0x0C00000A)     /* IrDA Echo-back Control (R/W) */
 359 #define VR4181_SIUACTMSK_2      __preg8(KSEG1 + 0x0C00000C)     /* SIU Activity Mask Register (R/W) */
 360 #define VR4181_SIUACTTMR_2      __preg8(KSEG1 + 0x0C00000E)     /* SIU Activity Timer Register (R/W) */
 361
 362
 363 // USB Module
 364 #define VR4181_USBINFIFO        __preg16(KSEG1 + 0x0B000780)    /* USB Bulk Input FIFO (Bulk In End Point) (W) */
 365 #define VR4181_USBOUTFIFO       __preg16(KSEG1 + 0x0B000782)    /* USB Bulk Output FIFO (Bulk Out End Point) (R) */
 366 #define VR4181_USBCTLFIFO       __preg16(KSEG1 + 0x0B000784)    /* USB Control FIFO (Control End Point) (W) */
 367 #define VR4181_USBSTAT          __preg16(KSEG1 + 0x0B000786)    /* Interrupt Status Register (R/W) */
 368 #define VR4181_USBINTMSK        __preg16(KSEG1 + 0x0B000788)    /* Interrupt Mask Register (R/W) */
 369 #define VR4181_USBCTLREG        __preg16(KSEG1 + 0x0B00078A)    /* Control Register (R/W) */
 370 #define VR4181_USBSTPREG        __preg16(KSEG1 + 0x0B00078C)    /* USB Transfer Stop Register (R/W) */
 371
 372 // LCD Controller
 373 #define VR4181_HRTOTALREG       __preg16(KSEG1 + 0x0A000400)    /* Horizontal total Register (R/W) */
 374 #define VR4181_HRVISIBREG       __preg16(KSEG1 + 0x0A000402)    /* Horizontal Visible Register (R/W) */
 375 #define VR4181_LDCLKSTREG       __preg16(KSEG1 + 0x0A000404)    /* Load clock start Register (R/W) */
 376 #define VR4181_LDCLKNDREG       __preg16(KSEG1 + 0x0A000406)    /* Load clock end Register (R/W) */
 377 #define VR4181_VRTOTALREG       __preg16(KSEG1 + 0x0A000408)    /* Vertical Total Register (R/W) */
 378 #define VR4181_VRVISIBREG       __preg16(KSEG1 + 0x0A00040A)    /* Vertical Visible Register (R/W) */
 379 #define VR4181_FVSTARTREG       __preg16(KSEG1 + 0x0A00040C)    /* FLM vertical start Register (R/W) */
 380 #define VR4181_FVENDREG         __preg16(KSEG1 + 0x0A00040E)    /* FLM vertical end Register (R/W) */
 381 #define VR4181_LCDCTRLREG       __preg16(KSEG1 + 0x0A000410)    /* LCD control Register (R/W) */
 382 #define VR4181_LCDINRQREG       __preg16(KSEG1 + 0x0A000412)    /* LCD Interrupt request Register (R/W) */
 383 #define VR4181_LCDCFGREG0       __preg16(KSEG1 + 0x0A000414)    /* LCD Configuration Register 0 (R/W) */
 384 #define VR4181_LCDCFGREG1       __preg16(KSEG1 + 0x0A000416)    /* LCD Configuration Register 1 (R/W) */
 385 #define VR4181_FBSTAD1REG       __preg16(KSEG1 + 0x0A000418)    /* Frame Buffer Start Address 1 Register (R/W) */
 386 #define VR4181_FBSTAD2REG       __preg16(KSEG1 + 0x0A00041A)    /* Frame Buffer Start Address 2 Register (R/W) */
 387 #define VR4181_FBNDAD1REG       __preg16(KSEG1 + 0x0A000420)    /* Frame Buffer End Address 1 Register (R/W) */
 388 #define VR4181_FBNDAD2REG       __preg16(KSEG1 + 0x0A000422)    /* Frame Buffer End Address 2 register (R/W) */
 389 #define VR4181_FHSTARTREG       __preg16(KSEG1 + 0x0A000424)    /* FLM horizontal Start Register (R/W) */
 390 #define VR4181_FHENDREG         __preg16(KSEG1 + 0x0A000426)    /* FLM horizontal End Register (R/W) */
 391 #define VR4181_PWRCONREG1       __preg16(KSEG1 + 0x0A000430)    /* Power Control register 1 (R/W) */
 392 #define VR4181_PWRCONREG2       __preg16(KSEG1 + 0x0A000432)    /* Power Control register 2 (R/W) */
 393 #define VR4181_LCDIMSKREG       __preg16(KSEG1 + 0x0A000434)    /* LCD Interrupt Mask register (R/W) */
 394 #define VR4181_CPINDCTREG       __preg16(KSEG1 + 0x0A00047E)    /* Color palette Index and control Register (R/W) */
 395 #define VR4181_CPALDATREG       __preg32(KSEG1 + 0x0A000480)    /* Color palette data register (32bits Register) (R/W) */
 396
 397 // physical address spaces
 398 #define VR4181_LCD             0x0a000000
 399 #define VR4181_INTERNAL_IO_2   0x0b000000
 400 #define VR4181_INTERNAL_IO_1   0x0c000000
 401 #define VR4181_ISA_MEM         0x10000000
 402 #define VR4181_ISA_IO          0x14000000
 403 #define VR4181_ROM             0x18000000
 404
 405 // This is the base address for IO port decoding to which the 16 bit IO port address
 406 // is added.  Defining it to 0 will usually cause a kernel oops any time port IO is
 407 // attempted, which can be handy for turning up parts of the kernel that make
 408 // incorrect architecture assumptions (by assuming that everything acts like a PC),
 409 // but we need it correctly defined to use the PCMCIA/CF controller:
 410 #define VR4181_PORT_BASE        (KSEG1 + VR4181_ISA_IO)
 411 #define VR4181_ISAMEM_BASE      (KSEG1 + VR4181_ISA_MEM)
 412
 413 #endif /* __ASM_VR4181_VR4181_H */