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ARM: OMAP: McBSP: Prepare for splitting into omap1 and omap2 code
[linux-ginger.git] / drivers / net / tc35815.c
blobb07b8cbadeaf8eb4a34dbbfe848ad5499f2a628b
1 /*
2 * tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux.
3 *
4 * Based on skelton.c by Donald Becker.
5 *
6 * This driver is a replacement of older and less maintained version.
7 * This is a header of the older version:
8 * -----<snip>-----
9 * Copyright 2001 MontaVista Software Inc.
10 * Author: MontaVista Software, Inc.
11 * ahennessy@mvista.com
12 * Copyright (C) 2000-2001 Toshiba Corporation
13 * static const char *version =
14 * "tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n";
15 * -----<snip>-----
16 *
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
19 * for more details.
20 *
21 * (C) Copyright TOSHIBA CORPORATION 2004-2005
22 * All Rights Reserved.
23 */
24
25 #ifdef TC35815_NAPI
26 #define DRV_VERSION "1.37-NAPI"
27 #else
28 #define DRV_VERSION "1.37"
29 #endif
30 static const char *version = "tc35815.c:v" DRV_VERSION "\n";
31 #define MODNAME "tc35815"
32
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/types.h>
36 #include <linux/fcntl.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
39 #include <linux/in.h>
40 #include <linux/slab.h>
41 #include <linux/string.h>
42 #include <linux/spinlock.h>
43 #include <linux/errno.h>
44 #include <linux/init.h>
45 #include <linux/netdevice.h>
46 #include <linux/etherdevice.h>
47 #include <linux/skbuff.h>
48 #include <linux/delay.h>
49 #include <linux/pci.h>
50 #include <linux/phy.h>
51 #include <linux/workqueue.h>
52 #include <linux/platform_device.h>
53 #include <asm/io.h>
54 #include <asm/byteorder.h>
55
56 /* First, a few definitions that the brave might change. */
57
58 #define GATHER_TXINT /* On-Demand Tx Interrupt */
59 #define WORKAROUND_LOSTCAR
60 #define WORKAROUND_100HALF_PROMISC
61 /* #define TC35815_USE_PACKEDBUFFER */
62
63 enum tc35815_chiptype {
64 TC35815CF = 0,
65 TC35815_NWU,
66 TC35815_TX4939,
67 };
68
69 /* indexed by tc35815_chiptype, above */
70 static const struct {
71 const char *name;
72 } chip_info[] __devinitdata = {
73 { "TOSHIBA TC35815CF 10/100BaseTX" },
74 { "TOSHIBA TC35815 with Wake on LAN" },
75 { "TOSHIBA TC35815/TX4939" },
76 };
77
78 static const struct pci_device_id tc35815_pci_tbl[] = {
79 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF), .driver_data = TC35815CF },
80 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU), .driver_data = TC35815_NWU },
81 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 },
82 {0,}
83 };
84 MODULE_DEVICE_TABLE(pci, tc35815_pci_tbl);
85
86 /* see MODULE_PARM_DESC */
87 static struct tc35815_options {
88 int speed;
89 int duplex;
90 } options;
91
92 /*
93 * Registers
94 */
95 struct tc35815_regs {
96 __u32 DMA_Ctl; /* 0x00 */
97 __u32 TxFrmPtr;
98 __u32 TxThrsh;
99 __u32 TxPollCtr;
100 __u32 BLFrmPtr;
101 __u32 RxFragSize;
102 __u32 Int_En;
103 __u32 FDA_Bas;
104 __u32 FDA_Lim; /* 0x20 */
105 __u32 Int_Src;
106 __u32 unused0[2];
107 __u32 PauseCnt;
108 __u32 RemPauCnt;
109 __u32 TxCtlFrmStat;
110 __u32 unused1;
111 __u32 MAC_Ctl; /* 0x40 */
112 __u32 CAM_Ctl;
113 __u32 Tx_Ctl;
114 __u32 Tx_Stat;
115 __u32 Rx_Ctl;
116 __u32 Rx_Stat;
117 __u32 MD_Data;
118 __u32 MD_CA;
119 __u32 CAM_Adr; /* 0x60 */
120 __u32 CAM_Data;
121 __u32 CAM_Ena;
122 __u32 PROM_Ctl;
123 __u32 PROM_Data;
124 __u32 Algn_Cnt;
125 __u32 CRC_Cnt;
126 __u32 Miss_Cnt;
127 };
128
129 /*
130 * Bit assignments
131 */
132 /* DMA_Ctl bit asign ------------------------------------------------------- */
133 #define DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */
134 #define DMA_RxAlign_1 0x00400000
135 #define DMA_RxAlign_2 0x00800000
136 #define DMA_RxAlign_3 0x00c00000
137 #define DMA_M66EnStat 0x00080000 /* 1:66MHz Enable State */
138 #define DMA_IntMask 0x00040000 /* 1:Interupt mask */
139 #define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */
140 #define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */
141 #define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */
142 #define DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */
143 #define DMA_TestMode 0x00002000 /* 1:Test Mode */
144 #define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */
145 #define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */
146
147 /* RxFragSize bit asign ---------------------------------------------------- */
148 #define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */
149 #define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */
150
151 /* MAC_Ctl bit asign ------------------------------------------------------- */
152 #define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */
153 #define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */
154 #define MAC_MissRoll 0x00000400 /* 1:Missed Roll */
155 #define MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */
156 #define MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */
157 #define MAC_Conn_10M 0x00000020 /*01: (10Mbps endec)*/
158 #define MAC_Conn_Mll 0x00000040 /*10: (Mll clock) */
159 #define MAC_MacLoop 0x00000010 /* 1:MAC Loopback */
160 #define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */
161 #define MAC_Reset 0x00000004 /* 1:Software Reset */
162 #define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */
163 #define MAC_HaltReq 0x00000001 /* 1:Halt request */
164
165 /* PROM_Ctl bit asign ------------------------------------------------------ */
166 #define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */
167 #define PROM_Read 0x00004000 /*10:Read operation */
168 #define PROM_Write 0x00002000 /*01:Write operation */
169 #define PROM_Erase 0x00006000 /*11:Erase operation */
170 /*00:Enable or Disable Writting, */
171 /* as specified in PROM_Addr. */
172 #define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */
173 /*00xxxx: disable */
174
175 /* CAM_Ctl bit asign ------------------------------------------------------- */
176 #define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */
177 #define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/
178 /* accept other */
179 #define CAM_BroadAcc 0x00000004 /* 1:Broadcast assept */
180 #define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */
181 #define CAM_StationAcc 0x00000001 /* 1:unicast accept */
182
183 /* CAM_Ena bit asign ------------------------------------------------------- */
184 #define CAM_ENTRY_MAX 21 /* CAM Data entry max count */
185 #define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */
186 #define CAM_Ena_Bit(index) (1 << (index))
187 #define CAM_ENTRY_DESTINATION 0
188 #define CAM_ENTRY_SOURCE 1
189 #define CAM_ENTRY_MACCTL 20
190
191 /* Tx_Ctl bit asign -------------------------------------------------------- */
192 #define Tx_En 0x00000001 /* 1:Transmit enable */
193 #define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */
194 #define Tx_NoPad 0x00000004 /* 1:Suppress Padding */
195 #define Tx_NoCRC 0x00000008 /* 1:Suppress Padding */
196 #define Tx_FBack 0x00000010 /* 1:Fast Back-off */
197 #define Tx_EnUnder 0x00000100 /* 1:Enable Underrun */
198 #define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */
199 #define Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */
200 #define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */
201 #define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */
202 #define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */
203 #define Tx_EnComp 0x00004000 /* 1:Enable Completion */
204
205 /* Tx_Stat bit asign ------------------------------------------------------- */
206 #define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */
207 #define Tx_ExColl 0x00000010 /* Excessive Collision */
208 #define Tx_TXDefer 0x00000020 /* Transmit Defered */
209 #define Tx_Paused 0x00000040 /* Transmit Paused */
210 #define Tx_IntTx 0x00000080 /* Interrupt on Tx */
211 #define Tx_Under 0x00000100 /* Underrun */
212 #define Tx_Defer 0x00000200 /* Deferral */
213 #define Tx_NCarr 0x00000400 /* No Carrier */
214 #define Tx_10Stat 0x00000800 /* 10Mbps Status */
215 #define Tx_LateColl 0x00001000 /* Late Collision */
216 #define Tx_TxPar 0x00002000 /* Tx Parity Error */
217 #define Tx_Comp 0x00004000 /* Completion */
218 #define Tx_Halted 0x00008000 /* Tx Halted */
219 #define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */
220
221 /* Rx_Ctl bit asign -------------------------------------------------------- */
222 #define Rx_EnGood 0x00004000 /* 1:Enable Good */
223 #define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */
224 #define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */
225 #define Rx_EnOver 0x00000400 /* 1:Enable OverFlow */
226 #define Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */
227 #define Rx_EnAlign 0x00000100 /* 1:Enable Alignment */
228 #define Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */
229 #define Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */
230 #define Rx_ShortEn 0x00000008 /* 1:Short Enable */
231 #define Rx_LongEn 0x00000004 /* 1:Long Enable */
232 #define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */
233 #define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */
234
235 /* Rx_Stat bit asign ------------------------------------------------------- */
236 #define Rx_Halted 0x00008000 /* Rx Halted */
237 #define Rx_Good 0x00004000 /* Rx Good */
238 #define Rx_RxPar 0x00002000 /* Rx Parity Error */
239 /* 0x00001000 not use */
240 #define Rx_LongErr 0x00000800 /* Rx Long Error */
241 #define Rx_Over 0x00000400 /* Rx Overflow */
242 #define Rx_CRCErr 0x00000200 /* Rx CRC Error */
243 #define Rx_Align 0x00000100 /* Rx Alignment Error */
244 #define Rx_10Stat 0x00000080 /* Rx 10Mbps Status */
245 #define Rx_IntRx 0x00000040 /* Rx Interrupt */
246 #define Rx_CtlRecd 0x00000020 /* Rx Control Receive */
247
248 #define Rx_Stat_Mask 0x0000EFC0 /* Rx All Status Mask */
249
250 /* Int_En bit asign -------------------------------------------------------- */
251 #define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */
252 #define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Ctl Complete Enable */
253 #define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */
254 #define Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */
255 #define Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */
256 #define Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */
257 #define Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */
258 #define Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */
259 #define Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */
260 #define Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */
261 #define Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */
262 #define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */
263 /* Exhausted Enable */
264
265 /* Int_Src bit asign ------------------------------------------------------- */
266 #define Int_NRabt 0x00004000 /* 1:Non Recoverable error */
267 #define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */
268 #define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */
269 #define Int_FDAEx 0x00000800 /* 1:FDA Empty & Clear */
270 #define Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */
271 #define Int_IntCmp 0x00000200 /* 1:MAC control packet complete */
272 #define Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */
273 #define Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */
274 #define Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */
275 #define Int_SWInt 0x00000020 /* 1:Software request & Clear */
276 #define Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */
277 #define Int_IntFDAEx 0x00000008 /* 1:FDA Empty & Clear */
278 #define Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */
279 #define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */
280 #define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */
281
282 /* MD_CA bit asign --------------------------------------------------------- */
283 #define MD_CA_PreSup 0x00001000 /* 1:Preamble Supress */
284 #define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */
285 #define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */
286
287
288 /*
289 * Descriptors
290 */
291
292 /* Frame descripter */
293 struct FDesc {
294 volatile __u32 FDNext;
295 volatile __u32 FDSystem;
296 volatile __u32 FDStat;
297 volatile __u32 FDCtl;
298 };
299
300 /* Buffer descripter */
301 struct BDesc {
302 volatile __u32 BuffData;
303 volatile __u32 BDCtl;
304 };
305
306 #define FD_ALIGN 16
307
308 /* Frame Descripter bit asign ---------------------------------------------- */
309 #define FD_FDLength_MASK 0x0000FFFF /* Length MASK */
310 #define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */
311 #define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */
312 #define FD_FrmOpt_BigEndian 0x40000000 /* Tx/Rx */
313 #define FD_FrmOpt_IntTx 0x20000000 /* Tx only */
314 #define FD_FrmOpt_NoCRC 0x10000000 /* Tx only */
315 #define FD_FrmOpt_NoPadding 0x08000000 /* Tx only */
316 #define FD_FrmOpt_Packing 0x04000000 /* Rx only */
317 #define FD_CownsFD 0x80000000 /* FD Controller owner bit */
318 #define FD_Next_EOL 0x00000001 /* FD EOL indicator */
319 #define FD_BDCnt_SHIFT 16
320
321 /* Buffer Descripter bit asign --------------------------------------------- */
322 #define BD_BuffLength_MASK 0x0000FFFF /* Recieve Data Size */
323 #define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */
324 #define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */
325 #define BD_CownsBD 0x80000000 /* BD Controller owner bit */
326 #define BD_RxBDID_SHIFT 16
327 #define BD_RxBDSeqN_SHIFT 24
328
329
330 /* Some useful constants. */
331 #undef NO_CHECK_CARRIER /* Does not check No-Carrier with TP */
332
333 #ifdef NO_CHECK_CARRIER
334 #define TX_CTL_CMD (Tx_EnComp | Tx_EnTxPar | Tx_EnLateColl | \
335 Tx_EnExColl | Tx_EnExDefer | Tx_EnUnder | \
336 Tx_En) /* maybe 0x7b01 */
337 #else
338 #define TX_CTL_CMD (Tx_EnComp | Tx_EnTxPar | Tx_EnLateColl | \
339 Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \
340 Tx_En) /* maybe 0x7b01 */
341 #endif
342 #define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \
343 | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */
344 #define INT_EN_CMD (Int_NRAbtEn | \
345 Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \
346 Int_SSysErrEn | Int_RMasAbtEn | Int_RTargAbtEn | \
347 Int_STargAbtEn | \
348 Int_BLExEn | Int_FDAExEn) /* maybe 0xb7f*/
349 #define DMA_CTL_CMD DMA_BURST_SIZE
350 #define HAVE_DMA_RXALIGN(lp) likely((lp)->chiptype != TC35815CF)
351
352 /* Tuning parameters */
353 #define DMA_BURST_SIZE 32
354 #define TX_THRESHOLD 1024
355 /* used threshold with packet max byte for low pci transfer ability.*/
356 #define TX_THRESHOLD_MAX 1536
357 /* setting threshold max value when overrun error occured this count. */
358 #define TX_THRESHOLD_KEEP_LIMIT 10
359
360 /* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */
361 #ifdef TC35815_USE_PACKEDBUFFER
362 #define FD_PAGE_NUM 2
363 #define RX_BUF_NUM 8 /* >= 2 */
364 #define RX_FD_NUM 250 /* >= 32 */
365 #define TX_FD_NUM 128
366 #define RX_BUF_SIZE PAGE_SIZE
367 #else /* TC35815_USE_PACKEDBUFFER */
368 #define FD_PAGE_NUM 4
369 #define RX_BUF_NUM 128 /* < 256 */
370 #define RX_FD_NUM 256 /* >= 32 */
371 #define TX_FD_NUM 128
372 #if RX_CTL_CMD & Rx_LongEn
373 #define RX_BUF_SIZE PAGE_SIZE
374 #elif RX_CTL_CMD & Rx_StripCRC
375 #define RX_BUF_SIZE ALIGN(ETH_FRAME_LEN + 4 + 2, 32) /* +2: reserve */
376 #else
377 #define RX_BUF_SIZE ALIGN(ETH_FRAME_LEN + 2, 32) /* +2: reserve */
378 #endif
379 #endif /* TC35815_USE_PACKEDBUFFER */
380 #define RX_FD_RESERVE (2 / 2) /* max 2 BD per RxFD */
381 #define NAPI_WEIGHT 16
382
383 struct TxFD {
384 struct FDesc fd;
385 struct BDesc bd;
386 struct BDesc unused;
387 };
388
389 struct RxFD {
390 struct FDesc fd;
391 struct BDesc bd[0]; /* variable length */
392 };
393
394 struct FrFD {
395 struct FDesc fd;
396 struct BDesc bd[RX_BUF_NUM];
397 };
398
399
400 #define tc_readl(addr) ioread32(addr)
401 #define tc_writel(d, addr) iowrite32(d, addr)
402
403 #define TC35815_TX_TIMEOUT msecs_to_jiffies(400)
404
405 /* Information that need to be kept for each controller. */
406 struct tc35815_local {
407 struct pci_dev *pci_dev;
408
409 struct net_device *dev;
410 struct napi_struct napi;
411
412 /* statistics */
413 struct {
414 int max_tx_qlen;
415 int tx_ints;
416 int rx_ints;
417 int tx_underrun;
418 } lstats;
419
420 /* Tx control lock. This protects the transmit buffer ring
421 * state along with the "tx full" state of the driver. This
422 * means all netif_queue flow control actions are protected
423 * by this lock as well.
424 */
425 spinlock_t lock;
426
427 struct mii_bus mii_bus;
428 struct phy_device *phy_dev;
429 int duplex;
430 int speed;
431 int link;
432 struct work_struct restart_work;
433
434 /*
435 * Transmitting: Batch Mode.
436 * 1 BD in 1 TxFD.
437 * Receiving: Packing Mode. (TC35815_USE_PACKEDBUFFER)
438 * 1 circular FD for Free Buffer List.
439 * RX_BUF_NUM BD in Free Buffer FD.
440 * One Free Buffer BD has PAGE_SIZE data buffer.
441 * Or Non-Packing Mode.
442 * 1 circular FD for Free Buffer List.
443 * RX_BUF_NUM BD in Free Buffer FD.
444 * One Free Buffer BD has ETH_FRAME_LEN data buffer.
445 */
446 void *fd_buf; /* for TxFD, RxFD, FrFD */
447 dma_addr_t fd_buf_dma;
448 struct TxFD *tfd_base;
449 unsigned int tfd_start;
450 unsigned int tfd_end;
451 struct RxFD *rfd_base;
452 struct RxFD *rfd_limit;
453 struct RxFD *rfd_cur;
454 struct FrFD *fbl_ptr;
455 #ifdef TC35815_USE_PACKEDBUFFER
456 unsigned char fbl_curid;
457 void *data_buf[RX_BUF_NUM]; /* packing */
458 dma_addr_t data_buf_dma[RX_BUF_NUM];
459 struct {
460 struct sk_buff *skb;
461 dma_addr_t skb_dma;
462 } tx_skbs[TX_FD_NUM];
463 #else
464 unsigned int fbl_count;
465 struct {
466 struct sk_buff *skb;
467 dma_addr_t skb_dma;
468 } tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM];
469 #endif
470 u32 msg_enable;
471 enum tc35815_chiptype chiptype;
472 };
473
474 static inline dma_addr_t fd_virt_to_bus(struct tc35815_local *lp, void *virt)
475 {
476 return lp->fd_buf_dma + ((u8 *)virt - (u8 *)lp->fd_buf);
477 }
478 #ifdef DEBUG
479 static inline void *fd_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
480 {
481 return (void *)((u8 *)lp->fd_buf + (bus - lp->fd_buf_dma));
482 }
483 #endif
484 #ifdef TC35815_USE_PACKEDBUFFER
485 static inline void *rxbuf_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
486 {
487 int i;
488 for (i = 0; i < RX_BUF_NUM; i++) {
489 if (bus >= lp->data_buf_dma[i] &&
490 bus < lp->data_buf_dma[i] + PAGE_SIZE)
491 return (void *)((u8 *)lp->data_buf[i] +
492 (bus - lp->data_buf_dma[i]));
493 }
494 return NULL;
495 }
496
497 #define TC35815_DMA_SYNC_ONDEMAND
498 static void *alloc_rxbuf_page(struct pci_dev *hwdev, dma_addr_t *dma_handle)
499 {
500 #ifdef TC35815_DMA_SYNC_ONDEMAND
501 void *buf;
502 /* pci_map + pci_dma_sync will be more effective than
503 * pci_alloc_consistent on some archs. */
504 buf = (void *)__get_free_page(GFP_ATOMIC);
505 if (!buf)
506 return NULL;
507 *dma_handle = pci_map_single(hwdev, buf, PAGE_SIZE,
508 PCI_DMA_FROMDEVICE);
509 if (pci_dma_mapping_error(*dma_handle)) {
510 free_page((unsigned long)buf);
511 return NULL;
512 }
513 return buf;
514 #else
515 return pci_alloc_consistent(hwdev, PAGE_SIZE, dma_handle);
516 #endif
517 }
518
519 static void free_rxbuf_page(struct pci_dev *hwdev, void *buf, dma_addr_t dma_handle)
520 {
521 #ifdef TC35815_DMA_SYNC_ONDEMAND
522 pci_unmap_single(hwdev, dma_handle, PAGE_SIZE, PCI_DMA_FROMDEVICE);
523 free_page((unsigned long)buf);
524 #else
525 pci_free_consistent(hwdev, PAGE_SIZE, buf, dma_handle);
526 #endif
527 }
528 #else /* TC35815_USE_PACKEDBUFFER */
529 static struct sk_buff *alloc_rxbuf_skb(struct net_device *dev,
530 struct pci_dev *hwdev,
531 dma_addr_t *dma_handle)
532 {
533 struct sk_buff *skb;
534 skb = dev_alloc_skb(RX_BUF_SIZE);
535 if (!skb)
536 return NULL;
537 *dma_handle = pci_map_single(hwdev, skb->data, RX_BUF_SIZE,
538 PCI_DMA_FROMDEVICE);
539 if (pci_dma_mapping_error(*dma_handle)) {
540 dev_kfree_skb_any(skb);
541 return NULL;
542 }
543 skb_reserve(skb, 2); /* make IP header 4byte aligned */
544 return skb;
545 }
546
547 static void free_rxbuf_skb(struct pci_dev *hwdev, struct sk_buff *skb, dma_addr_t dma_handle)
548 {
549 pci_unmap_single(hwdev, dma_handle, RX_BUF_SIZE,
550 PCI_DMA_FROMDEVICE);
551 dev_kfree_skb_any(skb);
552 }
553 #endif /* TC35815_USE_PACKEDBUFFER */
554
555 /* Index to functions, as function prototypes. */
556
557 static int tc35815_open(struct net_device *dev);
558 static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev);
559 static irqreturn_t tc35815_interrupt(int irq, void *dev_id);
560 #ifdef TC35815_NAPI
561 static int tc35815_rx(struct net_device *dev, int limit);
562 static int tc35815_poll(struct napi_struct *napi, int budget);
563 #else
564 static void tc35815_rx(struct net_device *dev);
565 #endif
566 static void tc35815_txdone(struct net_device *dev);
567 static int tc35815_close(struct net_device *dev);
568 static struct net_device_stats *tc35815_get_stats(struct net_device *dev);
569 static void tc35815_set_multicast_list(struct net_device *dev);
570 static void tc35815_tx_timeout(struct net_device *dev);
571 static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
572 #ifdef CONFIG_NET_POLL_CONTROLLER
573 static void tc35815_poll_controller(struct net_device *dev);
574 #endif
575 static const struct ethtool_ops tc35815_ethtool_ops;
576
577 /* Example routines you must write ;->. */
578 static void tc35815_chip_reset(struct net_device *dev);
579 static void tc35815_chip_init(struct net_device *dev);
580
581 #ifdef DEBUG
582 static void panic_queues(struct net_device *dev);
583 #endif
584
585 static void tc35815_restart_work(struct work_struct *work);
586
587 static int tc_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
588 {
589 struct net_device *dev = bus->priv;
590 struct tc35815_regs __iomem *tr =
591 (struct tc35815_regs __iomem *)dev->base_addr;
592 unsigned long timeout = jiffies + 10;
593
594 tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA);
595 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
596 if (time_after(jiffies, timeout))
597 return -EIO;
598 cpu_relax();
599 }
600 return tc_readl(&tr->MD_Data) & 0xffff;
601 }
602
603 static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val)
604 {
605 struct net_device *dev = bus->priv;
606 struct tc35815_regs __iomem *tr =
607 (struct tc35815_regs __iomem *)dev->base_addr;
608 unsigned long timeout = jiffies + 10;
609
610 tc_writel(val, &tr->MD_Data);
611 tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f),
612 &tr->MD_CA);
613 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
614 if (time_after(jiffies, timeout))
615 return -EIO;
616 cpu_relax();
617 }
618 return 0;
619 }
620
621 static void tc_handle_link_change(struct net_device *dev)
622 {
623 struct tc35815_local *lp = netdev_priv(dev);
624 struct phy_device *phydev = lp->phy_dev;
625 unsigned long flags;
626 int status_change = 0;
627
628 spin_lock_irqsave(&lp->lock, flags);
629 if (phydev->link &&
630 (lp->speed != phydev->speed || lp->duplex != phydev->duplex)) {
631 struct tc35815_regs __iomem *tr =
632 (struct tc35815_regs __iomem *)dev->base_addr;
633 u32 reg;
634
635 reg = tc_readl(&tr->MAC_Ctl);
636 reg |= MAC_HaltReq;
637 tc_writel(reg, &tr->MAC_Ctl);
638 if (phydev->duplex == DUPLEX_FULL)
639 reg |= MAC_FullDup;
640 else
641 reg &= ~MAC_FullDup;
642 tc_writel(reg, &tr->MAC_Ctl);
643 reg &= ~MAC_HaltReq;
644 tc_writel(reg, &tr->MAC_Ctl);
645
646 /*
647 * TX4939 PCFG.SPEEDn bit will be changed on
648 * NETDEV_CHANGE event.
649 */
650
651 #if !defined(NO_CHECK_CARRIER) && defined(WORKAROUND_LOSTCAR)
652 /*
653 * WORKAROUND: enable LostCrS only if half duplex
654 * operation.
655 * (TX4939 does not have EnLCarr)
656 */
657 if (phydev->duplex == DUPLEX_HALF &&
658 lp->chiptype != TC35815_TX4939)
659 tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,
660 &tr->Tx_Ctl);
661 #endif
662
663 lp->speed = phydev->speed;
664 lp->duplex = phydev->duplex;
665 status_change = 1;
666 }
667
668 if (phydev->link != lp->link) {
669 if (phydev->link) {
670 #ifdef WORKAROUND_100HALF_PROMISC
671 /* delayed promiscuous enabling */
672 if (dev->flags & IFF_PROMISC)
673 tc35815_set_multicast_list(dev);
674 #endif
675 netif_schedule(dev);
676 } else {
677 lp->speed = 0;
678 lp->duplex = -1;
679 }
680 lp->link = phydev->link;
681
682 status_change = 1;
683 }
684 spin_unlock_irqrestore(&lp->lock, flags);
685
686 if (status_change && netif_msg_link(lp)) {
687 phy_print_status(phydev);
688 #ifdef DEBUG
689 printk(KERN_DEBUG
690 "%s: MII BMCR %04x BMSR %04x LPA %04x\n",
691 dev->name,
692 phy_read(phydev, MII_BMCR),
693 phy_read(phydev, MII_BMSR),
694 phy_read(phydev, MII_LPA));
695 #endif
696 }
697 }
698
699 static int tc_mii_probe(struct net_device *dev)
700 {
701 struct tc35815_local *lp = netdev_priv(dev);
702 struct phy_device *phydev = NULL;
703 int phy_addr;
704 u32 dropmask;
705
706 /* find the first phy */
707 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
708 if (lp->mii_bus.phy_map[phy_addr]) {
709 if (phydev) {
710 printk(KERN_ERR "%s: multiple PHYs found\n",
711 dev->name);
712 return -EINVAL;
713 }
714 phydev = lp->mii_bus.phy_map[phy_addr];
715 break;
716 }
717 }
718
719 if (!phydev) {
720 printk(KERN_ERR "%s: no PHY found\n", dev->name);
721 return -ENODEV;
722 }
723
724 /* attach the mac to the phy */
725 phydev = phy_connect(dev, phydev->dev.bus_id,
726 &tc_handle_link_change, 0,
727 lp->chiptype == TC35815_TX4939 ?
728 PHY_INTERFACE_MODE_RMII : PHY_INTERFACE_MODE_MII);
729 if (IS_ERR(phydev)) {
730 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
731 return PTR_ERR(phydev);
732 }
733 printk(KERN_INFO "%s: attached PHY driver [%s] "
734 "(mii_bus:phy_addr=%s, id=%x)\n",
735 dev->name, phydev->drv->name, phydev->dev.bus_id,
736 phydev->phy_id);
737
738 /* mask with MAC supported features */
739 phydev->supported &= PHY_BASIC_FEATURES;
740 dropmask = 0;
741 if (options.speed == 10)
742 dropmask |= SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
743 else if (options.speed == 100)
744 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full;
745 if (options.duplex == 1)
746 dropmask |= SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full;
747 else if (options.duplex == 2)
748 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_100baseT_Half;
749 phydev->supported &= ~dropmask;
750 phydev->advertising = phydev->supported;
751
752 lp->link = 0;
753 lp->speed = 0;
754 lp->duplex = -1;
755 lp->phy_dev = phydev;
756
757 return 0;
758 }
759
760 static int tc_mii_init(struct net_device *dev)
761 {
762 struct tc35815_local *lp = netdev_priv(dev);
763 int err;
764 int i;
765
766 lp->mii_bus.name = "tc35815_mii_bus";
767 lp->mii_bus.read = tc_mdio_read;
768 lp->mii_bus.write = tc_mdio_write;
769 snprintf(lp->mii_bus.id, MII_BUS_ID_SIZE, "%x",
770 (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn);
771 lp->mii_bus.priv = dev;
772 lp->mii_bus.dev = &lp->pci_dev->dev;
773 lp->mii_bus.irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
774 if (!lp->mii_bus.irq) {
775 err = -ENOMEM;
776 goto err_out;
777 }
778
779 for (i = 0; i < PHY_MAX_ADDR; i++)
780 lp->mii_bus.irq[i] = PHY_POLL;
781
782 err = mdiobus_register(&lp->mii_bus);
783 if (err)
784 goto err_out_free_mdio_irq;
785 err = tc_mii_probe(dev);
786 if (err)
787 goto err_out_unregister_bus;
788 return 0;
789
790 err_out_unregister_bus:
791 mdiobus_unregister(&lp->mii_bus);
792 err_out_free_mdio_irq:
793 kfree(lp->mii_bus.irq);
794 err_out:
795 return err;
796 }
797
798 #ifdef CONFIG_CPU_TX49XX
799 /*
800 * Find a platform_device providing a MAC address. The platform code
801 * should provide a "tc35815-mac" device with a MAC address in its
802 * platform_data.
803 */
804 static int __devinit tc35815_mac_match(struct device *dev, void *data)
805 {
806 struct platform_device *plat_dev = to_platform_device(dev);
807 struct pci_dev *pci_dev = data;
808 unsigned int id = pci_dev->irq;
809 return !strcmp(plat_dev->name, "tc35815-mac") && plat_dev->id == id;
810 }
811
812 static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev)
813 {
814 struct tc35815_local *lp = netdev_priv(dev);
815 struct device *pd = bus_find_device(&platform_bus_type, NULL,
816 lp->pci_dev, tc35815_mac_match);
817 if (pd) {
818 if (pd->platform_data)
819 memcpy(dev->dev_addr, pd->platform_data, ETH_ALEN);
820 put_device(pd);
821 return is_valid_ether_addr(dev->dev_addr) ? 0 : -ENODEV;
822 }
823 return -ENODEV;
824 }
825 #else
826 static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev)
827 {
828 return -ENODEV;
829 }
830 #endif
831
832 static int __devinit tc35815_init_dev_addr(struct net_device *dev)
833 {
834 struct tc35815_regs __iomem *tr =
835 (struct tc35815_regs __iomem *)dev->base_addr;
836 int i;
837
838 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
839 ;
840 for (i = 0; i < 6; i += 2) {
841 unsigned short data;
842 tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl);
843 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
844 ;
845 data = tc_readl(&tr->PROM_Data);
846 dev->dev_addr[i] = data & 0xff;
847 dev->dev_addr[i+1] = data >> 8;
848 }
849 if (!is_valid_ether_addr(dev->dev_addr))
850 return tc35815_read_plat_dev_addr(dev);
851 return 0;
852 }
853
854 static int __devinit tc35815_init_one(struct pci_dev *pdev,
855 const struct pci_device_id *ent)
856 {
857 void __iomem *ioaddr = NULL;
858 struct net_device *dev;
859 struct tc35815_local *lp;
860 int rc;
861 DECLARE_MAC_BUF(mac);
862
863 static int printed_version;
864 if (!printed_version++) {
865 printk(version);
866 dev_printk(KERN_DEBUG, &pdev->dev,
867 "speed:%d duplex:%d\n",
868 options.speed, options.duplex);
869 }
870
871 if (!pdev->irq) {
872 dev_warn(&pdev->dev, "no IRQ assigned.\n");
873 return -ENODEV;
874 }
875
876 /* dev zeroed in alloc_etherdev */
877 dev = alloc_etherdev(sizeof(*lp));
878 if (dev == NULL) {
879 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
880 return -ENOMEM;
881 }
882 SET_NETDEV_DEV(dev, &pdev->dev);
883 lp = netdev_priv(dev);
884 lp->dev = dev;
885
886 /* enable device (incl. PCI PM wakeup), and bus-mastering */
887 rc = pcim_enable_device(pdev);
888 if (rc)
889 goto err_out;
890 rc = pcim_iomap_regions(pdev, 1 << 1, MODNAME);
891 if (rc)
892 goto err_out;
893 pci_set_master(pdev);
894 ioaddr = pcim_iomap_table(pdev)[1];
895
896 /* Initialize the device structure. */
897 dev->open = tc35815_open;
898 dev->hard_start_xmit = tc35815_send_packet;
899 dev->stop = tc35815_close;
900 dev->get_stats = tc35815_get_stats;
901 dev->set_multicast_list = tc35815_set_multicast_list;
902 dev->do_ioctl = tc35815_ioctl;
903 dev->ethtool_ops = &tc35815_ethtool_ops;
904 dev->tx_timeout = tc35815_tx_timeout;
905 dev->watchdog_timeo = TC35815_TX_TIMEOUT;
906 #ifdef TC35815_NAPI
907 netif_napi_add(dev, &lp->napi, tc35815_poll, NAPI_WEIGHT);
908 #endif
909 #ifdef CONFIG_NET_POLL_CONTROLLER
910 dev->poll_controller = tc35815_poll_controller;
911 #endif
912
913 dev->irq = pdev->irq;
914 dev->base_addr = (unsigned long)ioaddr;
915
916 INIT_WORK(&lp->restart_work, tc35815_restart_work);
917 spin_lock_init(&lp->lock);
918 lp->pci_dev = pdev;
919 lp->chiptype = ent->driver_data;
920
921 lp->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK;
922 pci_set_drvdata(pdev, dev);
923
924 /* Soft reset the chip. */
925 tc35815_chip_reset(dev);
926
927 /* Retrieve the ethernet address. */
928 if (tc35815_init_dev_addr(dev)) {
929 dev_warn(&pdev->dev, "not valid ether addr\n");
930 random_ether_addr(dev->dev_addr);
931 }
932
933 rc = register_netdev(dev);
934 if (rc)
935 goto err_out;
936
937 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
938 printk(KERN_INFO "%s: %s at 0x%lx, %s, IRQ %d\n",
939 dev->name,
940 chip_info[ent->driver_data].name,
941 dev->base_addr,
942 print_mac(mac, dev->dev_addr),
943 dev->irq);
944
945 rc = tc_mii_init(dev);
946 if (rc)
947 goto err_out_unregister;
948
949 return 0;
950
951 err_out_unregister:
952 unregister_netdev(dev);
953 err_out:
954 free_netdev(dev);
955 return rc;
956 }
957
958
959 static void __devexit tc35815_remove_one(struct pci_dev *pdev)
960 {
961 struct net_device *dev = pci_get_drvdata(pdev);
962 struct tc35815_local *lp = netdev_priv(dev);
963
964 phy_disconnect(lp->phy_dev);
965 mdiobus_unregister(&lp->mii_bus);
966 kfree(lp->mii_bus.irq);
967 unregister_netdev(dev);
968 free_netdev(dev);
969 pci_set_drvdata(pdev, NULL);
970 }
971
972 static int
973 tc35815_init_queues(struct net_device *dev)
974 {
975 struct tc35815_local *lp = netdev_priv(dev);
976 int i;
977 unsigned long fd_addr;
978
979 if (!lp->fd_buf) {
980 BUG_ON(sizeof(struct FDesc) +
981 sizeof(struct BDesc) * RX_BUF_NUM +
982 sizeof(struct FDesc) * RX_FD_NUM +
983 sizeof(struct TxFD) * TX_FD_NUM >
984 PAGE_SIZE * FD_PAGE_NUM);
985
986 lp->fd_buf = pci_alloc_consistent(lp->pci_dev,
987 PAGE_SIZE * FD_PAGE_NUM,
988 &lp->fd_buf_dma);
989 if (!lp->fd_buf)
990 return -ENOMEM;
991 for (i = 0; i < RX_BUF_NUM; i++) {
992 #ifdef TC35815_USE_PACKEDBUFFER
993 lp->data_buf[i] =
994 alloc_rxbuf_page(lp->pci_dev,
995 &lp->data_buf_dma[i]);
996 if (!lp->data_buf[i]) {
997 while (--i >= 0) {
998 free_rxbuf_page(lp->pci_dev,
999 lp->data_buf[i],
1000 lp->data_buf_dma[i]);
1001 lp->data_buf[i] = NULL;
1002 }
1003 pci_free_consistent(lp->pci_dev,
1004 PAGE_SIZE * FD_PAGE_NUM,
1005 lp->fd_buf,
1006 lp->fd_buf_dma);
1007 lp->fd_buf = NULL;
1008 return -ENOMEM;
1009 }
1010 #else
1011 lp->rx_skbs[i].skb =
1012 alloc_rxbuf_skb(dev, lp->pci_dev,
1013 &lp->rx_skbs[i].skb_dma);
1014 if (!lp->rx_skbs[i].skb) {
1015 while (--i >= 0) {
1016 free_rxbuf_skb(lp->pci_dev,
1017 lp->rx_skbs[i].skb,
1018 lp->rx_skbs[i].skb_dma);
1019 lp->rx_skbs[i].skb = NULL;
1020 }
1021 pci_free_consistent(lp->pci_dev,
1022 PAGE_SIZE * FD_PAGE_NUM,
1023 lp->fd_buf,
1024 lp->fd_buf_dma);
1025 lp->fd_buf = NULL;
1026 return -ENOMEM;
1027 }
1028 #endif
1029 }
1030 printk(KERN_DEBUG "%s: FD buf %p DataBuf",
1031 dev->name, lp->fd_buf);
1032 #ifdef TC35815_USE_PACKEDBUFFER
1033 printk(" DataBuf");
1034 for (i = 0; i < RX_BUF_NUM; i++)
1035 printk(" %p", lp->data_buf[i]);
1036 #endif
1037 printk("\n");
1038 } else {
1039 for (i = 0; i < FD_PAGE_NUM; i++)
1040 clear_page((void *)((unsigned long)lp->fd_buf +
1041 i * PAGE_SIZE));
1042 }
1043 fd_addr = (unsigned long)lp->fd_buf;
1044
1045 /* Free Descriptors (for Receive) */
1046 lp->rfd_base = (struct RxFD *)fd_addr;
1047 fd_addr += sizeof(struct RxFD) * RX_FD_NUM;
1048 for (i = 0; i < RX_FD_NUM; i++)
1049 lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD);
1050 lp->rfd_cur = lp->rfd_base;
1051 lp->rfd_limit = (struct RxFD *)fd_addr - (RX_FD_RESERVE + 1);
1052
1053 /* Transmit Descriptors */
1054 lp->tfd_base = (struct TxFD *)fd_addr;
1055 fd_addr += sizeof(struct TxFD) * TX_FD_NUM;
1056 for (i = 0; i < TX_FD_NUM; i++) {
1057 lp->tfd_base[i].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[i+1]));
1058 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1059 lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0);
1060 }
1061 lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[0]));
1062 lp->tfd_start = 0;
1063 lp->tfd_end = 0;
1064
1065 /* Buffer List (for Receive) */
1066 lp->fbl_ptr = (struct FrFD *)fd_addr;
1067 lp->fbl_ptr->fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, lp->fbl_ptr));
1068 lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_NUM | FD_CownsFD);
1069 #ifndef TC35815_USE_PACKEDBUFFER
1070 /*
1071 * move all allocated skbs to head of rx_skbs[] array.
1072 * fbl_count mighe not be RX_BUF_NUM if alloc_rxbuf_skb() in
1073 * tc35815_rx() had failed.
1074 */
1075 lp->fbl_count = 0;
1076 for (i = 0; i < RX_BUF_NUM; i++) {
1077 if (lp->rx_skbs[i].skb) {
1078 if (i != lp->fbl_count) {
1079 lp->rx_skbs[lp->fbl_count].skb =
1080 lp->rx_skbs[i].skb;
1081 lp->rx_skbs[lp->fbl_count].skb_dma =
1082 lp->rx_skbs[i].skb_dma;
1083 }
1084 lp->fbl_count++;
1085 }
1086 }
1087 #endif
1088 for (i = 0; i < RX_BUF_NUM; i++) {
1089 #ifdef TC35815_USE_PACKEDBUFFER
1090 lp->fbl_ptr->bd[i].BuffData = cpu_to_le32(lp->data_buf_dma[i]);
1091 #else
1092 if (i >= lp->fbl_count) {
1093 lp->fbl_ptr->bd[i].BuffData = 0;
1094 lp->fbl_ptr->bd[i].BDCtl = 0;
1095 continue;
1096 }
1097 lp->fbl_ptr->bd[i].BuffData =
1098 cpu_to_le32(lp->rx_skbs[i].skb_dma);
1099 #endif
1100 /* BDID is index of FrFD.bd[] */
1101 lp->fbl_ptr->bd[i].BDCtl =
1102 cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) |
1103 RX_BUF_SIZE);
1104 }
1105 #ifdef TC35815_USE_PACKEDBUFFER
1106 lp->fbl_curid = 0;
1107 #endif
1108
1109 printk(KERN_DEBUG "%s: TxFD %p RxFD %p FrFD %p\n",
1110 dev->name, lp->tfd_base, lp->rfd_base, lp->fbl_ptr);
1111 return 0;
1112 }
1113
1114 static void
1115 tc35815_clear_queues(struct net_device *dev)
1116 {
1117 struct tc35815_local *lp = netdev_priv(dev);
1118 int i;
1119
1120 for (i = 0; i < TX_FD_NUM; i++) {
1121 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1122 struct sk_buff *skb =
1123 fdsystem != 0xffffffff ?
1124 lp->tx_skbs[fdsystem].skb : NULL;
1125 #ifdef DEBUG
1126 if (lp->tx_skbs[i].skb != skb) {
1127 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1128 panic_queues(dev);
1129 }
1130 #else
1131 BUG_ON(lp->tx_skbs[i].skb != skb);
1132 #endif
1133 if (skb) {
1134 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1135 lp->tx_skbs[i].skb = NULL;
1136 lp->tx_skbs[i].skb_dma = 0;
1137 dev_kfree_skb_any(skb);
1138 }
1139 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1140 }
1141
1142 tc35815_init_queues(dev);
1143 }
1144
1145 static void
1146 tc35815_free_queues(struct net_device *dev)
1147 {
1148 struct tc35815_local *lp = netdev_priv(dev);
1149 int i;
1150
1151 if (lp->tfd_base) {
1152 for (i = 0; i < TX_FD_NUM; i++) {
1153 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1154 struct sk_buff *skb =
1155 fdsystem != 0xffffffff ?
1156 lp->tx_skbs[fdsystem].skb : NULL;
1157 #ifdef DEBUG
1158 if (lp->tx_skbs[i].skb != skb) {
1159 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1160 panic_queues(dev);
1161 }
1162 #else
1163 BUG_ON(lp->tx_skbs[i].skb != skb);
1164 #endif
1165 if (skb) {
1166 dev_kfree_skb(skb);
1167 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1168 lp->tx_skbs[i].skb = NULL;
1169 lp->tx_skbs[i].skb_dma = 0;
1170 }
1171 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1172 }
1173 }
1174
1175 lp->rfd_base = NULL;
1176 lp->rfd_limit = NULL;
1177 lp->rfd_cur = NULL;
1178 lp->fbl_ptr = NULL;
1179
1180 for (i = 0; i < RX_BUF_NUM; i++) {
1181 #ifdef TC35815_USE_PACKEDBUFFER
1182 if (lp->data_buf[i]) {
1183 free_rxbuf_page(lp->pci_dev,
1184 lp->data_buf[i], lp->data_buf_dma[i]);
1185 lp->data_buf[i] = NULL;
1186 }
1187 #else
1188 if (lp->rx_skbs[i].skb) {
1189 free_rxbuf_skb(lp->pci_dev, lp->rx_skbs[i].skb,
1190 lp->rx_skbs[i].skb_dma);
1191 lp->rx_skbs[i].skb = NULL;
1192 }
1193 #endif
1194 }
1195 if (lp->fd_buf) {
1196 pci_free_consistent(lp->pci_dev, PAGE_SIZE * FD_PAGE_NUM,
1197 lp->fd_buf, lp->fd_buf_dma);
1198 lp->fd_buf = NULL;
1199 }
1200 }
1201
1202 static void
1203 dump_txfd(struct TxFD *fd)
1204 {
1205 printk("TxFD(%p): %08x %08x %08x %08x\n", fd,
1206 le32_to_cpu(fd->fd.FDNext),
1207 le32_to_cpu(fd->fd.FDSystem),
1208 le32_to_cpu(fd->fd.FDStat),
1209 le32_to_cpu(fd->fd.FDCtl));
1210 printk("BD: ");
1211 printk(" %08x %08x",
1212 le32_to_cpu(fd->bd.BuffData),
1213 le32_to_cpu(fd->bd.BDCtl));
1214 printk("\n");
1215 }
1216
1217 static int
1218 dump_rxfd(struct RxFD *fd)
1219 {
1220 int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1221 if (bd_count > 8)
1222 bd_count = 8;
1223 printk("RxFD(%p): %08x %08x %08x %08x\n", fd,
1224 le32_to_cpu(fd->fd.FDNext),
1225 le32_to_cpu(fd->fd.FDSystem),
1226 le32_to_cpu(fd->fd.FDStat),
1227 le32_to_cpu(fd->fd.FDCtl));
1228 if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD)
1229 return 0;
1230 printk("BD: ");
1231 for (i = 0; i < bd_count; i++)
1232 printk(" %08x %08x",
1233 le32_to_cpu(fd->bd[i].BuffData),
1234 le32_to_cpu(fd->bd[i].BDCtl));
1235 printk("\n");
1236 return bd_count;
1237 }
1238
1239 #if defined(DEBUG) || defined(TC35815_USE_PACKEDBUFFER)
1240 static void
1241 dump_frfd(struct FrFD *fd)
1242 {
1243 int i;
1244 printk("FrFD(%p): %08x %08x %08x %08x\n", fd,
1245 le32_to_cpu(fd->fd.FDNext),
1246 le32_to_cpu(fd->fd.FDSystem),
1247 le32_to_cpu(fd->fd.FDStat),
1248 le32_to_cpu(fd->fd.FDCtl));
1249 printk("BD: ");
1250 for (i = 0; i < RX_BUF_NUM; i++)
1251 printk(" %08x %08x",
1252 le32_to_cpu(fd->bd[i].BuffData),
1253 le32_to_cpu(fd->bd[i].BDCtl));
1254 printk("\n");
1255 }
1256 #endif
1257
1258 #ifdef DEBUG
1259 static void
1260 panic_queues(struct net_device *dev)
1261 {
1262 struct tc35815_local *lp = netdev_priv(dev);
1263 int i;
1264
1265 printk("TxFD base %p, start %u, end %u\n",
1266 lp->tfd_base, lp->tfd_start, lp->tfd_end);
1267 printk("RxFD base %p limit %p cur %p\n",
1268 lp->rfd_base, lp->rfd_limit, lp->rfd_cur);
1269 printk("FrFD %p\n", lp->fbl_ptr);
1270 for (i = 0; i < TX_FD_NUM; i++)
1271 dump_txfd(&lp->tfd_base[i]);
1272 for (i = 0; i < RX_FD_NUM; i++) {
1273 int bd_count = dump_rxfd(&lp->rfd_base[i]);
1274 i += (bd_count + 1) / 2; /* skip BDs */
1275 }
1276 dump_frfd(lp->fbl_ptr);
1277 panic("%s: Illegal queue state.", dev->name);
1278 }
1279 #endif
1280
1281 static void print_eth(const u8 *add)
1282 {
1283 DECLARE_MAC_BUF(mac);
1284
1285 printk(KERN_DEBUG "print_eth(%p)\n", add);
1286 printk(KERN_DEBUG " %s =>", print_mac(mac, add + 6));
1287 printk(KERN_CONT " %s : %02x%02x\n",
1288 print_mac(mac, add), add[12], add[13]);
1289 }
1290
1291 static int tc35815_tx_full(struct net_device *dev)
1292 {
1293 struct tc35815_local *lp = netdev_priv(dev);
1294 return ((lp->tfd_start + 1) % TX_FD_NUM == lp->tfd_end);
1295 }
1296
1297 static void tc35815_restart(struct net_device *dev)
1298 {
1299 struct tc35815_local *lp = netdev_priv(dev);
1300
1301 if (lp->phy_dev) {
1302 int timeout;
1303
1304 phy_write(lp->phy_dev, MII_BMCR, BMCR_RESET);
1305 timeout = 100;
1306 while (--timeout) {
1307 if (!(phy_read(lp->phy_dev, MII_BMCR) & BMCR_RESET))
1308 break;
1309 udelay(1);
1310 }
1311 if (!timeout)
1312 printk(KERN_ERR "%s: BMCR reset failed.\n", dev->name);
1313 }
1314
1315 spin_lock_irq(&lp->lock);
1316 tc35815_chip_reset(dev);
1317 tc35815_clear_queues(dev);
1318 tc35815_chip_init(dev);
1319 /* Reconfigure CAM again since tc35815_chip_init() initialize it. */
1320 tc35815_set_multicast_list(dev);
1321 spin_unlock_irq(&lp->lock);
1322
1323 netif_wake_queue(dev);
1324 }
1325
1326 static void tc35815_restart_work(struct work_struct *work)
1327 {
1328 struct tc35815_local *lp =
1329 container_of(work, struct tc35815_local, restart_work);
1330 struct net_device *dev = lp->dev;
1331
1332 tc35815_restart(dev);
1333 }
1334
1335 static void tc35815_schedule_restart(struct net_device *dev)
1336 {
1337 struct tc35815_local *lp = netdev_priv(dev);
1338 struct tc35815_regs __iomem *tr =
1339 (struct tc35815_regs __iomem *)dev->base_addr;
1340
1341 /* disable interrupts */
1342 tc_writel(0, &tr->Int_En);
1343 tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl);
1344 schedule_work(&lp->restart_work);
1345 }
1346
1347 static void tc35815_tx_timeout(struct net_device *dev)
1348 {
1349 struct tc35815_regs __iomem *tr =
1350 (struct tc35815_regs __iomem *)dev->base_addr;
1351
1352 printk(KERN_WARNING "%s: transmit timed out, status %#x\n",
1353 dev->name, tc_readl(&tr->Tx_Stat));
1354
1355 /* Try to restart the adaptor. */
1356 tc35815_schedule_restart(dev);
1357 dev->stats.tx_errors++;
1358 }
1359
1360 /*
1361 * Open/initialize the controller. This is called (in the current kernel)
1362 * sometime after booting when the 'ifconfig' program is run.
1363 *
1364 * This routine should set everything up anew at each open, even
1365 * registers that "should" only need to be set once at boot, so that
1366 * there is non-reboot way to recover if something goes wrong.
1367 */
1368 static int
1369 tc35815_open(struct net_device *dev)
1370 {
1371 struct tc35815_local *lp = netdev_priv(dev);
1372
1373 /*
1374 * This is used if the interrupt line can turned off (shared).
1375 * See 3c503.c for an example of selecting the IRQ at config-time.
1376 */
1377 if (request_irq(dev->irq, &tc35815_interrupt, IRQF_SHARED,
1378 dev->name, dev))
1379 return -EAGAIN;
1380
1381 tc35815_chip_reset(dev);
1382
1383 if (tc35815_init_queues(dev) != 0) {
1384 free_irq(dev->irq, dev);
1385 return -EAGAIN;
1386 }
1387
1388 #ifdef TC35815_NAPI
1389 napi_enable(&lp->napi);
1390 #endif
1391
1392 /* Reset the hardware here. Don't forget to set the station address. */
1393 spin_lock_irq(&lp->lock);
1394 tc35815_chip_init(dev);
1395 spin_unlock_irq(&lp->lock);
1396
1397 netif_carrier_off(dev);
1398 /* schedule a link state check */
1399 phy_start(lp->phy_dev);
1400
1401 /* We are now ready to accept transmit requeusts from
1402 * the queueing layer of the networking.
1403 */
1404 netif_start_queue(dev);
1405
1406 return 0;
1407 }
1408
1409 /* This will only be invoked if your driver is _not_ in XOFF state.
1410 * What this means is that you need not check it, and that this
1411 * invariant will hold if you make sure that the netif_*_queue()
1412 * calls are done at the proper times.
1413 */
1414 static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev)
1415 {
1416 struct tc35815_local *lp = netdev_priv(dev);
1417 struct TxFD *txfd;
1418 unsigned long flags;
1419
1420 /* If some error occurs while trying to transmit this
1421 * packet, you should return '1' from this function.
1422 * In such a case you _may not_ do anything to the
1423 * SKB, it is still owned by the network queueing
1424 * layer when an error is returned. This means you
1425 * may not modify any SKB fields, you may not free
1426 * the SKB, etc.
1427 */
1428
1429 /* This is the most common case for modern hardware.
1430 * The spinlock protects this code from the TX complete
1431 * hardware interrupt handler. Queue flow control is
1432 * thus managed under this lock as well.
1433 */
1434 spin_lock_irqsave(&lp->lock, flags);
1435
1436 /* failsafe... (handle txdone now if half of FDs are used) */
1437 if ((lp->tfd_start + TX_FD_NUM - lp->tfd_end) % TX_FD_NUM >
1438 TX_FD_NUM / 2)
1439 tc35815_txdone(dev);
1440
1441 if (netif_msg_pktdata(lp))
1442 print_eth(skb->data);
1443 #ifdef DEBUG
1444 if (lp->tx_skbs[lp->tfd_start].skb) {
1445 printk("%s: tx_skbs conflict.\n", dev->name);
1446 panic_queues(dev);
1447 }
1448 #else
1449 BUG_ON(lp->tx_skbs[lp->tfd_start].skb);
1450 #endif
1451 lp->tx_skbs[lp->tfd_start].skb = skb;
1452 lp->tx_skbs[lp->tfd_start].skb_dma = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1453
1454 /*add to ring */
1455 txfd = &lp->tfd_base[lp->tfd_start];
1456 txfd->bd.BuffData = cpu_to_le32(lp->tx_skbs[lp->tfd_start].skb_dma);
1457 txfd->bd.BDCtl = cpu_to_le32(skb->len);
1458 txfd->fd.FDSystem = cpu_to_le32(lp->tfd_start);
1459 txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT));
1460
1461 if (lp->tfd_start == lp->tfd_end) {
1462 struct tc35815_regs __iomem *tr =
1463 (struct tc35815_regs __iomem *)dev->base_addr;
1464 /* Start DMA Transmitter. */
1465 txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1466 #ifdef GATHER_TXINT
1467 txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1468 #endif
1469 if (netif_msg_tx_queued(lp)) {
1470 printk("%s: starting TxFD.\n", dev->name);
1471 dump_txfd(txfd);
1472 }
1473 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1474 } else {
1475 txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL);
1476 if (netif_msg_tx_queued(lp)) {
1477 printk("%s: queueing TxFD.\n", dev->name);
1478 dump_txfd(txfd);
1479 }
1480 }
1481 lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM;
1482
1483 dev->trans_start = jiffies;
1484
1485 /* If we just used up the very last entry in the
1486 * TX ring on this device, tell the queueing
1487 * layer to send no more.
1488 */
1489 if (tc35815_tx_full(dev)) {
1490 if (netif_msg_tx_queued(lp))
1491 printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name);
1492 netif_stop_queue(dev);
1493 }
1494
1495 /* When the TX completion hw interrupt arrives, this
1496 * is when the transmit statistics are updated.
1497 */
1498
1499 spin_unlock_irqrestore(&lp->lock, flags);
1500 return 0;
1501 }
1502
1503 #define FATAL_ERROR_INT \
1504 (Int_IntPCI | Int_DmParErr | Int_IntNRAbt)
1505 static void tc35815_fatal_error_interrupt(struct net_device *dev, u32 status)
1506 {
1507 static int count;
1508 printk(KERN_WARNING "%s: Fatal Error Intterrupt (%#x):",
1509 dev->name, status);
1510 if (status & Int_IntPCI)
1511 printk(" IntPCI");
1512 if (status & Int_DmParErr)
1513 printk(" DmParErr");
1514 if (status & Int_IntNRAbt)
1515 printk(" IntNRAbt");
1516 printk("\n");
1517 if (count++ > 100)
1518 panic("%s: Too many fatal errors.", dev->name);
1519 printk(KERN_WARNING "%s: Resetting ...\n", dev->name);
1520 /* Try to restart the adaptor. */
1521 tc35815_schedule_restart(dev);
1522 }
1523
1524 #ifdef TC35815_NAPI
1525 static int tc35815_do_interrupt(struct net_device *dev, u32 status, int limit)
1526 #else
1527 static int tc35815_do_interrupt(struct net_device *dev, u32 status)
1528 #endif
1529 {
1530 struct tc35815_local *lp = netdev_priv(dev);
1531 struct tc35815_regs __iomem *tr =
1532 (struct tc35815_regs __iomem *)dev->base_addr;
1533 int ret = -1;
1534
1535 /* Fatal errors... */
1536 if (status & FATAL_ERROR_INT) {
1537 tc35815_fatal_error_interrupt(dev, status);
1538 return 0;
1539 }
1540 /* recoverable errors */
1541 if (status & Int_IntFDAEx) {
1542 /* disable FDAEx int. (until we make rooms...) */
1543 tc_writel(tc_readl(&tr->Int_En) & ~Int_FDAExEn, &tr->Int_En);
1544 printk(KERN_WARNING
1545 "%s: Free Descriptor Area Exhausted (%#x).\n",
1546 dev->name, status);
1547 dev->stats.rx_dropped++;
1548 ret = 0;
1549 }
1550 if (status & Int_IntBLEx) {
1551 /* disable BLEx int. (until we make rooms...) */
1552 tc_writel(tc_readl(&tr->Int_En) & ~Int_BLExEn, &tr->Int_En);
1553 printk(KERN_WARNING
1554 "%s: Buffer List Exhausted (%#x).\n",
1555 dev->name, status);
1556 dev->stats.rx_dropped++;
1557 ret = 0;
1558 }
1559 if (status & Int_IntExBD) {
1560 printk(KERN_WARNING
1561 "%s: Excessive Buffer Descriptiors (%#x).\n",
1562 dev->name, status);
1563 dev->stats.rx_length_errors++;
1564 ret = 0;
1565 }
1566
1567 /* normal notification */
1568 if (status & Int_IntMacRx) {
1569 /* Got a packet(s). */
1570 #ifdef TC35815_NAPI
1571 ret = tc35815_rx(dev, limit);
1572 #else
1573 tc35815_rx(dev);
1574 ret = 0;
1575 #endif
1576 lp->lstats.rx_ints++;
1577 }
1578 if (status & Int_IntMacTx) {
1579 /* Transmit complete. */
1580 lp->lstats.tx_ints++;
1581 tc35815_txdone(dev);
1582 netif_wake_queue(dev);
1583 ret = 0;
1584 }
1585 return ret;
1586 }
1587
1588 /*
1589 * The typical workload of the driver:
1590 * Handle the network interface interrupts.
1591 */
1592 static irqreturn_t tc35815_interrupt(int irq, void *dev_id)
1593 {
1594 struct net_device *dev = dev_id;
1595 struct tc35815_local *lp = netdev_priv(dev);
1596 struct tc35815_regs __iomem *tr =
1597 (struct tc35815_regs __iomem *)dev->base_addr;
1598 #ifdef TC35815_NAPI
1599 u32 dmactl = tc_readl(&tr->DMA_Ctl);
1600
1601 if (!(dmactl & DMA_IntMask)) {
1602 /* disable interrupts */
1603 tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl);
1604 if (netif_rx_schedule_prep(dev, &lp->napi))
1605 __netif_rx_schedule(dev, &lp->napi);
1606 else {
1607 printk(KERN_ERR "%s: interrupt taken in poll\n",
1608 dev->name);
1609 BUG();
1610 }
1611 (void)tc_readl(&tr->Int_Src); /* flush */
1612 return IRQ_HANDLED;
1613 }
1614 return IRQ_NONE;
1615 #else
1616 int handled;
1617 u32 status;
1618
1619 spin_lock(&lp->lock);
1620 status = tc_readl(&tr->Int_Src);
1621 tc_writel(status, &tr->Int_Src); /* write to clear */
1622 handled = tc35815_do_interrupt(dev, status);
1623 (void)tc_readl(&tr->Int_Src); /* flush */
1624 spin_unlock(&lp->lock);
1625 return IRQ_RETVAL(handled >= 0);
1626 #endif /* TC35815_NAPI */
1627 }
1628
1629 #ifdef CONFIG_NET_POLL_CONTROLLER
1630 static void tc35815_poll_controller(struct net_device *dev)
1631 {
1632 disable_irq(dev->irq);
1633 tc35815_interrupt(dev->irq, dev);
1634 enable_irq(dev->irq);
1635 }
1636 #endif
1637
1638 /* We have a good packet(s), get it/them out of the buffers. */
1639 #ifdef TC35815_NAPI
1640 static int
1641 tc35815_rx(struct net_device *dev, int limit)
1642 #else
1643 static void
1644 tc35815_rx(struct net_device *dev)
1645 #endif
1646 {
1647 struct tc35815_local *lp = netdev_priv(dev);
1648 unsigned int fdctl;
1649 int i;
1650 int buf_free_count = 0;
1651 int fd_free_count = 0;
1652 #ifdef TC35815_NAPI
1653 int received = 0;
1654 #endif
1655
1656 while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) {
1657 int status = le32_to_cpu(lp->rfd_cur->fd.FDStat);
1658 int pkt_len = fdctl & FD_FDLength_MASK;
1659 int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1660 #ifdef DEBUG
1661 struct RxFD *next_rfd;
1662 #endif
1663 #if (RX_CTL_CMD & Rx_StripCRC) == 0
1664 pkt_len -= 4;
1665 #endif
1666
1667 if (netif_msg_rx_status(lp))
1668 dump_rxfd(lp->rfd_cur);
1669 if (status & Rx_Good) {
1670 struct sk_buff *skb;
1671 unsigned char *data;
1672 int cur_bd;
1673 #ifdef TC35815_USE_PACKEDBUFFER
1674 int offset;
1675 #endif
1676
1677 #ifdef TC35815_NAPI
1678 if (--limit < 0)
1679 break;
1680 #endif
1681 #ifdef TC35815_USE_PACKEDBUFFER
1682 BUG_ON(bd_count > 2);
1683 skb = dev_alloc_skb(pkt_len + 2); /* +2: for reserve */
1684 if (skb == NULL) {
1685 printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n",
1686 dev->name);
1687 dev->stats.rx_dropped++;
1688 break;
1689 }
1690 skb_reserve(skb, 2); /* 16 bit alignment */
1691
1692 data = skb_put(skb, pkt_len);
1693
1694 /* copy from receive buffer */
1695 cur_bd = 0;
1696 offset = 0;
1697 while (offset < pkt_len && cur_bd < bd_count) {
1698 int len = le32_to_cpu(lp->rfd_cur->bd[cur_bd].BDCtl) &
1699 BD_BuffLength_MASK;
1700 dma_addr_t dma = le32_to_cpu(lp->rfd_cur->bd[cur_bd].BuffData);
1701 void *rxbuf = rxbuf_bus_to_virt(lp, dma);
1702 if (offset + len > pkt_len)
1703 len = pkt_len - offset;
1704 #ifdef TC35815_DMA_SYNC_ONDEMAND
1705 pci_dma_sync_single_for_cpu(lp->pci_dev,
1706 dma, len,
1707 PCI_DMA_FROMDEVICE);
1708 #endif
1709 memcpy(data + offset, rxbuf, len);
1710 #ifdef TC35815_DMA_SYNC_ONDEMAND
1711 pci_dma_sync_single_for_device(lp->pci_dev,
1712 dma, len,
1713 PCI_DMA_FROMDEVICE);
1714 #endif
1715 offset += len;
1716 cur_bd++;
1717 }
1718 #else /* TC35815_USE_PACKEDBUFFER */
1719 BUG_ON(bd_count > 1);
1720 cur_bd = (le32_to_cpu(lp->rfd_cur->bd[0].BDCtl)
1721 & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1722 #ifdef DEBUG
1723 if (cur_bd >= RX_BUF_NUM) {
1724 printk("%s: invalid BDID.\n", dev->name);
1725 panic_queues(dev);
1726 }
1727 BUG_ON(lp->rx_skbs[cur_bd].skb_dma !=
1728 (le32_to_cpu(lp->rfd_cur->bd[0].BuffData) & ~3));
1729 if (!lp->rx_skbs[cur_bd].skb) {
1730 printk("%s: NULL skb.\n", dev->name);
1731 panic_queues(dev);
1732 }
1733 #else
1734 BUG_ON(cur_bd >= RX_BUF_NUM);
1735 #endif
1736 skb = lp->rx_skbs[cur_bd].skb;
1737 prefetch(skb->data);
1738 lp->rx_skbs[cur_bd].skb = NULL;
1739 pci_unmap_single(lp->pci_dev,
1740 lp->rx_skbs[cur_bd].skb_dma,
1741 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1742 if (!HAVE_DMA_RXALIGN(lp))
1743 memmove(skb->data, skb->data - 2, pkt_len);
1744 data = skb_put(skb, pkt_len);
1745 #endif /* TC35815_USE_PACKEDBUFFER */
1746 if (netif_msg_pktdata(lp))
1747 print_eth(data);
1748 skb->protocol = eth_type_trans(skb, dev);
1749 #ifdef TC35815_NAPI
1750 netif_receive_skb(skb);
1751 received++;
1752 #else
1753 netif_rx(skb);
1754 #endif
1755 dev->last_rx = jiffies;
1756 dev->stats.rx_packets++;
1757 dev->stats.rx_bytes += pkt_len;
1758 } else {
1759 dev->stats.rx_errors++;
1760 printk(KERN_DEBUG "%s: Rx error (status %x)\n",
1761 dev->name, status & Rx_Stat_Mask);
1762 /* WORKAROUND: LongErr and CRCErr means Overflow. */
1763 if ((status & Rx_LongErr) && (status & Rx_CRCErr)) {
1764 status &= ~(Rx_LongErr|Rx_CRCErr);
1765 status |= Rx_Over;
1766 }
1767 if (status & Rx_LongErr)
1768 dev->stats.rx_length_errors++;
1769 if (status & Rx_Over)
1770 dev->stats.rx_fifo_errors++;
1771 if (status & Rx_CRCErr)
1772 dev->stats.rx_crc_errors++;
1773 if (status & Rx_Align)
1774 dev->stats.rx_frame_errors++;
1775 }
1776
1777 if (bd_count > 0) {
1778 /* put Free Buffer back to controller */
1779 int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl);
1780 unsigned char id =
1781 (bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1782 #ifdef DEBUG
1783 if (id >= RX_BUF_NUM) {
1784 printk("%s: invalid BDID.\n", dev->name);
1785 panic_queues(dev);
1786 }
1787 #else
1788 BUG_ON(id >= RX_BUF_NUM);
1789 #endif
1790 /* free old buffers */
1791 #ifdef TC35815_USE_PACKEDBUFFER
1792 while (lp->fbl_curid != id)
1793 #else
1794 lp->fbl_count--;
1795 while (lp->fbl_count < RX_BUF_NUM)
1796 #endif
1797 {
1798 #ifdef TC35815_USE_PACKEDBUFFER
1799 unsigned char curid = lp->fbl_curid;
1800 #else
1801 unsigned char curid =
1802 (id + 1 + lp->fbl_count) % RX_BUF_NUM;
1803 #endif
1804 struct BDesc *bd = &lp->fbl_ptr->bd[curid];
1805 #ifdef DEBUG
1806 bdctl = le32_to_cpu(bd->BDCtl);
1807 if (bdctl & BD_CownsBD) {
1808 printk("%s: Freeing invalid BD.\n",
1809 dev->name);
1810 panic_queues(dev);
1811 }
1812 #endif
1813 /* pass BD to controller */
1814 #ifndef TC35815_USE_PACKEDBUFFER
1815 if (!lp->rx_skbs[curid].skb) {
1816 lp->rx_skbs[curid].skb =
1817 alloc_rxbuf_skb(dev,
1818 lp->pci_dev,
1819 &lp->rx_skbs[curid].skb_dma);
1820 if (!lp->rx_skbs[curid].skb)
1821 break; /* try on next reception */
1822 bd->BuffData = cpu_to_le32(lp->rx_skbs[curid].skb_dma);
1823 }
1824 #endif /* TC35815_USE_PACKEDBUFFER */
1825 /* Note: BDLength was modified by chip. */
1826 bd->BDCtl = cpu_to_le32(BD_CownsBD |
1827 (curid << BD_RxBDID_SHIFT) |
1828 RX_BUF_SIZE);
1829 #ifdef TC35815_USE_PACKEDBUFFER
1830 lp->fbl_curid = (curid + 1) % RX_BUF_NUM;
1831 if (netif_msg_rx_status(lp)) {
1832 printk("%s: Entering new FBD %d\n",
1833 dev->name, lp->fbl_curid);
1834 dump_frfd(lp->fbl_ptr);
1835 }
1836 #else
1837 lp->fbl_count++;
1838 #endif
1839 buf_free_count++;
1840 }
1841 }
1842
1843 /* put RxFD back to controller */
1844 #ifdef DEBUG
1845 next_rfd = fd_bus_to_virt(lp,
1846 le32_to_cpu(lp->rfd_cur->fd.FDNext));
1847 if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) {
1848 printk("%s: RxFD FDNext invalid.\n", dev->name);
1849 panic_queues(dev);
1850 }
1851 #endif
1852 for (i = 0; i < (bd_count + 1) / 2 + 1; i++) {
1853 /* pass FD to controller */
1854 #ifdef DEBUG
1855 lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead);
1856 #else
1857 lp->rfd_cur->fd.FDNext = cpu_to_le32(FD_Next_EOL);
1858 #endif
1859 lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD);
1860 lp->rfd_cur++;
1861 fd_free_count++;
1862 }
1863 if (lp->rfd_cur > lp->rfd_limit)
1864 lp->rfd_cur = lp->rfd_base;
1865 #ifdef DEBUG
1866 if (lp->rfd_cur != next_rfd)
1867 printk("rfd_cur = %p, next_rfd %p\n",
1868 lp->rfd_cur, next_rfd);
1869 #endif
1870 }
1871
1872 /* re-enable BL/FDA Exhaust interrupts. */
1873 if (fd_free_count) {
1874 struct tc35815_regs __iomem *tr =
1875 (struct tc35815_regs __iomem *)dev->base_addr;
1876 u32 en, en_old = tc_readl(&tr->Int_En);
1877 en = en_old | Int_FDAExEn;
1878 if (buf_free_count)
1879 en |= Int_BLExEn;
1880 if (en != en_old)
1881 tc_writel(en, &tr->Int_En);
1882 }
1883 #ifdef TC35815_NAPI
1884 return received;
1885 #endif
1886 }
1887
1888 #ifdef TC35815_NAPI
1889 static int tc35815_poll(struct napi_struct *napi, int budget)
1890 {
1891 struct tc35815_local *lp = container_of(napi, struct tc35815_local, napi);
1892 struct net_device *dev = lp->dev;
1893 struct tc35815_regs __iomem *tr =
1894 (struct tc35815_regs __iomem *)dev->base_addr;
1895 int received = 0, handled;
1896 u32 status;
1897
1898 spin_lock(&lp->lock);
1899 status = tc_readl(&tr->Int_Src);
1900 do {
1901 tc_writel(status, &tr->Int_Src); /* write to clear */
1902
1903 handled = tc35815_do_interrupt(dev, status, limit);
1904 if (handled >= 0) {
1905 received += handled;
1906 if (received >= budget)
1907 break;
1908 }
1909 status = tc_readl(&tr->Int_Src);
1910 } while (status);
1911 spin_unlock(&lp->lock);
1912
1913 if (received < budget) {
1914 netif_rx_complete(dev, napi);
1915 /* enable interrupts */
1916 tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl);
1917 }
1918 return received;
1919 }
1920 #endif
1921
1922 #ifdef NO_CHECK_CARRIER
1923 #define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1924 #else
1925 #define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1926 #endif
1927
1928 static void
1929 tc35815_check_tx_stat(struct net_device *dev, int status)
1930 {
1931 struct tc35815_local *lp = netdev_priv(dev);
1932 const char *msg = NULL;
1933
1934 /* count collisions */
1935 if (status & Tx_ExColl)
1936 dev->stats.collisions += 16;
1937 if (status & Tx_TxColl_MASK)
1938 dev->stats.collisions += status & Tx_TxColl_MASK;
1939
1940 #ifndef NO_CHECK_CARRIER
1941 /* TX4939 does not have NCarr */
1942 if (lp->chiptype == TC35815_TX4939)
1943 status &= ~Tx_NCarr;
1944 #ifdef WORKAROUND_LOSTCAR
1945 /* WORKAROUND: ignore LostCrS in full duplex operation */
1946 if (!lp->link || lp->duplex == DUPLEX_FULL)
1947 status &= ~Tx_NCarr;
1948 #endif
1949 #endif
1950
1951 if (!(status & TX_STA_ERR)) {
1952 /* no error. */
1953 dev->stats.tx_packets++;
1954 return;
1955 }
1956
1957 dev->stats.tx_errors++;
1958 if (status & Tx_ExColl) {
1959 dev->stats.tx_aborted_errors++;
1960 msg = "Excessive Collision.";
1961 }
1962 if (status & Tx_Under) {
1963 dev->stats.tx_fifo_errors++;
1964 msg = "Tx FIFO Underrun.";
1965 if (lp->lstats.tx_underrun < TX_THRESHOLD_KEEP_LIMIT) {
1966 lp->lstats.tx_underrun++;
1967 if (lp->lstats.tx_underrun >= TX_THRESHOLD_KEEP_LIMIT) {
1968 struct tc35815_regs __iomem *tr =
1969 (struct tc35815_regs __iomem *)dev->base_addr;
1970 tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh);
1971 msg = "Tx FIFO Underrun.Change Tx threshold to max.";
1972 }
1973 }
1974 }
1975 if (status & Tx_Defer) {
1976 dev->stats.tx_fifo_errors++;
1977 msg = "Excessive Deferral.";
1978 }
1979 #ifndef NO_CHECK_CARRIER
1980 if (status & Tx_NCarr) {
1981 dev->stats.tx_carrier_errors++;
1982 msg = "Lost Carrier Sense.";
1983 }
1984 #endif
1985 if (status & Tx_LateColl) {
1986 dev->stats.tx_aborted_errors++;
1987 msg = "Late Collision.";
1988 }
1989 if (status & Tx_TxPar) {
1990 dev->stats.tx_fifo_errors++;
1991 msg = "Transmit Parity Error.";
1992 }
1993 if (status & Tx_SQErr) {
1994 dev->stats.tx_heartbeat_errors++;
1995 msg = "Signal Quality Error.";
1996 }
1997 if (msg && netif_msg_tx_err(lp))
1998 printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status);
1999 }
2000
2001 /* This handles TX complete events posted by the device
2002 * via interrupts.
2003 */
2004 static void
2005 tc35815_txdone(struct net_device *dev)
2006 {
2007 struct tc35815_local *lp = netdev_priv(dev);
2008 struct TxFD *txfd;
2009 unsigned int fdctl;
2010
2011 txfd = &lp->tfd_base[lp->tfd_end];
2012 while (lp->tfd_start != lp->tfd_end &&
2013 !((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) {
2014 int status = le32_to_cpu(txfd->fd.FDStat);
2015 struct sk_buff *skb;
2016 unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext);
2017 u32 fdsystem = le32_to_cpu(txfd->fd.FDSystem);
2018
2019 if (netif_msg_tx_done(lp)) {
2020 printk("%s: complete TxFD.\n", dev->name);
2021 dump_txfd(txfd);
2022 }
2023 tc35815_check_tx_stat(dev, status);
2024
2025 skb = fdsystem != 0xffffffff ?
2026 lp->tx_skbs[fdsystem].skb : NULL;
2027 #ifdef DEBUG
2028 if (lp->tx_skbs[lp->tfd_end].skb != skb) {
2029 printk("%s: tx_skbs mismatch.\n", dev->name);
2030 panic_queues(dev);
2031 }
2032 #else
2033 BUG_ON(lp->tx_skbs[lp->tfd_end].skb != skb);
2034 #endif
2035 if (skb) {
2036 dev->stats.tx_bytes += skb->len;
2037 pci_unmap_single(lp->pci_dev, lp->tx_skbs[lp->tfd_end].skb_dma, skb->len, PCI_DMA_TODEVICE);
2038 lp->tx_skbs[lp->tfd_end].skb = NULL;
2039 lp->tx_skbs[lp->tfd_end].skb_dma = 0;
2040 #ifdef TC35815_NAPI
2041 dev_kfree_skb_any(skb);
2042 #else
2043 dev_kfree_skb_irq(skb);
2044 #endif
2045 }
2046 txfd->fd.FDSystem = cpu_to_le32(0xffffffff);
2047
2048 lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM;
2049 txfd = &lp->tfd_base[lp->tfd_end];
2050 #ifdef DEBUG
2051 if ((fdnext & ~FD_Next_EOL) != fd_virt_to_bus(lp, txfd)) {
2052 printk("%s: TxFD FDNext invalid.\n", dev->name);
2053 panic_queues(dev);
2054 }
2055 #endif
2056 if (fdnext & FD_Next_EOL) {
2057 /* DMA Transmitter has been stopping... */
2058 if (lp->tfd_end != lp->tfd_start) {
2059 struct tc35815_regs __iomem *tr =
2060 (struct tc35815_regs __iomem *)dev->base_addr;
2061 int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM;
2062 struct TxFD *txhead = &lp->tfd_base[head];
2063 int qlen = (lp->tfd_start + TX_FD_NUM
2064 - lp->tfd_end) % TX_FD_NUM;
2065
2066 #ifdef DEBUG
2067 if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) {
2068 printk("%s: TxFD FDCtl invalid.\n", dev->name);
2069 panic_queues(dev);
2070 }
2071 #endif
2072 /* log max queue length */
2073 if (lp->lstats.max_tx_qlen < qlen)
2074 lp->lstats.max_tx_qlen = qlen;
2075
2076
2077 /* start DMA Transmitter again */
2078 txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
2079 #ifdef GATHER_TXINT
2080 txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
2081 #endif
2082 if (netif_msg_tx_queued(lp)) {
2083 printk("%s: start TxFD on queue.\n",
2084 dev->name);
2085 dump_txfd(txfd);
2086 }
2087 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
2088 }
2089 break;
2090 }
2091 }
2092
2093 /* If we had stopped the queue due to a "tx full"
2094 * condition, and space has now been made available,
2095 * wake up the queue.
2096 */
2097 if (netif_queue_stopped(dev) && !tc35815_tx_full(dev))
2098 netif_wake_queue(dev);
2099 }
2100
2101 /* The inverse routine to tc35815_open(). */
2102 static int
2103 tc35815_close(struct net_device *dev)
2104 {
2105 struct tc35815_local *lp = netdev_priv(dev);
2106
2107 netif_stop_queue(dev);
2108 #ifdef TC35815_NAPI
2109 napi_disable(&lp->napi);
2110 #endif
2111 if (lp->phy_dev)
2112 phy_stop(lp->phy_dev);
2113 cancel_work_sync(&lp->restart_work);
2114
2115 /* Flush the Tx and disable Rx here. */
2116 tc35815_chip_reset(dev);
2117 free_irq(dev->irq, dev);
2118
2119 tc35815_free_queues(dev);
2120
2121 return 0;
2122
2123 }
2124
2125 /*
2126 * Get the current statistics.
2127 * This may be called with the card open or closed.
2128 */
2129 static struct net_device_stats *tc35815_get_stats(struct net_device *dev)
2130 {
2131 struct tc35815_regs __iomem *tr =
2132 (struct tc35815_regs __iomem *)dev->base_addr;
2133 if (netif_running(dev))
2134 /* Update the statistics from the device registers. */
2135 dev->stats.rx_missed_errors = tc_readl(&tr->Miss_Cnt);
2136
2137 return &dev->stats;
2138 }
2139
2140 static void tc35815_set_cam_entry(struct net_device *dev, int index, unsigned char *addr)
2141 {
2142 struct tc35815_local *lp = netdev_priv(dev);
2143 struct tc35815_regs __iomem *tr =
2144 (struct tc35815_regs __iomem *)dev->base_addr;
2145 int cam_index = index * 6;
2146 u32 cam_data;
2147 u32 saved_addr;
2148 DECLARE_MAC_BUF(mac);
2149
2150 saved_addr = tc_readl(&tr->CAM_Adr);
2151
2152 if (netif_msg_hw(lp))
2153 printk(KERN_DEBUG "%s: CAM %d: %s\n",
2154 dev->name, index, print_mac(mac, addr));
2155 if (index & 1) {
2156 /* read modify write */
2157 tc_writel(cam_index - 2, &tr->CAM_Adr);
2158 cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000;
2159 cam_data |= addr[0] << 8 | addr[1];
2160 tc_writel(cam_data, &tr->CAM_Data);
2161 /* write whole word */
2162 tc_writel(cam_index + 2, &tr->CAM_Adr);
2163 cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
2164 tc_writel(cam_data, &tr->CAM_Data);
2165 } else {
2166 /* write whole word */
2167 tc_writel(cam_index, &tr->CAM_Adr);
2168 cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
2169 tc_writel(cam_data, &tr->CAM_Data);
2170 /* read modify write */
2171 tc_writel(cam_index + 4, &tr->CAM_Adr);
2172 cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff;
2173 cam_data |= addr[4] << 24 | (addr[5] << 16);
2174 tc_writel(cam_data, &tr->CAM_Data);
2175 }
2176
2177 tc_writel(saved_addr, &tr->CAM_Adr);
2178 }
2179
2180
2181 /*
2182 * Set or clear the multicast filter for this adaptor.
2183 * num_addrs == -1 Promiscuous mode, receive all packets
2184 * num_addrs == 0 Normal mode, clear multicast list
2185 * num_addrs > 0 Multicast mode, receive normal and MC packets,
2186 * and do best-effort filtering.
2187 */
2188 static void
2189 tc35815_set_multicast_list(struct net_device *dev)
2190 {
2191 struct tc35815_regs __iomem *tr =
2192 (struct tc35815_regs __iomem *)dev->base_addr;
2193
2194 if (dev->flags & IFF_PROMISC) {
2195 #ifdef WORKAROUND_100HALF_PROMISC
2196 /* With some (all?) 100MHalf HUB, controller will hang
2197 * if we enabled promiscuous mode before linkup... */
2198 struct tc35815_local *lp = netdev_priv(dev);
2199
2200 if (!lp->link)
2201 return;
2202 #endif
2203 /* Enable promiscuous mode */
2204 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl);
2205 } else if ((dev->flags & IFF_ALLMULTI) ||
2206 dev->mc_count > CAM_ENTRY_MAX - 3) {
2207 /* CAM 0, 1, 20 are reserved. */
2208 /* Disable promiscuous mode, use normal mode. */
2209 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl);
2210 } else if (dev->mc_count) {
2211 struct dev_mc_list *cur_addr = dev->mc_list;
2212 int i;
2213 int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE);
2214
2215 tc_writel(0, &tr->CAM_Ctl);
2216 /* Walk the address list, and load the filter */
2217 for (i = 0; i < dev->mc_count; i++, cur_addr = cur_addr->next) {
2218 if (!cur_addr)
2219 break;
2220 /* entry 0,1 is reserved. */
2221 tc35815_set_cam_entry(dev, i + 2, cur_addr->dmi_addr);
2222 ena_bits |= CAM_Ena_Bit(i + 2);
2223 }
2224 tc_writel(ena_bits, &tr->CAM_Ena);
2225 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2226 } else {
2227 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
2228 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2229 }
2230 }
2231
2232 static void tc35815_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2233 {
2234 struct tc35815_local *lp = netdev_priv(dev);
2235 strcpy(info->driver, MODNAME);
2236 strcpy(info->version, DRV_VERSION);
2237 strcpy(info->bus_info, pci_name(lp->pci_dev));
2238 }
2239
2240 static int tc35815_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2241 {
2242 struct tc35815_local *lp = netdev_priv(dev);
2243
2244 if (!lp->phy_dev)
2245 return -ENODEV;
2246 return phy_ethtool_gset(lp->phy_dev, cmd);
2247 }
2248
2249 static int tc35815_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2250 {
2251 struct tc35815_local *lp = netdev_priv(dev);
2252
2253 if (!lp->phy_dev)
2254 return -ENODEV;
2255 return phy_ethtool_sset(lp->phy_dev, cmd);
2256 }
2257
2258 static u32 tc35815_get_msglevel(struct net_device *dev)
2259 {
2260 struct tc35815_local *lp = netdev_priv(dev);
2261 return lp->msg_enable;
2262 }
2263
2264 static void tc35815_set_msglevel(struct net_device *dev, u32 datum)
2265 {
2266 struct tc35815_local *lp = netdev_priv(dev);
2267 lp->msg_enable = datum;
2268 }
2269
2270 static int tc35815_get_sset_count(struct net_device *dev, int sset)
2271 {
2272 struct tc35815_local *lp = netdev_priv(dev);
2273
2274 switch (sset) {
2275 case ETH_SS_STATS:
2276 return sizeof(lp->lstats) / sizeof(int);
2277 default:
2278 return -EOPNOTSUPP;
2279 }
2280 }
2281
2282 static void tc35815_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2283 {
2284 struct tc35815_local *lp = netdev_priv(dev);
2285 data[0] = lp->lstats.max_tx_qlen;
2286 data[1] = lp->lstats.tx_ints;
2287 data[2] = lp->lstats.rx_ints;
2288 data[3] = lp->lstats.tx_underrun;
2289 }
2290
2291 static struct {
2292 const char str[ETH_GSTRING_LEN];
2293 } ethtool_stats_keys[] = {
2294 { "max_tx_qlen" },
2295 { "tx_ints" },
2296 { "rx_ints" },
2297 { "tx_underrun" },
2298 };
2299
2300 static void tc35815_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2301 {
2302 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2303 }
2304
2305 static const struct ethtool_ops tc35815_ethtool_ops = {
2306 .get_drvinfo = tc35815_get_drvinfo,
2307 .get_settings = tc35815_get_settings,
2308 .set_settings = tc35815_set_settings,
2309 .get_link = ethtool_op_get_link,
2310 .get_msglevel = tc35815_get_msglevel,
2311 .set_msglevel = tc35815_set_msglevel,
2312 .get_strings = tc35815_get_strings,
2313 .get_sset_count = tc35815_get_sset_count,
2314 .get_ethtool_stats = tc35815_get_ethtool_stats,
2315 };
2316
2317 static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2318 {
2319 struct tc35815_local *lp = netdev_priv(dev);
2320
2321 if (!netif_running(dev))
2322 return -EINVAL;
2323 if (!lp->phy_dev)
2324 return -ENODEV;
2325 return phy_mii_ioctl(lp->phy_dev, if_mii(rq), cmd);
2326 }
2327
2328 static void tc35815_chip_reset(struct net_device *dev)
2329 {
2330 struct tc35815_regs __iomem *tr =
2331 (struct tc35815_regs __iomem *)dev->base_addr;
2332 int i;
2333 /* reset the controller */
2334 tc_writel(MAC_Reset, &tr->MAC_Ctl);
2335 udelay(4); /* 3200ns */
2336 i = 0;
2337 while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) {
2338 if (i++ > 100) {
2339 printk(KERN_ERR "%s: MAC reset failed.\n", dev->name);
2340 break;
2341 }
2342 mdelay(1);
2343 }
2344 tc_writel(0, &tr->MAC_Ctl);
2345
2346 /* initialize registers to default value */
2347 tc_writel(0, &tr->DMA_Ctl);
2348 tc_writel(0, &tr->TxThrsh);
2349 tc_writel(0, &tr->TxPollCtr);
2350 tc_writel(0, &tr->RxFragSize);
2351 tc_writel(0, &tr->Int_En);
2352 tc_writel(0, &tr->FDA_Bas);
2353 tc_writel(0, &tr->FDA_Lim);
2354 tc_writel(0xffffffff, &tr->Int_Src); /* Write 1 to clear */
2355 tc_writel(0, &tr->CAM_Ctl);
2356 tc_writel(0, &tr->Tx_Ctl);
2357 tc_writel(0, &tr->Rx_Ctl);
2358 tc_writel(0, &tr->CAM_Ena);
2359 (void)tc_readl(&tr->Miss_Cnt); /* Read to clear */
2360
2361 /* initialize internal SRAM */
2362 tc_writel(DMA_TestMode, &tr->DMA_Ctl);
2363 for (i = 0; i < 0x1000; i += 4) {
2364 tc_writel(i, &tr->CAM_Adr);
2365 tc_writel(0, &tr->CAM_Data);
2366 }
2367 tc_writel(0, &tr->DMA_Ctl);
2368 }
2369
2370 static void tc35815_chip_init(struct net_device *dev)
2371 {
2372 struct tc35815_local *lp = netdev_priv(dev);
2373 struct tc35815_regs __iomem *tr =
2374 (struct tc35815_regs __iomem *)dev->base_addr;
2375 unsigned long txctl = TX_CTL_CMD;
2376
2377 /* load station address to CAM */
2378 tc35815_set_cam_entry(dev, CAM_ENTRY_SOURCE, dev->dev_addr);
2379
2380 /* Enable CAM (broadcast and unicast) */
2381 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
2382 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2383
2384 /* Use DMA_RxAlign_2 to make IP header 4-byte aligned. */
2385 if (HAVE_DMA_RXALIGN(lp))
2386 tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl);
2387 else
2388 tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl);
2389 #ifdef TC35815_USE_PACKEDBUFFER
2390 tc_writel(RxFrag_EnPack | ETH_ZLEN, &tr->RxFragSize); /* Packing */
2391 #else
2392 tc_writel(ETH_ZLEN, &tr->RxFragSize);
2393 #endif
2394 tc_writel(0, &tr->TxPollCtr); /* Batch mode */
2395 tc_writel(TX_THRESHOLD, &tr->TxThrsh);
2396 tc_writel(INT_EN_CMD, &tr->Int_En);
2397
2398 /* set queues */
2399 tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas);
2400 tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base,
2401 &tr->FDA_Lim);
2402 /*
2403 * Activation method:
2404 * First, enable the MAC Transmitter and the DMA Receive circuits.
2405 * Then enable the DMA Transmitter and the MAC Receive circuits.
2406 */
2407 tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr); /* start DMA receiver */
2408 tc_writel(RX_CTL_CMD, &tr->Rx_Ctl); /* start MAC receiver */
2409
2410 /* start MAC transmitter */
2411 #ifndef NO_CHECK_CARRIER
2412 /* TX4939 does not have EnLCarr */
2413 if (lp->chiptype == TC35815_TX4939)
2414 txctl &= ~Tx_EnLCarr;
2415 #ifdef WORKAROUND_LOSTCAR
2416 /* WORKAROUND: ignore LostCrS in full duplex operation */
2417 if (!lp->phy_dev || !lp->link || lp->duplex == DUPLEX_FULL)
2418 txctl &= ~Tx_EnLCarr;
2419 #endif
2420 #endif /* !NO_CHECK_CARRIER */
2421 #ifdef GATHER_TXINT
2422 txctl &= ~Tx_EnComp; /* disable global tx completion int. */
2423 #endif
2424 tc_writel(txctl, &tr->Tx_Ctl);
2425 }
2426
2427 #ifdef CONFIG_PM
2428 static int tc35815_suspend(struct pci_dev *pdev, pm_message_t state)
2429 {
2430 struct net_device *dev = pci_get_drvdata(pdev);
2431 struct tc35815_local *lp = netdev_priv(dev);
2432 unsigned long flags;
2433
2434 pci_save_state(pdev);
2435 if (!netif_running(dev))
2436 return 0;
2437 netif_device_detach(dev);
2438 if (lp->phy_dev)
2439 phy_stop(lp->phy_dev);
2440 spin_lock_irqsave(&lp->lock, flags);
2441 tc35815_chip_reset(dev);
2442 spin_unlock_irqrestore(&lp->lock, flags);
2443 pci_set_power_state(pdev, PCI_D3hot);
2444 return 0;
2445 }
2446
2447 static int tc35815_resume(struct pci_dev *pdev)
2448 {
2449 struct net_device *dev = pci_get_drvdata(pdev);
2450 struct tc35815_local *lp = netdev_priv(dev);
2451
2452 pci_restore_state(pdev);
2453 if (!netif_running(dev))
2454 return 0;
2455 pci_set_power_state(pdev, PCI_D0);
2456 tc35815_restart(dev);
2457 netif_carrier_off(dev);
2458 if (lp->phy_dev)
2459 phy_start(lp->phy_dev);
2460 netif_device_attach(dev);
2461 return 0;
2462 }
2463 #endif /* CONFIG_PM */
2464
2465 static struct pci_driver tc35815_pci_driver = {
2466 .name = MODNAME,
2467 .id_table = tc35815_pci_tbl,
2468 .probe = tc35815_init_one,
2469 .remove = __devexit_p(tc35815_remove_one),
2470 #ifdef CONFIG_PM
2471 .suspend = tc35815_suspend,
2472 .resume = tc35815_resume,
2473 #endif
2474 };
2475
2476 module_param_named(speed, options.speed, int, 0);
2477 MODULE_PARM_DESC(speed, "0:auto, 10:10Mbps, 100:100Mbps");
2478 module_param_named(duplex, options.duplex, int, 0);
2479 MODULE_PARM_DESC(duplex, "0:auto, 1:half, 2:full");
2480
2481 static int __init tc35815_init_module(void)
2482 {
2483 return pci_register_driver(&tc35815_pci_driver);
2484 }
2485
2486 static void __exit tc35815_cleanup_module(void)
2487 {
2488 pci_unregister_driver(&tc35815_pci_driver);
2489 }
2490
2491 module_init(tc35815_init_module);
2492 module_exit(tc35815_cleanup_module);
2493
2494 MODULE_DESCRIPTION("TOSHIBA TC35815 PCI 10M/100M Ethernet driver");
2495 MODULE_LICENSE("GPL");
Linux for Ginger Game Console