arch/arm/mach-davinci/psc.c

   1 /*
   2  * TI DaVinci Power and Sleep Controller (PSC)
   3  *
   4  * Copyright (C) 2006 Texas Instruments.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  *
  20  */
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/init.h>
  24 #include <linux/io.h>
  25
  26 #include <mach/cputype.h>
  27 #include <mach/hardware.h>
  28 #include <mach/psc.h>
  29 #include <mach/mux.h>
  30
  31 /* PSC register offsets */
  32 #define EPCPR           0x070
  33 #define PTCMD           0x120
  34 #define PTSTAT          0x128
  35 #define PDSTAT          0x200
  36 #define PDCTL1          0x304
  37 #define MDSTAT          0x800
  38 #define MDCTL           0xA00
  39
  40
  41 /* Return nonzero iff the domain's clock is active */
  42 int __init davinci_psc_is_clk_active(unsigned int id)
  43 {
  44         void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE);
  45         u32 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
  46
  47         /* if clocked, state can be "Enable" or "SyncReset" */
  48         return mdstat & BIT(12);
  49 }
  50
  51 /* Enable or disable a PSC domain */
  52 void davinci_psc_config(unsigned int domain, unsigned int id, char enable)
  53 {
  54         u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl, mdstat_mask;
  55         void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE);
  56
  57         mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
  58         if (enable)
  59                 mdctl |= 0x00000003;    /* Enable Module */
  60         else
  61                 mdctl &= 0xFFFFFFE2;    /* Disable Module */
  62         __raw_writel(mdctl, psc_base + MDCTL + 4 * id);
  63
  64         pdstat = __raw_readl(psc_base + PDSTAT);
  65         if ((pdstat & 0x00000001) == 0) {
  66                 pdctl1 = __raw_readl(psc_base + PDCTL1);
  67                 pdctl1 |= 0x1;
  68                 __raw_writel(pdctl1, psc_base + PDCTL1);
  69
  70                 ptcmd = 1 << domain;
  71                 __raw_writel(ptcmd, psc_base + PTCMD);
  72
  73                 do {
  74                         epcpr = __raw_readl(psc_base + EPCPR);
  75                 } while ((((epcpr >> domain) & 1) == 0));
  76
  77                 pdctl1 = __raw_readl(psc_base + PDCTL1);
  78                 pdctl1 |= 0x100;
  79                 __raw_writel(pdctl1, psc_base + PDCTL1);
  80
  81                 do {
  82                         ptstat = __raw_readl(psc_base +
  83                                                PTSTAT);
  84                 } while (!(((ptstat >> domain) & 1) == 0));
  85         } else {
  86                 ptcmd = 1 << domain;
  87                 __raw_writel(ptcmd, psc_base + PTCMD);
  88
  89                 do {
  90                         ptstat = __raw_readl(psc_base + PTSTAT);
  91                 } while (!(((ptstat >> domain) & 1) == 0));
  92         }
  93
  94         if (enable)
  95                 mdstat_mask = 0x3;
  96         else
  97                 mdstat_mask = 0x2;
  98
  99         do {
 100                 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
 101         } while (!((mdstat & 0x0000001F) == mdstat_mask));
 102 }