arch/arm/mach-davinci/time.c

   1 /*
   2  * DaVinci timer subsystem
   3  *
   4  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
   5  *
   6  * 2007 (c) MontaVista Software, Inc. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/clocksource.h>
  16 #include <linux/clockchips.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/io.h>
  19 #include <linux/clk.h>
  20 #include <linux/err.h>
  21 #include <linux/device.h>
  22
  23 #include <mach/hardware.h>
  24 #include <asm/system.h>
  25 #include <asm/irq.h>
  26 #include <asm/mach/irq.h>
  27 #include <asm/mach/time.h>
  28 #include <asm/errno.h>
  29 #include <mach/io.h>
  30 #include <mach/cputype.h>
  31 #include "clock.h"
  32
  33 static struct clock_event_device clockevent_davinci;
  34 static unsigned int davinci_clock_tick_rate;
  35
  36 #define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400)
  37 #define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800)
  38 #define DAVINCI_WDOG_BASE   (IO_PHYS + 0x21C00)
  39
  40 enum {
  41         T0_BOT = 0, T0_TOP, T1_BOT, T1_TOP, NUM_TIMERS,
  42 };
  43
  44 #define IS_TIMER1(id)    (id & 0x2)
  45 #define IS_TIMER0(id)    (!IS_TIMER1(id))
  46 #define IS_TIMER_TOP(id) ((id & 0x1))
  47 #define IS_TIMER_BOT(id) (!IS_TIMER_TOP(id))
  48
  49 static int timer_irqs[NUM_TIMERS] = {
  50         IRQ_TINT0_TINT12,
  51         IRQ_TINT0_TINT34,
  52         IRQ_TINT1_TINT12,
  53         IRQ_TINT1_TINT34,
  54 };
  55
  56 /*
  57  * This driver configures the 2 64-bit count-up timers as 4 independent
  58  * 32-bit count-up timers used as follows:
  59  *
  60  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
  61  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
  62  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
  63  * T1_TOP: Timer 1, top   :  <unused>
  64  */
  65 #define TID_CLOCKEVENT  T0_BOT
  66 #define TID_CLOCKSOURCE T0_TOP
  67
  68 /* Timer register offsets */
  69 #define PID12                        0x0
  70 #define TIM12                        0x10
  71 #define TIM34                        0x14
  72 #define PRD12                        0x18
  73 #define PRD34                        0x1c
  74 #define TCR                          0x20
  75 #define TGCR                         0x24
  76 #define WDTCR                        0x28
  77
  78 /* Timer register bitfields */
  79 #define TCR_ENAMODE_DISABLE          0x0
  80 #define TCR_ENAMODE_ONESHOT          0x1
  81 #define TCR_ENAMODE_PERIODIC         0x2
  82 #define TCR_ENAMODE_MASK             0x3
  83
  84 #define TGCR_TIMMODE_SHIFT           2
  85 #define TGCR_TIMMODE_64BIT_GP        0x0
  86 #define TGCR_TIMMODE_32BIT_UNCHAINED 0x1
  87 #define TGCR_TIMMODE_64BIT_WDOG      0x2
  88 #define TGCR_TIMMODE_32BIT_CHAINED   0x3
  89
  90 #define TGCR_TIM12RS_SHIFT           0
  91 #define TGCR_TIM34RS_SHIFT           1
  92 #define TGCR_RESET                   0x0
  93 #define TGCR_UNRESET                 0x1
  94 #define TGCR_RESET_MASK              0x3
  95
  96 #define WDTCR_WDEN_SHIFT             14
  97 #define WDTCR_WDEN_DISABLE           0x0
  98 #define WDTCR_WDEN_ENABLE            0x1
  99 #define WDTCR_WDKEY_SHIFT            16
 100 #define WDTCR_WDKEY_SEQ0             0xa5c6
 101 #define WDTCR_WDKEY_SEQ1             0xda7e
 102
 103 struct timer_s {
 104         char *name;
 105         unsigned int id;
 106         unsigned long period;
 107         unsigned long opts;
 108         void __iomem *base;
 109         unsigned long tim_off;
 110         unsigned long prd_off;
 111         unsigned long enamode_shift;
 112         struct irqaction irqaction;
 113 };
 114 static struct timer_s timers[];
 115
 116 /* values for 'opts' field of struct timer_s */
 117 #define TIMER_OPTS_DISABLED   0x00
 118 #define TIMER_OPTS_ONESHOT    0x01
 119 #define TIMER_OPTS_PERIODIC   0x02
 120
 121 static int timer32_config(struct timer_s *t)
 122 {
 123         u32 tcr = __raw_readl(t->base + TCR);
 124
 125         /* disable timer */
 126         tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift);
 127         __raw_writel(tcr, t->base + TCR);
 128
 129         /* reset counter to zero, set new period */
 130         __raw_writel(0, t->base + t->tim_off);
 131         __raw_writel(t->period, t->base + t->prd_off);
 132
 133         /* Set enable mode */
 134         if (t->opts & TIMER_OPTS_ONESHOT) {
 135                 tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift;
 136         } else if (t->opts & TIMER_OPTS_PERIODIC) {
 137                 tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift;
 138         }
 139
 140         __raw_writel(tcr, t->base + TCR);
 141         return 0;
 142 }
 143
 144 static inline u32 timer32_read(struct timer_s *t)
 145 {
 146         return __raw_readl(t->base + t->tim_off);
 147 }
 148
 149 static irqreturn_t timer_interrupt(int irq, void *dev_id)
 150 {
 151         struct clock_event_device *evt = &clockevent_davinci;
 152
 153         evt->event_handler(evt);
 154         return IRQ_HANDLED;
 155 }
 156
 157 /* called when 32-bit counter wraps */
 158 static irqreturn_t freerun_interrupt(int irq, void *dev_id)
 159 {
 160         return IRQ_HANDLED;
 161 }
 162
 163 static struct timer_s timers[] = {
 164         [TID_CLOCKEVENT] = {
 165                 .name      = "clockevent",
 166                 .opts      = TIMER_OPTS_DISABLED,
 167                 .irqaction = {
 168                         .flags   = IRQF_DISABLED | IRQF_TIMER,
 169                         .handler = timer_interrupt,
 170                 }
 171         },
 172         [TID_CLOCKSOURCE] = {
 173                 .name       = "free-run counter",
 174                 .period     = ~0,
 175                 .opts       = TIMER_OPTS_PERIODIC,
 176                 .irqaction = {
 177                         .flags   = IRQF_DISABLED | IRQF_TIMER,
 178                         .handler = freerun_interrupt,
 179                 }
 180         },
 181 };
 182
 183 static void __init timer_init(void)
 184 {
 185         u32 phys_bases[] = {DAVINCI_TIMER0_BASE, DAVINCI_TIMER1_BASE};
 186         int i;
 187
 188         /* Global init of each 64-bit timer as a whole */
 189         for(i=0; i<2; i++) {
 190                 u32 tgcr;
 191                 void __iomem *base = IO_ADDRESS(phys_bases[i]);
 192
 193                 /* Disabled, Internal clock source */
 194                 __raw_writel(0, base + TCR);
 195
 196                 /* reset both timers, no pre-scaler for timer34 */
 197                 tgcr = 0;
 198                 __raw_writel(tgcr, base + TGCR);
 199
 200                 /* Set both timers to unchained 32-bit */
 201                 tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT;
 202                 __raw_writel(tgcr, base + TGCR);
 203
 204                 /* Unreset timers */
 205                 tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
 206                         (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
 207                 __raw_writel(tgcr, base + TGCR);
 208
 209                 /* Init both counters to zero */
 210                 __raw_writel(0, base + TIM12);
 211                 __raw_writel(0, base + TIM34);
 212         }
 213
 214         /* Init of each timer as a 32-bit timer */
 215         for (i=0; i< ARRAY_SIZE(timers); i++) {
 216                 struct timer_s *t = &timers[i];
 217                 u32 phys_base;
 218
 219                 if (t->name) {
 220                         t->id = i;
 221                         phys_base = (IS_TIMER1(t->id) ?
 222                                DAVINCI_TIMER1_BASE : DAVINCI_TIMER0_BASE);
 223                         t->base = IO_ADDRESS(phys_base);
 224
 225                         if (IS_TIMER_BOT(t->id)) {
 226                                 t->enamode_shift = 6;
 227                                 t->tim_off = TIM12;
 228                                 t->prd_off = PRD12;
 229                         } else {
 230                                 t->enamode_shift = 22;
 231                                 t->tim_off = TIM34;
 232                                 t->prd_off = PRD34;
 233                         }
 234
 235                         /* Register interrupt */
 236                         t->irqaction.name = t->name;
 237                         t->irqaction.dev_id = (void *)t;
 238                         if (t->irqaction.handler != NULL) {
 239                                 setup_irq(timer_irqs[t->id], &t->irqaction);
 240                         }
 241
 242                         timer32_config(&timers[i]);
 243                 }
 244         }
 245 }
 246
 247 /*
 248  * clocksource
 249  */
 250 static cycle_t read_cycles(struct clocksource *cs)
 251 {
 252         struct timer_s *t = &timers[TID_CLOCKSOURCE];
 253
 254         return (cycles_t)timer32_read(t);
 255 }
 256
 257 static struct clocksource clocksource_davinci = {
 258         .name           = "timer0_1",
 259         .rating         = 300,
 260         .read           = read_cycles,
 261         .mask           = CLOCKSOURCE_MASK(32),
 262         .shift          = 24,
 263         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 264 };
 265
 266 /*
 267  * clockevent
 268  */
 269 static int davinci_set_next_event(unsigned long cycles,
 270                                   struct clock_event_device *evt)
 271 {
 272         struct timer_s *t = &timers[TID_CLOCKEVENT];
 273
 274         t->period = cycles;
 275         timer32_config(t);
 276         return 0;
 277 }
 278
 279 static void davinci_set_mode(enum clock_event_mode mode,
 280                              struct clock_event_device *evt)
 281 {
 282         struct timer_s *t = &timers[TID_CLOCKEVENT];
 283
 284         switch (mode) {
 285         case CLOCK_EVT_MODE_PERIODIC:
 286                 t->period = davinci_clock_tick_rate / (HZ);
 287                 t->opts = TIMER_OPTS_PERIODIC;
 288                 timer32_config(t);
 289                 break;
 290         case CLOCK_EVT_MODE_ONESHOT:
 291                 t->opts = TIMER_OPTS_ONESHOT;
 292                 break;
 293         case CLOCK_EVT_MODE_UNUSED:
 294         case CLOCK_EVT_MODE_SHUTDOWN:
 295                 t->opts = TIMER_OPTS_DISABLED;
 296                 break;
 297         case CLOCK_EVT_MODE_RESUME:
 298                 break;
 299         }
 300 }
 301
 302 static struct clock_event_device clockevent_davinci = {
 303         .name           = "timer0_0",
 304         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 305         .shift          = 32,
 306         .set_next_event = davinci_set_next_event,
 307         .set_mode       = davinci_set_mode,
 308 };
 309
 310
 311 static void __init davinci_timer_init(void)
 312 {
 313         struct clk *timer_clk;
 314
 315         static char err[] __initdata = KERN_ERR
 316                 "%s: can't register clocksource!\n";
 317
 318         /* init timer hw */
 319         timer_init();
 320
 321         timer_clk = clk_get(NULL, "timer0");
 322         BUG_ON(IS_ERR(timer_clk));
 323         clk_enable(timer_clk);
 324
 325         davinci_clock_tick_rate = clk_get_rate(timer_clk);
 326
 327         /* setup clocksource */
 328         clocksource_davinci.mult =
 329                 clocksource_khz2mult(davinci_clock_tick_rate/1000,
 330                                      clocksource_davinci.shift);
 331         if (clocksource_register(&clocksource_davinci))
 332                 printk(err, clocksource_davinci.name);
 333
 334         /* setup clockevent */
 335         clockevent_davinci.mult = div_sc(davinci_clock_tick_rate, NSEC_PER_SEC,
 336                                          clockevent_davinci.shift);
 337         clockevent_davinci.max_delta_ns =
 338                 clockevent_delta2ns(0xfffffffe, &clockevent_davinci);
 339         clockevent_davinci.min_delta_ns =
 340                 clockevent_delta2ns(1, &clockevent_davinci);
 341
 342         clockevent_davinci.cpumask = cpumask_of(0);
 343         clockevents_register_device(&clockevent_davinci);
 344 }
 345
 346 struct sys_timer davinci_timer = {
 347         .init   = davinci_timer_init,
 348 };
 349
 350
 351 /* reset board using watchdog timer */
 352 void davinci_watchdog_reset(void) {
 353         u32 tgcr, wdtcr;
 354         void __iomem *base = IO_ADDRESS(DAVINCI_WDOG_BASE);
 355         struct device dev;
 356         struct clk *wd_clk;
 357         char *name = "watchdog";
 358
 359         dev_set_name(&dev, name);
 360         wd_clk = clk_get(&dev, NULL);
 361         if (WARN_ON(IS_ERR(wd_clk)))
 362                 return;
 363         clk_enable(wd_clk);
 364
 365         /* disable, internal clock source */
 366         __raw_writel(0, base + TCR);
 367
 368         /* reset timer, set mode to 64-bit watchdog, and unreset */
 369         tgcr = 0;
 370         __raw_writel(tgcr, base + TCR);
 371         tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT;
 372         tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
 373                 (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
 374         __raw_writel(tgcr, base + TCR);
 375
 376         /* clear counter and period regs */
 377         __raw_writel(0, base + TIM12);
 378         __raw_writel(0, base + TIM34);
 379         __raw_writel(0, base + PRD12);
 380         __raw_writel(0, base + PRD34);
 381
 382         /* enable */
 383         wdtcr = __raw_readl(base + WDTCR);
 384         wdtcr |= WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT;
 385         __raw_writel(wdtcr, base + WDTCR);
 386
 387         /* put watchdog in pre-active state */
 388         wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
 389                 (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
 390         __raw_writel(wdtcr, base + WDTCR);
 391
 392         /* put watchdog in active state */
 393         wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) |
 394                 (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
 395         __raw_writel(wdtcr, base + WDTCR);
 396
 397         /* write an invalid value to the WDKEY field to trigger
 398          * a watchdog reset */
 399         wdtcr = 0x00004000;
 400         __raw_writel(wdtcr, base + WDTCR);
 401 }