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OMAP3 SRF: Fix crash on non-3430SDP platforms with DVFS/CPUFreq
[linux-ginger.git] / arch / arm / mach-omap2 / clock34xx.c
blobdd921833e6647b5e17026f02da03751a0272b7c6
1 /*
2 * OMAP3-specific clock framework functions
3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2009 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * Testing and integration fixes by Jouni Högander
9 *
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17 #undef DEBUG
18
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h>
22 #include <linux/list.h>
23 #include <linux/errno.h>
24 #include <linux/delay.h>
25 #include <linux/clk.h>
26 #include <linux/io.h>
27 #include <linux/limits.h>
28 #include <linux/bitops.h>
29 #include <linux/err.h>
30 #include <linux/cpufreq.h>
31
32 #include <plat/cpu.h>
33 #include <plat/clock.h>
34 #include <plat/sram.h>
35 #include <plat/omap-pm.h>
36
37 #include <asm/div64.h>
38 #include <asm/clkdev.h>
39
40 #include <plat/sdrc.h>
41 #include "clock.h"
42 #include "prm.h"
43 #include "prm-regbits-34xx.h"
44 #include "cm.h"
45 #include "cm-regbits-34xx.h"
46
47 static const struct clkops clkops_noncore_dpll_ops;
48
49 static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
50 void __iomem **idlest_reg,
51 u8 *idlest_bit);
52 static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
53 void __iomem **idlest_reg,
54 u8 *idlest_bit);
55 static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
56 void __iomem **idlest_reg,
57 u8 *idlest_bit);
58
59 static const struct clkops clkops_omap3430es2_ssi_wait = {
60 .enable = omap2_dflt_clk_enable,
61 .disable = omap2_dflt_clk_disable,
62 .find_idlest = omap3430es2_clk_ssi_find_idlest,
63 .find_companion = omap2_clk_dflt_find_companion,
64 };
65
66 static const struct clkops clkops_omap3430es2_hsotgusb_wait = {
67 .enable = omap2_dflt_clk_enable,
68 .disable = omap2_dflt_clk_disable,
69 .find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
70 .find_companion = omap2_clk_dflt_find_companion,
71 };
72
73 static const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
74 .enable = omap2_dflt_clk_enable,
75 .disable = omap2_dflt_clk_disable,
76 .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
77 .find_companion = omap2_clk_dflt_find_companion,
78 };
79
80 #include "clock34xx.h"
81
82 struct omap_clk {
83 u32 cpu;
84 struct clk_lookup lk;
85 };
86
87 #define CLK(dev, con, ck, cp) \
88 { \
89 .cpu = cp, \
90 .lk = { \
91 .dev_id = dev, \
92 .con_id = con, \
93 .clk = ck, \
94 }, \
95 }
96
97 #define CK_343X (1 << 0)
98 #define CK_3430ES1 (1 << 1)
99 #define CK_3430ES2 (1 << 2)
100
101 static struct omap_clk omap34xx_clks[] = {
102 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X),
103 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X),
104 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X),
105 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
106 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
107 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X),
108 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
109 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X),
110 CLK(NULL, "sys_ck", &sys_ck, CK_343X),
111 CLK(NULL, "sys_altclk", &sys_altclk, CK_343X),
112 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X),
113 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X),
114 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X),
115 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X),
116 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
117 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X),
118 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X),
119 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X),
120 CLK(NULL, "core_ck", &core_ck, CK_343X),
121 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X),
122 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X),
123 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
124 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X),
125 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
126 CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
127 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X),
128 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X),
129 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
130 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X),
131 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X),
132 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X),
133 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X),
134 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X),
135 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X),
136 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
137 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X),
138 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
139 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X),
140 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
141 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X),
142 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
143 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X),
144 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
145 CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
146 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2),
147 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2),
148 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X),
149 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X),
150 CLK(NULL, "corex2_fck", &corex2_fck, CK_343X),
151 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X),
152 CLK(NULL, "mpu_ck", &mpu_ck, CK_343X),
153 CLK(NULL, "arm_fck", &arm_fck, CK_343X),
154 CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
155 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X),
156 CLK(NULL, "iva2_ck", &iva2_ck, CK_343X),
157 CLK(NULL, "l3_ick", &l3_ick, CK_343X),
158 CLK(NULL, "l4_ick", &l4_ick, CK_343X),
159 CLK(NULL, "rm_ick", &rm_ick, CK_343X),
160 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
161 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
162 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
163 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
164 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
165 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2),
166 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2),
167 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
168 CLK(NULL, "modem_fck", &modem_fck, CK_343X),
169 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X),
170 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X),
171 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X),
172 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X),
173 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2),
174 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2),
175 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2),
176 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X),
177 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2),
178 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X),
179 CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
180 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X),
181 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X),
182 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X),
183 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X),
184 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X),
185 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X),
186 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X),
187 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X),
188 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X),
189 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X),
190 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X),
191 CLK(NULL, "uart2_fck", &uart2_fck, CK_343X),
192 CLK(NULL, "uart1_fck", &uart1_fck, CK_343X),
193 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
194 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X),
195 CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X),
196 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
197 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2),
198 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
199 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2),
200 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X),
201 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
202 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2),
203 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X),
204 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X),
205 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
206 CLK(NULL, "pka_ick", &pka_ick, CK_343X),
207 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X),
208 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2),
209 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2),
210 CLK(NULL, "icr_ick", &icr_ick, CK_343X),
211 CLK(NULL, "aes2_ick", &aes2_ick, CK_343X),
212 CLK(NULL, "sha12_ick", &sha12_ick, CK_343X),
213 CLK(NULL, "des2_ick", &des2_ick, CK_343X),
214 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X),
215 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X),
216 CLK(NULL, "mspro_ick", &mspro_ick, CK_343X),
217 CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X),
218 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X),
219 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X),
220 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X),
221 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X),
222 CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X),
223 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X),
224 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X),
225 CLK(NULL, "uart2_ick", &uart2_ick, CK_343X),
226 CLK(NULL, "uart1_ick", &uart1_ick, CK_343X),
227 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X),
228 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X),
229 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X),
230 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X),
231 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
232 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
233 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X),
234 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
235 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
236 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2),
237 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
238 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
239 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
240 CLK("omap_rng", "ick", &rng_ick, CK_343X),
241 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
242 CLK(NULL, "des1_ick", &des1_ick, CK_343X),
243 CLK("omapfb", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
244 CLK("omapfb", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2),
245 CLK("omapfb", "tv_fck", &dss_tv_fck, CK_343X),
246 CLK("omapfb", "video_fck", &dss_96m_fck, CK_343X),
247 CLK("omapfb", "dss2_fck", &dss2_alwon_fck, CK_343X),
248 CLK("omapfb", "ick", &dss_ick_3430es1, CK_3430ES1),
249 CLK("omapfb", "ick", &dss_ick_3430es2, CK_3430ES2),
250 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
251 CLK(NULL, "cam_ick", &cam_ick, CK_343X),
252 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
253 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
254 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
255 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2),
256 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
257 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X),
258 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X),
259 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X),
260 CLK("omap_wdt", "fck", &wdt2_fck, CK_343X),
261 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X),
262 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2),
263 CLK("omap_wdt", "ick", &wdt2_ick, CK_343X),
264 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X),
265 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X),
266 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
267 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X),
268 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X),
269 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X),
270 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X),
271 CLK(NULL, "uart3_fck", &uart3_fck, CK_343X),
272 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X),
273 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X),
274 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X),
275 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X),
276 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X),
277 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X),
278 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X),
279 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X),
280 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
281 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X),
282 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X),
283 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X),
284 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X),
285 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X),
286 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X),
287 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X),
288 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X),
289 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X),
290 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X),
291 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X),
292 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X),
293 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X),
294 CLK(NULL, "uart3_ick", &uart3_ick, CK_343X),
295 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X),
296 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X),
297 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X),
298 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X),
299 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X),
300 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X),
301 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X),
302 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X),
303 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X),
304 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X),
305 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X),
306 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X),
307 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X),
308 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X),
309 CLK(NULL, "emu_src_ck", &emu_src_ck, CK_343X),
310 CLK(NULL, "pclk_fck", &pclk_fck, CK_343X),
311 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X),
312 CLK(NULL, "atclk_fck", &atclk_fck, CK_343X),
313 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X),
314 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X),
315 CLK(NULL, "sr1_fck", &sr1_fck, CK_343X),
316 CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
317 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
318 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X),
319 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X),
320 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X),
321 };
322
323 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
324 #define DPLL_AUTOIDLE_DISABLE 0x0
325 #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
326
327 #define MAX_DPLL_WAIT_TRIES 1000000
328
329 #define MIN_SDRC_DLL_LOCK_FREQ 83000000
330
331 #define CYCLES_PER_MHZ 1000000
332
333 /* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
334 #define SDRC_MPURATE_SCALE 8
335
336 /* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
337 #define SDRC_MPURATE_BASE_SHIFT 9
338
339 /*
340 * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
341 * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
342 */
343 #define SDRC_MPURATE_LOOPS 96
344
345 /*
346 * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
347 * that are sourced by DPLL5, and both of these require this clock
348 * to be at 120 MHz for proper operation.
349 */
350 #define DPLL5_FREQ_FOR_USBHOST 120000000
351
352 /**
353 * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
354 * @clk: struct clk * being enabled
355 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
356 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
357 *
358 * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
359 * from the CM_{I,F}CLKEN bit. Pass back the correct info via
360 * @idlest_reg and @idlest_bit. No return value.
361 */
362 static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
363 void __iomem **idlest_reg,
364 u8 *idlest_bit)
365 {
366 u32 r;
367
368 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
369 *idlest_reg = (__force void __iomem *)r;
370 *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
371 }
372
373 /**
374 * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
375 * @clk: struct clk * being enabled
376 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
377 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
378 *
379 * Some OMAP modules on OMAP3 ES2+ chips have both initiator and
380 * target IDLEST bits. For our purposes, we are concerned with the
381 * target IDLEST bits, which exist at a different bit position than
382 * the *CLKEN bit position for these modules (DSS and USBHOST) (The
383 * default find_idlest code assumes that they are at the same
384 * position.) No return value.
385 */
386 static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
387 void __iomem **idlest_reg,
388 u8 *idlest_bit)
389 {
390 u32 r;
391
392 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
393 *idlest_reg = (__force void __iomem *)r;
394 /* USBHOST_IDLE has same shift */
395 *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
396 }
397
398 /**
399 * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
400 * @clk: struct clk * being enabled
401 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
402 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
403 *
404 * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
405 * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via
406 * @idlest_reg and @idlest_bit. No return value.
407 */
408 static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
409 void __iomem **idlest_reg,
410 u8 *idlest_bit)
411 {
412 u32 r;
413
414 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
415 *idlest_reg = (__force void __iomem *)r;
416 *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
417 }
418
419 /**
420 * omap3_dpll_recalc - recalculate DPLL rate
421 * @clk: DPLL struct clk
422 *
423 * Recalculate and propagate the DPLL rate.
424 */
425 static unsigned long omap3_dpll_recalc(struct clk *clk)
426 {
427 return omap2_get_dpll_rate(clk);
428 }
429
430 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
431 static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
432 {
433 const struct dpll_data *dd;
434 u32 v;
435
436 dd = clk->dpll_data;
437
438 v = __raw_readl(dd->control_reg);
439 v &= ~dd->enable_mask;
440 v |= clken_bits << __ffs(dd->enable_mask);
441 __raw_writel(v, dd->control_reg);
442 }
443
444 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
445 static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
446 {
447 const struct dpll_data *dd;
448 int i = 0;
449 int ret = -EINVAL;
450
451 dd = clk->dpll_data;
452
453 state <<= __ffs(dd->idlest_mask);
454
455 while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
456 i < MAX_DPLL_WAIT_TRIES) {
457 i++;
458 udelay(1);
459 }
460
461 if (i == MAX_DPLL_WAIT_TRIES) {
462 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
463 clk->name, (state) ? "locked" : "bypassed");
464 } else {
465 pr_debug("clock: %s transition to '%s' in %d loops\n",
466 clk->name, (state) ? "locked" : "bypassed", i);
467
468 ret = 0;
469 }
470
471 return ret;
472 }
473
474 /* From 3430 TRM ES2 4.7.6.2 */
475 static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
476 {
477 unsigned long fint;
478 u16 f = 0;
479
480 fint = clk->dpll_data->clk_ref->rate / (n + 1);
481
482 pr_debug("clock: fint is %lu\n", fint);
483
484 if (fint >= 750000 && fint <= 1000000)
485 f = 0x3;
486 else if (fint > 1000000 && fint <= 1250000)
487 f = 0x4;
488 else if (fint > 1250000 && fint <= 1500000)
489 f = 0x5;
490 else if (fint > 1500000 && fint <= 1750000)
491 f = 0x6;
492 else if (fint > 1750000 && fint <= 2100000)
493 f = 0x7;
494 else if (fint > 7500000 && fint <= 10000000)
495 f = 0xB;
496 else if (fint > 10000000 && fint <= 12500000)
497 f = 0xC;
498 else if (fint > 12500000 && fint <= 15000000)
499 f = 0xD;
500 else if (fint > 15000000 && fint <= 17500000)
501 f = 0xE;
502 else if (fint > 17500000 && fint <= 21000000)
503 f = 0xF;
504 else
505 pr_debug("clock: unknown freqsel setting for %d\n", n);
506
507 return f;
508 }
509
510 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
511
512 /*
513 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
514 * @clk: pointer to a DPLL struct clk
515 *
516 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
517 * readiness before returning. Will save and restore the DPLL's
518 * autoidle state across the enable, per the CDP code. If the DPLL
519 * locked successfully, return 0; if the DPLL did not lock in the time
520 * allotted, or DPLL3 was passed in, return -EINVAL.
521 */
522 static int _omap3_noncore_dpll_lock(struct clk *clk)
523 {
524 u8 ai;
525 int r;
526
527 if (clk == &dpll3_ck)
528 return -EINVAL;
529
530 pr_debug("clock: locking DPLL %s\n", clk->name);
531
532 ai = omap3_dpll_autoidle_read(clk);
533
534 omap3_dpll_deny_idle(clk);
535
536 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
537
538 r = _omap3_wait_dpll_status(clk, 1);
539
540 if (ai)
541 omap3_dpll_allow_idle(clk);
542
543 return r;
544 }
545
546 /*
547 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
548 * @clk: pointer to a DPLL struct clk
549 *
550 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
551 * bypass mode, the DPLL's rate is set equal to its parent clock's
552 * rate. Waits for the DPLL to report readiness before returning.
553 * Will save and restore the DPLL's autoidle state across the enable,
554 * per the CDP code. If the DPLL entered bypass mode successfully,
555 * return 0; if the DPLL did not enter bypass in the time allotted, or
556 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
557 * return -EINVAL.
558 */
559 static int _omap3_noncore_dpll_bypass(struct clk *clk)
560 {
561 int r;
562 u8 ai;
563
564 if (clk == &dpll3_ck)
565 return -EINVAL;
566
567 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
568 return -EINVAL;
569
570 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
571 clk->name);
572
573 ai = omap3_dpll_autoidle_read(clk);
574
575 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
576
577 r = _omap3_wait_dpll_status(clk, 0);
578
579 if (ai)
580 omap3_dpll_allow_idle(clk);
581 else
582 omap3_dpll_deny_idle(clk);
583
584 return r;
585 }
586
587 /*
588 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
589 * @clk: pointer to a DPLL struct clk
590 *
591 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
592 * restore the DPLL's autoidle state across the stop, per the CDP
593 * code. If DPLL3 was passed in, or the DPLL does not support
594 * low-power stop, return -EINVAL; otherwise, return 0.
595 */
596 static int _omap3_noncore_dpll_stop(struct clk *clk)
597 {
598 u8 ai;
599
600 if (clk == &dpll3_ck)
601 return -EINVAL;
602
603 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
604 return -EINVAL;
605
606 pr_debug("clock: stopping DPLL %s\n", clk->name);
607
608 ai = omap3_dpll_autoidle_read(clk);
609
610 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
611
612 if (ai)
613 omap3_dpll_allow_idle(clk);
614 else
615 omap3_dpll_deny_idle(clk);
616
617 return 0;
618 }
619
620 /**
621 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
622 * @clk: pointer to a DPLL struct clk
623 *
624 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
625 * The choice of modes depends on the DPLL's programmed rate: if it is
626 * the same as the DPLL's parent clock, it will enter bypass;
627 * otherwise, it will enter lock. This code will wait for the DPLL to
628 * indicate readiness before returning, unless the DPLL takes too long
629 * to enter the target state. Intended to be used as the struct clk's
630 * enable function. If DPLL3 was passed in, or the DPLL does not
631 * support low-power stop, or if the DPLL took too long to enter
632 * bypass or lock, return -EINVAL; otherwise, return 0.
633 */
634 static int omap3_noncore_dpll_enable(struct clk *clk)
635 {
636 int r;
637 struct dpll_data *dd;
638
639 if (clk == &dpll3_ck)
640 return -EINVAL;
641
642 dd = clk->dpll_data;
643 if (!dd)
644 return -EINVAL;
645
646 if (clk->rate == dd->clk_bypass->rate) {
647 WARN_ON(clk->parent != dd->clk_bypass);
648 r = _omap3_noncore_dpll_bypass(clk);
649 } else {
650 WARN_ON(clk->parent != dd->clk_ref);
651 r = _omap3_noncore_dpll_lock(clk);
652 }
653 /* FIXME: this is dubious - if clk->rate has changed, what about propagating? */
654 if (!r)
655 clk->rate = omap2_get_dpll_rate(clk);
656
657 return r;
658 }
659
660 /**
661 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
662 * @clk: pointer to a DPLL struct clk
663 *
664 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
665 * The choice of modes depends on the DPLL's programmed rate: if it is
666 * the same as the DPLL's parent clock, it will enter bypass;
667 * otherwise, it will enter lock. This code will wait for the DPLL to
668 * indicate readiness before returning, unless the DPLL takes too long
669 * to enter the target state. Intended to be used as the struct clk's
670 * enable function. If DPLL3 was passed in, or the DPLL does not
671 * support low-power stop, or if the DPLL took too long to enter
672 * bypass or lock, return -EINVAL; otherwise, return 0.
673 */
674 static void omap3_noncore_dpll_disable(struct clk *clk)
675 {
676 if (clk == &dpll3_ck)
677 return;
678
679 _omap3_noncore_dpll_stop(clk);
680 }
681
682
683 /* Non-CORE DPLL rate set code */
684
685 /*
686 * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
687 * @clk: struct clk * of DPLL to set
688 * @m: DPLL multiplier to set
689 * @n: DPLL divider to set
690 * @freqsel: FREQSEL value to set
691 *
692 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
693 * lock.. Returns -EINVAL upon error, or 0 upon success.
694 */
695 static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
696 {
697 struct dpll_data *dd = clk->dpll_data;
698 u32 v;
699
700 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
701 _omap3_noncore_dpll_bypass(clk);
702
703 /* Set jitter correction */
704 v = __raw_readl(dd->control_reg);
705 v &= ~dd->freqsel_mask;
706 v |= freqsel << __ffs(dd->freqsel_mask);
707 __raw_writel(v, dd->control_reg);
708
709 /* Set DPLL multiplier, divider */
710 v = __raw_readl(dd->mult_div1_reg);
711 v &= ~(dd->mult_mask | dd->div1_mask);
712 v |= m << __ffs(dd->mult_mask);
713 v |= (n - 1) << __ffs(dd->div1_mask);
714 __raw_writel(v, dd->mult_div1_reg);
715
716 /* We let the clock framework set the other output dividers later */
717
718 /* REVISIT: Set ramp-up delay? */
719
720 _omap3_noncore_dpll_lock(clk);
721
722 return 0;
723 }
724
725 /**
726 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
727 * @clk: struct clk * of DPLL to set
728 * @rate: rounded target rate
729 *
730 * Set the DPLL CLKOUT to the target rate. If the DPLL can enter
731 * low-power bypass, and the target rate is the bypass source clock
732 * rate, then configure the DPLL for bypass. Otherwise, round the
733 * target rate if it hasn't been done already, then program and lock
734 * the DPLL. Returns -EINVAL upon error, or 0 upon success.
735 */
736 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
737 {
738 struct clk *new_parent = NULL;
739 u16 freqsel;
740 struct dpll_data *dd;
741 int ret;
742
743 if (!clk || !rate)
744 return -EINVAL;
745
746 dd = clk->dpll_data;
747 if (!dd)
748 return -EINVAL;
749
750 if (rate == omap2_get_dpll_rate(clk))
751 return 0;
752
753 /*
754 * Ensure both the bypass and ref clocks are enabled prior to
755 * doing anything; we need the bypass clock running to reprogram
756 * the DPLL.
757 */
758 omap2_clk_enable(dd->clk_bypass);
759 omap2_clk_enable(dd->clk_ref);
760
761 if (dd->clk_bypass->rate == rate &&
762 (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
763 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
764
765 ret = _omap3_noncore_dpll_bypass(clk);
766 if (!ret)
767 new_parent = dd->clk_bypass;
768 } else {
769 if (dd->last_rounded_rate != rate)
770 omap2_dpll_round_rate(clk, rate);
771
772 if (dd->last_rounded_rate == 0)
773 return -EINVAL;
774
775 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
776 if (!freqsel)
777 WARN_ON(1);
778
779 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
780 clk->name, rate);
781
782 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
783 dd->last_rounded_n, freqsel);
784 if (!ret)
785 new_parent = dd->clk_ref;
786 }
787 if (!ret) {
788 /*
789 * Switch the parent clock in the heirarchy, and make sure
790 * that the new parent's usecount is correct. Note: we
791 * enable the new parent before disabling the old to avoid
792 * any unnecessary hardware disable->enable transitions.
793 */
794 if (clk->usecount) {
795 omap2_clk_enable(new_parent);
796 omap2_clk_disable(clk->parent);
797 }
798 clk_reparent(clk, new_parent);
799 clk->rate = rate;
800 }
801 omap2_clk_disable(dd->clk_ref);
802 omap2_clk_disable(dd->clk_bypass);
803
804 return 0;
805 }
806
807 static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
808 {
809 /*
810 * According to the 12-5 CDP code from TI, "Limitation 2.5"
811 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
812 * on DPLL4.
813 */
814 if (omap_rev() == OMAP3430_REV_ES1_0) {
815 printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
816 "silicon 'Limitation 2.5' on 3430ES1.\n");
817 return -EINVAL;
818 }
819 return omap3_noncore_dpll_set_rate(clk, rate);
820 }
821
822
823 /*
824 * CORE DPLL (DPLL3) rate programming functions
825 *
826 * These call into SRAM code to do the actual CM writes, since the SDRAM
827 * is clocked from DPLL3.
828 */
829
830 /**
831 * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
832 * @clk: struct clk * of DPLL to set
833 * @rate: rounded target rate
834 *
835 * Program the DPLL M2 divider with the rounded target rate. Returns
836 * -EINVAL upon error, or 0 upon success.
837 */
838 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
839 {
840 u32 new_div = 0;
841 u32 unlock_dll = 0;
842 u32 c;
843 unsigned long validrate, sdrcrate, mpurate;
844 struct omap_sdrc_params *sdrc_cs0;
845 struct omap_sdrc_params *sdrc_cs1;
846 int ret;
847
848 if (!clk || !rate)
849 return -EINVAL;
850
851 if (clk != &dpll3_m2_ck)
852 return -EINVAL;
853
854 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
855 if (validrate != rate)
856 return -EINVAL;
857
858 sdrcrate = sdrc_ick.rate;
859 if (rate > clk->rate)
860 sdrcrate <<= ((rate / clk->rate) >> 1);
861 else
862 sdrcrate >>= ((clk->rate / rate) >> 1);
863
864 ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
865 if (ret)
866 return -EINVAL;
867
868 if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
869 pr_debug("clock: will unlock SDRC DLL\n");
870 unlock_dll = 1;
871 }
872
873 /*
874 * XXX This only needs to be done when the CPU frequency changes
875 */
876 mpurate = arm_fck.rate / CYCLES_PER_MHZ;
877 c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
878 c += 1; /* for safety */
879 c *= SDRC_MPURATE_LOOPS;
880 c >>= SDRC_MPURATE_SCALE;
881 if (c == 0)
882 c = 1;
883
884 pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
885 validrate);
886 pr_debug("clock: SDRC CS0 timing params used:"
887 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
888 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
889 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
890 if (sdrc_cs1)
891 pr_debug("clock: SDRC CS1 timing params used: "
892 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
893 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
894 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
895
896 if (sdrc_cs1)
897 omap3_configure_core_dpll(
898 new_div, unlock_dll, c, rate > clk->rate,
899 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
900 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
901 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
902 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
903 else
904 omap3_configure_core_dpll(
905 new_div, unlock_dll, c, rate > clk->rate,
906 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
907 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
908 0, 0, 0, 0);
909
910 return 0;
911 }
912
913
914 static const struct clkops clkops_noncore_dpll_ops = {
915 .enable = &omap3_noncore_dpll_enable,
916 .disable = &omap3_noncore_dpll_disable,
917 };
918
919 /* DPLL autoidle read/set code */
920
921
922 /**
923 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
924 * @clk: struct clk * of the DPLL to read
925 *
926 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
927 * -EINVAL if passed a null pointer or if the struct clk does not
928 * appear to refer to a DPLL.
929 */
930 static u32 omap3_dpll_autoidle_read(struct clk *clk)
931 {
932 const struct dpll_data *dd;
933 u32 v;
934
935 if (!clk || !clk->dpll_data)
936 return -EINVAL;
937
938 dd = clk->dpll_data;
939
940 v = __raw_readl(dd->autoidle_reg);
941 v &= dd->autoidle_mask;
942 v >>= __ffs(dd->autoidle_mask);
943
944 return v;
945 }
946
947 /**
948 * omap3_dpll_allow_idle - enable DPLL autoidle bits
949 * @clk: struct clk * of the DPLL to operate on
950 *
951 * Enable DPLL automatic idle control. This automatic idle mode
952 * switching takes effect only when the DPLL is locked, at least on
953 * OMAP3430. The DPLL will enter low-power stop when its downstream
954 * clocks are gated. No return value.
955 */
956 static void omap3_dpll_allow_idle(struct clk *clk)
957 {
958 const struct dpll_data *dd;
959 u32 v;
960
961 if (!clk || !clk->dpll_data)
962 return;
963
964 dd = clk->dpll_data;
965
966 /*
967 * REVISIT: CORE DPLL can optionally enter low-power bypass
968 * by writing 0x5 instead of 0x1. Add some mechanism to
969 * optionally enter this mode.
970 */
971 v = __raw_readl(dd->autoidle_reg);
972 v &= ~dd->autoidle_mask;
973 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
974 __raw_writel(v, dd->autoidle_reg);
975 }
976
977 /**
978 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
979 * @clk: struct clk * of the DPLL to operate on
980 *
981 * Disable DPLL automatic idle control. No return value.
982 */
983 static void omap3_dpll_deny_idle(struct clk *clk)
984 {
985 const struct dpll_data *dd;
986 u32 v;
987
988 if (!clk || !clk->dpll_data)
989 return;
990
991 dd = clk->dpll_data;
992
993 v = __raw_readl(dd->autoidle_reg);
994 v &= ~dd->autoidle_mask;
995 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
996 __raw_writel(v, dd->autoidle_reg);
997 }
998
999 /* Clock control for DPLL outputs */
1000
1001 /**
1002 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
1003 * @clk: DPLL output struct clk
1004 *
1005 * Using parent clock DPLL data, look up DPLL state. If locked, set our
1006 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
1007 */
1008 static unsigned long omap3_clkoutx2_recalc(struct clk *clk)
1009 {
1010 const struct dpll_data *dd;
1011 unsigned long rate;
1012 u32 v;
1013 struct clk *pclk;
1014
1015 /* Walk up the parents of clk, looking for a DPLL */
1016 pclk = clk->parent;
1017 while (pclk && !pclk->dpll_data)
1018 pclk = pclk->parent;
1019
1020 /* clk does not have a DPLL as a parent? */
1021 WARN_ON(!pclk);
1022
1023 dd = pclk->dpll_data;
1024
1025 WARN_ON(!dd->enable_mask);
1026
1027 v = __raw_readl(dd->control_reg) & dd->enable_mask;
1028 v >>= __ffs(dd->enable_mask);
1029 if (v != OMAP3XXX_EN_DPLL_LOCKED)
1030 rate = clk->parent->rate;
1031 else
1032 rate = clk->parent->rate * 2;
1033 return rate;
1034 }
1035
1036 /* Common clock code */
1037
1038 /*
1039 * As it is structured now, this will prevent an OMAP2/3 multiboot
1040 * kernel from compiling. This will need further attention.
1041 */
1042 #if defined(CONFIG_ARCH_OMAP3)
1043
1044 #ifdef CONFIG_CPU_FREQ
1045 static struct cpufreq_frequency_table freq_table[MAX_VDD1_OPP+1];
1046
1047 void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
1048 {
1049 struct omap_opp *prcm;
1050 int i = 0;
1051
1052 if (!mpu_opps)
1053 return;
1054
1055 /* Avoid registering the 120% Overdrive with CPUFreq */
1056 prcm = mpu_opps + MAX_VDD1_OPP - 1;
1057 for (; prcm->rate; prcm--) {
1058 freq_table[i].index = i;
1059 freq_table[i].frequency = prcm->rate / 1000;
1060 i++;
1061 }
1062
1063 if (i == 0) {
1064 printk(KERN_WARNING "%s: failed to initialize frequency \
1065 table\n",
1066 __func__);
1067 return;
1068 }
1069
1070 freq_table[i].index = i;
1071 freq_table[i].frequency = CPUFREQ_TABLE_END;
1072
1073 *table = &freq_table[0];
1074 }
1075 #endif
1076
1077 static struct clk_functions omap2_clk_functions = {
1078 .clk_enable = omap2_clk_enable,
1079 .clk_disable = omap2_clk_disable,
1080 .clk_round_rate = omap2_clk_round_rate,
1081 .clk_set_rate = omap2_clk_set_rate,
1082 .clk_set_parent = omap2_clk_set_parent,
1083 .clk_disable_unused = omap2_clk_disable_unused,
1084 #ifdef CONFIG_CPU_FREQ
1085 .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
1086 #endif
1087 };
1088
1089 /*
1090 * Set clocks for bypass mode for reboot to work.
1091 */
1092 void omap2_clk_prepare_for_reboot(void)
1093 {
1094 /* REVISIT: Not ready for 343x */
1095 #if 0
1096 u32 rate;
1097
1098 if (vclk == NULL || sclk == NULL)
1099 return;
1100
1101 rate = clk_get_rate(sclk);
1102 clk_set_rate(vclk, rate);
1103 #endif
1104 }
1105
1106 static void omap3_clk_lock_dpll5(void)
1107 {
1108 struct clk *dpll5_clk;
1109 struct clk *dpll5_m2_clk;
1110
1111 dpll5_clk = clk_get(NULL, "dpll5_ck");
1112 clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
1113 clk_enable(dpll5_clk);
1114
1115 /* Enable autoidle to allow it to enter low power bypass */
1116 omap3_dpll_allow_idle(dpll5_clk);
1117
1118 /* Program dpll5_m2_clk divider for no division */
1119 dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
1120 clk_enable(dpll5_m2_clk);
1121 clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
1122
1123 clk_disable(dpll5_m2_clk);
1124 clk_disable(dpll5_clk);
1125 return;
1126 }
1127
1128 /* REVISIT: Move this init stuff out into clock.c */
1129
1130 /*
1131 * Switch the MPU rate if specified on cmdline.
1132 * We cannot do this early until cmdline is parsed.
1133 */
1134 static int __init omap2_clk_arch_init(void)
1135 {
1136 if (!mpurate)
1137 return -EINVAL;
1138
1139 /* REVISIT: not yet ready for 343x */
1140 if (clk_set_rate(&dpll1_ck, mpurate))
1141 printk(KERN_ERR "*** Unable to set MPU rate\n");
1142
1143 recalculate_root_clocks();
1144
1145 printk(KERN_INFO "Switched to new clocking rate (Crystal/Core/MPU): "
1146 "%ld.%01ld/%ld/%ld MHz\n",
1147 (osc_sys_ck.rate / 1000000), ((osc_sys_ck.rate / 100000) % 10),
1148 (core_ck.rate / 1000000), (arm_fck.rate / 1000000)) ;
1149
1150 calibrate_delay();
1151
1152 return 0;
1153 }
1154 arch_initcall(omap2_clk_arch_init);
1155
1156 int __init omap2_clk_init(void)
1157 {
1158 /* struct prcm_config *prcm; */
1159 struct omap_clk *c;
1160 /* u32 clkrate; */
1161 u32 cpu_clkflg;
1162
1163 if (cpu_is_omap34xx()) {
1164 cpu_mask = RATE_IN_343X;
1165 cpu_clkflg = CK_343X;
1166
1167 /*
1168 * Update this if there are further clock changes between ES2
1169 * and production parts
1170 */
1171 if (omap_rev() == OMAP3430_REV_ES1_0) {
1172 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
1173 cpu_clkflg |= CK_3430ES1;
1174 } else {
1175 cpu_mask |= RATE_IN_3430ES2;
1176 cpu_clkflg |= CK_3430ES2;
1177 }
1178 }
1179
1180 clk_init(&omap2_clk_functions);
1181
1182 for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
1183 clk_preinit(c->lk.clk);
1184
1185 for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
1186 if (c->cpu & cpu_clkflg) {
1187 clkdev_add(&c->lk);
1188 clk_register(c->lk.clk);
1189 omap2_init_clk_clkdm(c->lk.clk);
1190 }
1191
1192 /* REVISIT: Not yet ready for OMAP3 */
1193 #if 0
1194 /* Check the MPU rate set by bootloader */
1195 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
1196 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
1197 if (!(prcm->flags & cpu_mask))
1198 continue;
1199 if (prcm->xtal_speed != sys_ck.rate)
1200 continue;
1201 if (prcm->dpll_speed <= clkrate)
1202 break;
1203 }
1204 curr_prcm_set = prcm;
1205 #endif
1206
1207 recalculate_root_clocks();
1208
1209 printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
1210 "%ld.%01ld/%ld/%ld MHz\n",
1211 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
1212 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
1213
1214 /*
1215 * Only enable those clocks we will need, let the drivers
1216 * enable other clocks as necessary
1217 */
1218 clk_enable_init_clocks();
1219
1220 /*
1221 * Lock DPLL5 and put it in autoidle.
1222 */
1223 if (omap_rev() >= OMAP3430_REV_ES2_0)
1224 omap3_clk_lock_dpll5();
1225
1226 /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
1227 /* REVISIT: not yet ready for 343x */
1228 #if 0
1229 vclk = clk_get(NULL, "virt_prcm_set");
1230 sclk = clk_get(NULL, "sys_ck");
1231 #endif
1232 return 0;
1233 }
1234
1235 unsigned long get_freq(struct omap_opp *opp_freq_table,
1236 unsigned short opp)
1237 {
1238 struct omap_opp *prcm_config;
1239 prcm_config = opp_freq_table;
1240
1241 for (; prcm_config->opp_id; prcm_config--)
1242 if (prcm_config->opp_id == opp)
1243 return prcm_config->rate;
1244 return 0;
1245 }
1246
1247 unsigned short get_opp(struct omap_opp *opp_freq_table,
1248 unsigned long freq)
1249 {
1250 struct omap_opp *prcm_config;
1251 prcm_config = opp_freq_table;
1252
1253 if (prcm_config->rate <= freq)
1254 return prcm_config->opp_id; /* Return the Highest OPP */
1255 for (; prcm_config->rate; prcm_config--)
1256 if (prcm_config->rate < freq)
1257 return (prcm_config+1)->opp_id;
1258 else if (prcm_config->rate == freq)
1259 return prcm_config->opp_id;
1260 /* Return the least OPP */
1261 return (prcm_config+1)->opp_id;
1262 }
1263
1264 static void omap3_table_recalc(struct clk *clk)
1265 {
1266 if ((clk != &virt_vdd1_prcm_set) && (clk != &virt_vdd2_prcm_set))
1267 return;
1268
1269 if ((curr_vdd1_prcm_set) && (clk == &virt_vdd1_prcm_set))
1270 clk->rate = curr_vdd1_prcm_set->rate;
1271 else if ((curr_vdd2_prcm_set) && (clk == &virt_vdd2_prcm_set))
1272 clk->rate = curr_vdd2_prcm_set->rate;
1273 pr_debug("CLK RATE:%lu\n", clk->rate);
1274 }
1275
1276 static long omap3_round_to_table_rate(struct clk *clk, unsigned long rate)
1277 {
1278 struct omap_opp *ptr;
1279 long highest_rate;
1280
1281 if ((clk != &virt_vdd1_prcm_set) && (clk != &virt_vdd2_prcm_set))
1282 return -EINVAL;
1283
1284 if (!mpu_opps || !dsp_opps || !l3_opps)
1285 return -EINVAL;
1286
1287 highest_rate = -EINVAL;
1288
1289 if (clk == &virt_vdd1_prcm_set)
1290 ptr = mpu_opps + MAX_VDD1_OPP;
1291 else
1292 ptr = dsp_opps + MAX_VDD2_OPP;
1293
1294 for (; ptr->rate; ptr--) {
1295 highest_rate = ptr->rate;
1296 pr_debug("Highest speed : %lu, rate: %lu\n", highest_rate,
1297 rate);
1298 if (ptr->rate <= rate)
1299 break;
1300 }
1301 return highest_rate;
1302 }
1303
1304 static int omap3_select_table_rate(struct clk *clk, unsigned long rate)
1305 {
1306 struct omap_opp *prcm_vdd = NULL;
1307 unsigned long found_speed = 0, curr_mpu_speed;
1308 int index = 0;
1309
1310 if ((clk != &virt_vdd1_prcm_set) && (clk != &virt_vdd2_prcm_set))
1311 return -EINVAL;
1312
1313 if (!mpu_opps || !dsp_opps || !l3_opps)
1314 return -EINVAL;
1315
1316 if (clk == &virt_vdd1_prcm_set) {
1317 prcm_vdd = mpu_opps + MAX_VDD1_OPP;
1318 index = MAX_VDD1_OPP;
1319 } else if (clk == &virt_vdd2_prcm_set) {
1320 prcm_vdd = l3_opps + MAX_VDD2_OPP;
1321 index = MAX_VDD2_OPP;
1322 }
1323
1324 for (; prcm_vdd && prcm_vdd->rate; prcm_vdd--, index--) {
1325 if (prcm_vdd->rate <= rate) {
1326 found_speed = prcm_vdd->rate;
1327 pr_debug("Found speed = %lu\n", found_speed);
1328 break;
1329 }
1330 }
1331
1332 if (!found_speed) {
1333 printk(KERN_INFO "Could not set table rate to %luMHz\n",
1334 rate / 1000000);
1335 return -EINVAL;
1336 }
1337
1338
1339 if (clk == &virt_vdd1_prcm_set) {
1340 curr_mpu_speed = curr_vdd1_prcm_set->rate;
1341 clk_set_rate(dpll1_clk, prcm_vdd->rate);
1342 clk_set_rate(dpll2_clk, dsp_opps[index].rate);
1343 curr_vdd1_prcm_set = prcm_vdd;
1344 omap2_clksel_recalc(&mpu_ck);
1345 propagate_rate(&mpu_ck);
1346 omap2_clksel_recalc(&iva2_ck);
1347 propagate_rate(&iva2_ck);
1348 #ifndef CONFIG_CPU_FREQ
1349 /*Update loops_per_jiffy if processor speed is being changed*/
1350 loops_per_jiffy = compute_lpj(loops_per_jiffy,
1351 curr_mpu_speed/1000, found_speed/1000);
1352 #endif
1353 } else {
1354 clk_set_rate(dpll3_clk, prcm_vdd->rate);
1355 curr_vdd2_prcm_set = prcm_vdd;
1356 omap2_clksel_recalc(&core_ck);
1357 propagate_rate(&core_ck);
1358 }
1359 return 0;
1360 }
1361
1362 #endif /* CONFIG_ARCH_OMAP3 */
Linux for Ginger Game Console