2 * linux/arch/arm/mach-omap2/io.c
4 * OMAP2 I/O mapping code
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
24 #include <linux/clk.h>
28 #include <asm/mach/map.h>
31 #include <plat/omapfb.h>
32 #include <plat/sram.h>
33 #include <plat/sdrc.h>
34 #include <plat/gpmc.h>
35 #include <plat/serial.h>
37 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdev is ready */
40 #include <plat/omap-pm.h>
41 #include <plat/powerdomain.h>
42 #include "powerdomains.h"
44 #include <plat/clockdomain.h>
45 #include "clockdomains.h"
47 #include <plat/omap_hwmod.h>
48 #include "omap_hwmod_2420.h"
49 #include "omap_hwmod_2430.h"
50 #include "omap_hwmod_34xx.h"
53 * The machine specific code may provide the extra mapping besides the
54 * default mapping provided here.
57 #ifdef CONFIG_ARCH_OMAP24XX
58 static struct map_desc omap24xx_io_desc
[] __initdata
= {
60 .virtual = L3_24XX_VIRT
,
61 .pfn
= __phys_to_pfn(L3_24XX_PHYS
),
62 .length
= L3_24XX_SIZE
,
66 .virtual = L4_24XX_VIRT
,
67 .pfn
= __phys_to_pfn(L4_24XX_PHYS
),
68 .length
= L4_24XX_SIZE
,
73 #ifdef CONFIG_ARCH_OMAP2420
74 static struct map_desc omap242x_io_desc
[] __initdata
= {
76 .virtual = DSP_MEM_24XX_VIRT
,
77 .pfn
= __phys_to_pfn(DSP_MEM_24XX_PHYS
),
78 .length
= DSP_MEM_24XX_SIZE
,
82 .virtual = DSP_IPI_24XX_VIRT
,
83 .pfn
= __phys_to_pfn(DSP_IPI_24XX_PHYS
),
84 .length
= DSP_IPI_24XX_SIZE
,
88 .virtual = DSP_MMU_24XX_VIRT
,
89 .pfn
= __phys_to_pfn(DSP_MMU_24XX_PHYS
),
90 .length
= DSP_MMU_24XX_SIZE
,
97 #ifdef CONFIG_ARCH_OMAP2430
98 static struct map_desc omap243x_io_desc
[] __initdata
= {
100 .virtual = L4_WK_243X_VIRT
,
101 .pfn
= __phys_to_pfn(L4_WK_243X_PHYS
),
102 .length
= L4_WK_243X_SIZE
,
106 .virtual = OMAP243X_GPMC_VIRT
,
107 .pfn
= __phys_to_pfn(OMAP243X_GPMC_PHYS
),
108 .length
= OMAP243X_GPMC_SIZE
,
112 .virtual = OMAP243X_SDRC_VIRT
,
113 .pfn
= __phys_to_pfn(OMAP243X_SDRC_PHYS
),
114 .length
= OMAP243X_SDRC_SIZE
,
118 .virtual = OMAP243X_SMS_VIRT
,
119 .pfn
= __phys_to_pfn(OMAP243X_SMS_PHYS
),
120 .length
= OMAP243X_SMS_SIZE
,
127 #ifdef CONFIG_ARCH_OMAP34XX
128 static struct map_desc omap34xx_io_desc
[] __initdata
= {
130 .virtual = L3_34XX_VIRT
,
131 .pfn
= __phys_to_pfn(L3_34XX_PHYS
),
132 .length
= L3_34XX_SIZE
,
136 .virtual = L4_34XX_VIRT
,
137 .pfn
= __phys_to_pfn(L4_34XX_PHYS
),
138 .length
= L4_34XX_SIZE
,
142 .virtual = L4_WK_34XX_VIRT
,
143 .pfn
= __phys_to_pfn(L4_WK_34XX_PHYS
),
144 .length
= L4_WK_34XX_SIZE
,
148 .virtual = OMAP34XX_GPMC_VIRT
,
149 .pfn
= __phys_to_pfn(OMAP34XX_GPMC_PHYS
),
150 .length
= OMAP34XX_GPMC_SIZE
,
154 .virtual = OMAP343X_SMS_VIRT
,
155 .pfn
= __phys_to_pfn(OMAP343X_SMS_PHYS
),
156 .length
= OMAP343X_SMS_SIZE
,
160 .virtual = OMAP343X_SDRC_VIRT
,
161 .pfn
= __phys_to_pfn(OMAP343X_SDRC_PHYS
),
162 .length
= OMAP343X_SDRC_SIZE
,
166 .virtual = L4_PER_34XX_VIRT
,
167 .pfn
= __phys_to_pfn(L4_PER_34XX_PHYS
),
168 .length
= L4_PER_34XX_SIZE
,
172 .virtual = L4_EMU_34XX_VIRT
,
173 .pfn
= __phys_to_pfn(L4_EMU_34XX_PHYS
),
174 .length
= L4_EMU_34XX_SIZE
,
179 #ifdef CONFIG_ARCH_OMAP4
180 static struct map_desc omap44xx_io_desc
[] __initdata
= {
182 .virtual = L3_44XX_VIRT
,
183 .pfn
= __phys_to_pfn(L3_44XX_PHYS
),
184 .length
= L3_44XX_SIZE
,
188 .virtual = L4_44XX_VIRT
,
189 .pfn
= __phys_to_pfn(L4_44XX_PHYS
),
190 .length
= L4_44XX_SIZE
,
194 .virtual = L4_WK_44XX_VIRT
,
195 .pfn
= __phys_to_pfn(L4_WK_44XX_PHYS
),
196 .length
= L4_WK_44XX_SIZE
,
200 .virtual = OMAP44XX_GPMC_VIRT
,
201 .pfn
= __phys_to_pfn(OMAP44XX_GPMC_PHYS
),
202 .length
= OMAP44XX_GPMC_SIZE
,
206 .virtual = OMAP44XX_EMIF1_VIRT
,
207 .pfn
= __phys_to_pfn(OMAP44XX_EMIF1_PHYS
),
208 .length
= OMAP44XX_EMIF1_SIZE
,
212 .virtual = OMAP44XX_EMIF2_VIRT
,
213 .pfn
= __phys_to_pfn(OMAP44XX_EMIF2_PHYS
),
214 .length
= OMAP44XX_EMIF2_SIZE
,
218 .virtual = OMAP44XX_DMM_VIRT
,
219 .pfn
= __phys_to_pfn(OMAP44XX_DMM_PHYS
),
220 .length
= OMAP44XX_DMM_SIZE
,
224 .virtual = L4_PER_44XX_VIRT
,
225 .pfn
= __phys_to_pfn(L4_PER_44XX_PHYS
),
226 .length
= L4_PER_44XX_SIZE
,
230 .virtual = L4_EMU_44XX_VIRT
,
231 .pfn
= __phys_to_pfn(L4_EMU_44XX_PHYS
),
232 .length
= L4_EMU_44XX_SIZE
,
238 void __init
omap2_map_common_io(void)
240 #if defined(CONFIG_ARCH_OMAP2420)
241 iotable_init(omap24xx_io_desc
, ARRAY_SIZE(omap24xx_io_desc
));
242 iotable_init(omap242x_io_desc
, ARRAY_SIZE(omap242x_io_desc
));
245 #if defined(CONFIG_ARCH_OMAP2430)
246 iotable_init(omap24xx_io_desc
, ARRAY_SIZE(omap24xx_io_desc
));
247 iotable_init(omap243x_io_desc
, ARRAY_SIZE(omap243x_io_desc
));
250 #if defined(CONFIG_ARCH_OMAP34XX)
251 iotable_init(omap34xx_io_desc
, ARRAY_SIZE(omap34xx_io_desc
));
254 #if defined(CONFIG_ARCH_OMAP4)
255 iotable_init(omap44xx_io_desc
, ARRAY_SIZE(omap44xx_io_desc
));
257 /* Normally devicemaps_init() would flush caches and tlb after
258 * mdesc->map_io(), but we must also do it here because of the CPU
259 * revision check below.
261 local_flush_tlb_all();
264 omap2_check_revision();
266 omapfb_reserve_sdram();
270 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
272 * Sets the CORE DPLL3 M2 divider to the same value that it's at
273 * currently. This has the effect of setting the SDRC SDRAM AC timing
274 * registers to the values currently defined by the kernel. Currently
275 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
276 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
277 * or passes along the return value of clk_set_rate().
279 static int __init
_omap2_init_reprogram_sdrc(void)
281 struct clk
*dpll3_m2_ck
;
285 if (!cpu_is_omap34xx())
288 dpll3_m2_ck
= clk_get(NULL
, "dpll3_m2_ck");
292 rate
= clk_get_rate(dpll3_m2_ck
);
293 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate
);
294 v
= clk_set_rate(dpll3_m2_ck
, rate
);
296 pr_err("dpll3_m2_clk rate change failed: %d\n", v
);
298 clk_put(dpll3_m2_ck
);
303 void __init
omap2_init_common_hw(struct omap_sdrc_params
*sdrc_cs0
,
304 struct omap_sdrc_params
*sdrc_cs1
,
305 struct omap_opp
*mpu_opps
,
306 struct omap_opp
*dsp_opps
,
307 struct omap_opp
*l3_opps
)
309 struct omap_hwmod
**hwmods
= NULL
;
311 if (cpu_is_omap2420())
312 hwmods
= omap2420_hwmods
;
313 else if (cpu_is_omap2430())
314 hwmods
= omap2430_hwmods
;
315 else if (cpu_is_omap34xx())
316 hwmods
= omap34xx_hwmods
;
318 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
319 /* The OPP tables have to be registered before a clk init */
320 omap_hwmod_init(hwmods
);
322 omap_pm_if_early_init(mpu_opps
, dsp_opps
, l3_opps
);
323 pwrdm_init(powerdomains_omap
);
324 clkdm_init(clockdomains_omap
, clkdm_pwrdm_autodeps
);
327 omap_serial_early_init();
328 #ifndef CONFIG_ARCH_OMAP4
329 omap_hwmod_late_init();
331 omap2_sdrc_init(sdrc_cs0
, sdrc_cs1
);
332 _omap2_init_reprogram_sdrc();