| blob | 029d376198d4c592bf4c145907ea231c5b7d62a9 |
1 /*
2 * linux/arch/arm/mach-omap2/prcm.c
3 *
4 * OMAP 24xx Power Reset and Clock Management (PRCM) functions
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 *
10 * Copyright (C) 2007 Texas Instruments, Inc.
11 * Rajendra Nayak <rnayak@ti.com>
12 *
13 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23 #include <linux/delay.h>
25 #include <plat/common.h>
26 #include <plat/prcm.h>
27 #include <plat/irqs.h>
28 #include <plat/control.h>
38 #define MAX_MODULE_ENABLE_WAIT 100000
41 u32 control_padconf_sys_nirq;
42 u32 iva2_cm_clksel1;
43 u32 iva2_cm_clksel2;
44 u32 cm_sysconfig;
45 u32 sgx_cm_clksel;
46 u32 wkup_cm_clksel;
47 u32 dss_cm_clksel;
48 u32 cam_cm_clksel;
49 u32 per_cm_clksel;
50 u32 emu_cm_clksel;
51 u32 emu_cm_clkstctrl;
52 u32 pll_cm_autoidle2;
53 u32 pll_cm_clksel4;
54 u32 pll_cm_clksel5;
55 u32 pll_cm_clken;
56 u32 pll_cm_clken2;
57 u32 cm_polctrl;
58 u32 iva2_cm_fclken;
59 u32 iva2_cm_clken_pll;
60 u32 core_cm_fclken1;
61 u32 core_cm_fclken3;
62 u32 sgx_cm_fclken;
63 u32 wkup_cm_fclken;
64 u32 dss_cm_fclken;
65 u32 cam_cm_fclken;
66 u32 per_cm_fclken;
67 u32 usbhost_cm_fclken;
68 u32 core_cm_iclken1;
69 u32 core_cm_iclken2;
70 u32 core_cm_iclken3;
71 u32 sgx_cm_iclken;
72 u32 wkup_cm_iclken;
73 u32 dss_cm_iclken;
74 u32 cam_cm_iclken;
75 u32 per_cm_iclken;
76 u32 usbhost_cm_iclken;
77 u32 iva2_cm_autiidle2;
78 u32 mpu_cm_autoidle2;
79 u32 pll_cm_autoidle;
80 u32 iva2_cm_clkstctrl;
81 u32 mpu_cm_clkstctrl;
82 u32 core_cm_clkstctrl;
83 u32 sgx_cm_clkstctrl;
84 u32 dss_cm_clkstctrl;
85 u32 cam_cm_clkstctrl;
86 u32 per_cm_clkstctrl;
87 u32 neon_cm_clkstctrl;
88 u32 usbhost_cm_clkstctrl;
89 u32 core_cm_autoidle1;
90 u32 core_cm_autoidle2;
91 u32 core_cm_autoidle3;
92 u32 wkup_cm_autoidle;
93 u32 dss_cm_autoidle;
94 u32 cam_cm_autoidle;
95 u32 per_cm_autoidle;
96 u32 usbhost_cm_autoidle;
97 u32 sgx_cm_sleepdep;
98 u32 dss_cm_sleepdep;
99 u32 cam_cm_sleepdep;
100 u32 per_cm_sleepdep;
101 u32 usbhost_cm_sleepdep;
102 u32 cm_clkout_ctrl;
103 u32 prm_clkout_ctrl;
104 u32 sgx_pm_wkdep;
105 u32 dss_pm_wkdep;
106 u32 cam_pm_wkdep;
107 u32 per_pm_wkdep;
108 u32 neon_pm_wkdep;
109 u32 usbhost_pm_wkdep;
110 u32 core_pm_mpugrpsel1;
111 u32 iva2_pm_ivagrpsel1;
112 u32 core_pm_mpugrpsel3;
113 u32 core_pm_ivagrpsel3;
114 u32 wkup_pm_mpugrpsel;
115 u32 wkup_pm_ivagrpsel;
116 u32 per_pm_mpugrpsel;
117 u32 per_pm_ivagrpsel;
118 u32 wkup_pm_wken;
119 };
124 {
125 /* XXX This presumably needs modification for 34XX */
127 }
130 /* Resets clock rates and reboots the system. Only called from system.h */
132 {
133 s16 prcm_offs;
139 u32 l;
143 /* Reserve the first word in scratchpad for communicating
144 * with the boot ROM. A pointer to a data structure
145 * describing the boot process can be stored there,
146 * cf. OMAP34xx TRM, Initialization / Software Booting
147 * Configuration. */
153 }
156 {
159 }
163 {
166 }
168 /* Read a register in a PRM module */
170 {
172 }
175 /* Write into a register in a PRM module */
177 {
179 }
182 /* Read-modify-write a register in a PRM module. Caller must lock */
184 {
185 u32 v;
193 }
196 /* Read a register in a CM module */
198 {
200 }
203 /* Write into a register in a CM module */
205 {
207 }
210 /* Read-modify-write a register in a CM module. Caller must lock */
212 {
213 u32 v;
221 }
224 /**
225 * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
226 * @reg: physical address of module IDLEST register
227 * @mask: value to mask against to determine if the module is active
228 * @name: name of the clock (for printk)
229 *
230 * Returns 1 if the module indicated readiness in time, or 0 if it
231 * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
232 */
234 {
238 /*
239 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
240 * 34xx reverses this, just to keep us on our toes
241 */
246 else
249 /* Wait for lock */
257 else
262 };
265 {
268 }
270 #ifdef CONFIG_ARCH_OMAP3
272 {
307 OMAP3430_CM_CLKEN_PLL);
393 OMAP3_CM_CLKOUT_CTRL_OFFSET);
395 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
426 }
429 {
431 OMAP343X_CONTROL_PADCONF_SYSNIRQ);
433 CM_CLKSEL1);
435 CM_CLKSEL2);
438 CM_CLKSEL);
441 CM_CLKSEL);
443 CM_CLKSEL);
445 CM_CLKSEL);
447 CM_CLKSEL1);
449 CM_CLKSTCTRL);
451 CM_AUTOIDLE2);
453 OMAP3430ES2_CM_CLKSEL4);
455 OMAP3430ES2_CM_CLKSEL5);
458 OMAP3430ES2_CM_CLKEN2);
461 CM_FCLKEN);
463 OMAP3430_CM_CLKEN_PLL);
466 OMAP3430ES2_CM_FCLKEN3);
468 CM_FCLKEN);
471 CM_FCLKEN);
473 CM_FCLKEN);
475 CM_FCLKEN);
482 CM_ICLKEN);
485 CM_ICLKEN);
487 CM_ICLKEN);
489 CM_ICLKEN);
493 CM_AUTOIDLE2);
497 CM_CLKSTCTRL);
500 CM_CLKSTCTRL);
502 CM_CLKSTCTRL);
504 CM_CLKSTCTRL);
506 CM_CLKSTCTRL);
508 CM_CLKSTCTRL);
510 CM_CLKSTCTRL);
514 CM_AUTOIDLE1);
516 CM_AUTOIDLE2);
518 CM_AUTOIDLE3);
521 CM_AUTOIDLE);
523 CM_AUTOIDLE);
525 CM_AUTOIDLE);
529 OMAP3430_CM_SLEEPDEP);
531 OMAP3430_CM_SLEEPDEP);
533 OMAP3430_CM_SLEEPDEP);
535 OMAP3430_CM_SLEEPDEP);
539 OMAP3_CM_CLKOUT_CTRL_OFFSET);
541 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
543 PM_WKDEP);
545 PM_WKDEP);
547 PM_WKDEP);
549 PM_WKDEP);
551 PM_WKDEP);
555 OMAP3430_PM_MPUGRPSEL1);
557 OMAP3430_PM_IVAGRPSEL1);
559 OMAP3430ES2_PM_MPUGRPSEL3);
561 OMAP3430ES2_PM_IVAGRPSEL3);
563 OMAP3430_PM_MPUGRPSEL);
565 OMAP3430_PM_IVAGRPSEL);
567 OMAP3430_PM_MPUGRPSEL);
569 OMAP3430_PM_IVAGRPSEL);
572 }
573 #endif