?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[PATCH] dvb: saa7134-dvb must select tda1004x
[linux-ginger.git] / sound / pci / cmipci.c
blobb098b51099c2ddbccac84f9ebf2ebae629837b90
1 /*
2 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
3 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 /* Does not work. Warning may block system in capture mode */
21 /* #define USE_VAR48KRATE */
22
23 #include <sound/driver.h>
24 #include <asm/io.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/pci.h>
29 #include <linux/slab.h>
30 #include <linux/gameport.h>
31 #include <linux/moduleparam.h>
32 #include <sound/core.h>
33 #include <sound/info.h>
34 #include <sound/control.h>
35 #include <sound/pcm.h>
36 #include <sound/rawmidi.h>
37 #include <sound/mpu401.h>
38 #include <sound/opl3.h>
39 #include <sound/sb.h>
40 #include <sound/asoundef.h>
41 #include <sound/initval.h>
42
43 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
44 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
45 MODULE_LICENSE("GPL");
46 MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
47 "{C-Media,CMI8738B},"
48 "{C-Media,CMI8338A},"
49 "{C-Media,CMI8338B}}");
50
51 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
52 #define SUPPORT_JOYSTICK 1
53 #endif
54
55 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
56 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
57 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
58 static long mpu_port[SNDRV_CARDS];
59 static long fm_port[SNDRV_CARDS];
60 static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
61 #ifdef SUPPORT_JOYSTICK
62 static int joystick_port[SNDRV_CARDS];
63 #endif
64
65 module_param_array(index, int, NULL, 0444);
66 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
67 module_param_array(id, charp, NULL, 0444);
68 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
69 module_param_array(enable, bool, NULL, 0444);
70 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
71 module_param_array(mpu_port, long, NULL, 0444);
72 MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
73 module_param_array(fm_port, long, NULL, 0444);
74 MODULE_PARM_DESC(fm_port, "FM port.");
75 module_param_array(soft_ac3, bool, NULL, 0444);
76 MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only).");
77 #ifdef SUPPORT_JOYSTICK
78 module_param_array(joystick_port, int, NULL, 0444);
79 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
80 #endif
81
82 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738
83 #define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111
84 #endif
85 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738B
86 #define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112
87 #endif
88
89 /*
90 * CM8x38 registers definition
91 */
92
93 #define CM_REG_FUNCTRL0 0x00
94 #define CM_RST_CH1 0x00080000
95 #define CM_RST_CH0 0x00040000
96 #define CM_CHEN1 0x00020000 /* ch1: enable */
97 #define CM_CHEN0 0x00010000 /* ch0: enable */
98 #define CM_PAUSE1 0x00000008 /* ch1: pause */
99 #define CM_PAUSE0 0x00000004 /* ch0: pause */
100 #define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
101 #define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
102
103 #define CM_REG_FUNCTRL1 0x04
104 #define CM_ASFC_MASK 0x0000E000 /* ADC sampling frequency */
105 #define CM_ASFC_SHIFT 13
106 #define CM_DSFC_MASK 0x00001C00 /* DAC sampling frequency */
107 #define CM_DSFC_SHIFT 10
108 #define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
109 #define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
110 #define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/OUT -> IN loopback */
111 #define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
112 #define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
113 #define CM_BREQ 0x00000010 /* bus master enabled */
114 #define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
115 #define CM_UART_EN 0x00000004 /* UART */
116 #define CM_JYSTK_EN 0x00000002 /* joy stick */
117
118 #define CM_REG_CHFORMAT 0x08
119
120 #define CM_CHB3D5C 0x80000000 /* 5,6 channels */
121 #define CM_CHB3D 0x20000000 /* 4 channels */
122
123 #define CM_CHIP_MASK1 0x1f000000
124 #define CM_CHIP_037 0x01000000
125
126 #define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
127 #define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
128 #define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
129 /* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
130
131 #define CM_ADCBITLEN_MASK 0x0000C000
132 #define CM_ADCBITLEN_16 0x00000000
133 #define CM_ADCBITLEN_15 0x00004000
134 #define CM_ADCBITLEN_14 0x00008000
135 #define CM_ADCBITLEN_13 0x0000C000
136
137 #define CM_ADCDACLEN_MASK 0x00003000
138 #define CM_ADCDACLEN_060 0x00000000
139 #define CM_ADCDACLEN_066 0x00001000
140 #define CM_ADCDACLEN_130 0x00002000
141 #define CM_ADCDACLEN_280 0x00003000
142
143 #define CM_CH1_SRATE_176K 0x00000800
144 #define CM_CH1_SRATE_88K 0x00000400
145 #define CM_CH0_SRATE_176K 0x00000200
146 #define CM_CH0_SRATE_88K 0x00000100
147
148 #define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
149
150 #define CM_CH1FMT_MASK 0x0000000C
151 #define CM_CH1FMT_SHIFT 2
152 #define CM_CH0FMT_MASK 0x00000003
153 #define CM_CH0FMT_SHIFT 0
154
155 #define CM_REG_INT_HLDCLR 0x0C
156 #define CM_CHIP_MASK2 0xff000000
157 #define CM_CHIP_039 0x04000000
158 #define CM_CHIP_039_6CH 0x01000000
159 #define CM_CHIP_055 0x08000000
160 #define CM_CHIP_8768 0x20000000
161 #define CM_TDMA_INT_EN 0x00040000
162 #define CM_CH1_INT_EN 0x00020000
163 #define CM_CH0_INT_EN 0x00010000
164 #define CM_INT_HOLD 0x00000002
165 #define CM_INT_CLEAR 0x00000001
166
167 #define CM_REG_INT_STATUS 0x10
168 #define CM_INTR 0x80000000
169 #define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
170 #define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
171 #define CM_UARTINT 0x00010000
172 #define CM_LTDMAINT 0x00008000
173 #define CM_HTDMAINT 0x00004000
174 #define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
175 #define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
176 #define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
177 #define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
178 #define CM_CH1BUSY 0x00000008
179 #define CM_CH0BUSY 0x00000004
180 #define CM_CHINT1 0x00000002
181 #define CM_CHINT0 0x00000001
182
183 #define CM_REG_LEGACY_CTRL 0x14
184 #define CM_NXCHG 0x80000000 /* h/w multi channels? */
185 #define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
186 #define CM_VMPU_330 0x00000000
187 #define CM_VMPU_320 0x20000000
188 #define CM_VMPU_310 0x40000000
189 #define CM_VMPU_300 0x60000000
190 #define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
191 #define CM_VSBSEL_220 0x00000000
192 #define CM_VSBSEL_240 0x04000000
193 #define CM_VSBSEL_260 0x08000000
194 #define CM_VSBSEL_280 0x0C000000
195 #define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
196 #define CM_FMSEL_388 0x00000000
197 #define CM_FMSEL_3C8 0x01000000
198 #define CM_FMSEL_3E0 0x02000000
199 #define CM_FMSEL_3E8 0x03000000
200 #define CM_ENSPDOUT 0x00800000 /* enable XPDIF/OUT to I/O interface */
201 #define CM_SPDCOPYRHT 0x00400000 /* set copyright spdif in/out */
202 #define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
203 #define CM_SETRETRY 0x00010000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
204 #define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
205 #define CM_LINE_AS_BASS 0x00006000 /* use line-in as bass */
206
207 #define CM_REG_MISC_CTRL 0x18
208 #define CM_PWD 0x80000000
209 #define CM_RESET 0x40000000
210 #define CM_SFIL_MASK 0x30000000
211 #define CM_TXVX 0x08000000
212 #define CM_N4SPK3D 0x04000000 /* 4ch output */
213 #define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
214 #define CM_SPDIF48K 0x01000000 /* write */
215 #define CM_SPATUS48K 0x01000000 /* read */
216 #define CM_ENDBDAC 0x00800000 /* enable dual dac */
217 #define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
218 #define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
219 #define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-IN -> int. OUT */
220 #define CM_FM_EN 0x00080000 /* enalbe FM */
221 #define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
222 #define CM_VIDWPDSB 0x00010000
223 #define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
224 #define CM_MASK_EN 0x00004000
225 #define CM_VIDWPPRT 0x00002000
226 #define CM_SFILENB 0x00001000
227 #define CM_MMODE_MASK 0x00000E00
228 #define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
229 #define CM_ENCENTER 0x00000080
230 #define CM_FLINKON 0x00000040
231 #define CM_FLINKOFF 0x00000020
232 #define CM_MIDSMP 0x00000010
233 #define CM_UPDDMA_MASK 0x0000000C
234 #define CM_TWAIT_MASK 0x00000003
235
236 /* byte */
237 #define CM_REG_MIXER0 0x20
238
239 #define CM_REG_SB16_DATA 0x22
240 #define CM_REG_SB16_ADDR 0x23
241
242 #define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
243 #define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
244 #define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
245 #define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
246
247 #define CM_REG_MIXER1 0x24
248 #define CM_FMMUTE 0x80 /* mute FM */
249 #define CM_FMMUTE_SHIFT 7
250 #define CM_WSMUTE 0x40 /* mute PCM */
251 #define CM_WSMUTE_SHIFT 6
252 #define CM_SPK4 0x20 /* lin-in -> rear line out */
253 #define CM_SPK4_SHIFT 5
254 #define CM_REAR2FRONT 0x10 /* exchange rear/front */
255 #define CM_REAR2FRONT_SHIFT 4
256 #define CM_WAVEINL 0x08 /* digital wave rec. left chan */
257 #define CM_WAVEINL_SHIFT 3
258 #define CM_WAVEINR 0x04 /* digical wave rec. right */
259 #define CM_WAVEINR_SHIFT 2
260 #define CM_X3DEN 0x02 /* 3D surround enable */
261 #define CM_X3DEN_SHIFT 1
262 #define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
263 #define CM_CDPLAY_SHIFT 0
264
265 #define CM_REG_MIXER2 0x25
266 #define CM_RAUXREN 0x80 /* AUX right capture */
267 #define CM_RAUXREN_SHIFT 7
268 #define CM_RAUXLEN 0x40 /* AUX left capture */
269 #define CM_RAUXLEN_SHIFT 6
270 #define CM_VAUXRM 0x20 /* AUX right mute */
271 #define CM_VAUXRM_SHIFT 5
272 #define CM_VAUXLM 0x10 /* AUX left mute */
273 #define CM_VAUXLM_SHIFT 4
274 #define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
275 #define CM_VADMIC_SHIFT 1
276 #define CM_MICGAINZ 0x01 /* mic boost */
277 #define CM_MICGAINZ_SHIFT 0
278
279 #define CM_REG_AUX_VOL 0x26
280 #define CM_VAUXL_MASK 0xf0
281 #define CM_VAUXR_MASK 0x0f
282
283 #define CM_REG_MISC 0x27
284 #define CM_XGPO1 0x20
285 // #define CM_XGPBIO 0x04
286 #define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
287 #define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
288 #define CM_SPDVALID 0x02 /* spdif input valid check */
289 #define CM_DMAUTO 0x01
290
291 #define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
292 /*
293 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
294 * or identical with AC97 codec?
295 */
296 #define CM_REG_EXTERN_CODEC CM_REG_AC97
297
298 /*
299 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
300 */
301 #define CM_REG_MPU_PCI 0x40
302
303 /*
304 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
305 */
306 #define CM_REG_FM_PCI 0x50
307
308 /*
309 * access from SB-mixer port
310 */
311 #define CM_REG_EXTENT_IND 0xf0
312 #define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
313 #define CM_VPHONE_SHIFT 5
314 #define CM_VPHOM 0x10 /* Phone mute control */
315 #define CM_VSPKM 0x08 /* Speaker mute control, default high */
316 #define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
317 #define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
318 #define CM_VADMIC3 0x01 /* Mic record boost */
319
320 /*
321 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
322 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
323 * unit (readonly?).
324 */
325 #define CM_REG_PLL 0xf8
326
327 /*
328 * extended registers
329 */
330 #define CM_REG_CH0_FRAME1 0x80 /* base address */
331 #define CM_REG_CH0_FRAME2 0x84
332 #define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
333 #define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
334 #define CM_REG_MISC_CTRL_8768 0x92 /* reg. name the same as 0x18 */
335 #define CM_CHB3D8C 0x20 /* 7.1 channels support */
336 #define CM_SPD32FMT 0x10 /* SPDIF/IN 32k */
337 #define CM_ADC2SPDIF 0x08 /* ADC output to SPDIF/OUT */
338 #define CM_SHAREADC 0x04 /* DAC in ADC as Center/LFE */
339 #define CM_REALTCMP 0x02 /* monitor the CMPL/CMPR of ADC */
340 #define CM_INVLRCK 0x01 /* invert ZVPORT's LRCK */
341
342 /*
343 * size of i/o region
344 */
345 #define CM_EXTENT_CODEC 0x100
346 #define CM_EXTENT_MIDI 0x2
347 #define CM_EXTENT_SYNTH 0x4
348
349
350 /*
351 * pci ids
352 */
353 #ifndef PCI_VENDOR_ID_CMEDIA
354 #define PCI_VENDOR_ID_CMEDIA 0x13F6
355 #endif
356 #ifndef PCI_DEVICE_ID_CMEDIA_CM8338A
357 #define PCI_DEVICE_ID_CMEDIA_CM8338A 0x0100
358 #endif
359 #ifndef PCI_DEVICE_ID_CMEDIA_CM8338B
360 #define PCI_DEVICE_ID_CMEDIA_CM8338B 0x0101
361 #endif
362 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738
363 #define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111
364 #endif
365 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738B
366 #define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112
367 #endif
368
369 /*
370 * channels for playback / capture
371 */
372 #define CM_CH_PLAY 0
373 #define CM_CH_CAPT 1
374
375 /*
376 * flags to check device open/close
377 */
378 #define CM_OPEN_NONE 0
379 #define CM_OPEN_CH_MASK 0x01
380 #define CM_OPEN_DAC 0x10
381 #define CM_OPEN_ADC 0x20
382 #define CM_OPEN_SPDIF 0x40
383 #define CM_OPEN_MCHAN 0x80
384 #define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
385 #define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
386 #define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
387 #define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
388 #define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
389 #define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
390
391
392 #if CM_CH_PLAY == 1
393 #define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
394 #define CM_PLAYBACK_SPDF CM_SPDF_1
395 #define CM_CAPTURE_SPDF CM_SPDF_0
396 #else
397 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
398 #define CM_PLAYBACK_SPDF CM_SPDF_0
399 #define CM_CAPTURE_SPDF CM_SPDF_1
400 #endif
401
402
403 /*
404 * driver data
405 */
406
407 typedef struct snd_stru_cmipci cmipci_t;
408 typedef struct snd_stru_cmipci_pcm cmipci_pcm_t;
409
410 struct snd_stru_cmipci_pcm {
411 snd_pcm_substream_t *substream;
412 int running; /* dac/adc running? */
413 unsigned int dma_size; /* in frames */
414 unsigned int period_size; /* in frames */
415 unsigned int offset; /* physical address of the buffer */
416 unsigned int fmt; /* format bits */
417 int ch; /* channel (0/1) */
418 unsigned int is_dac; /* is dac? */
419 int bytes_per_frame;
420 int shift;
421 };
422
423 /* mixer elements toggled/resumed during ac3 playback */
424 struct cmipci_mixer_auto_switches {
425 const char *name; /* switch to toggle */
426 int toggle_on; /* value to change when ac3 mode */
427 };
428 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
429 {"PCM Playback Switch", 0},
430 {"IEC958 Output Switch", 1},
431 {"IEC958 Mix Analog", 0},
432 // {"IEC958 Out To DAC", 1}, // no longer used
433 {"IEC958 Loop", 0},
434 };
435 #define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
436
437 struct snd_stru_cmipci {
438 snd_card_t *card;
439
440 struct pci_dev *pci;
441 unsigned int device; /* device ID */
442 int irq;
443
444 unsigned long iobase;
445 unsigned int ctrl; /* FUNCTRL0 current value */
446
447 snd_pcm_t *pcm; /* DAC/ADC PCM */
448 snd_pcm_t *pcm2; /* 2nd DAC */
449 snd_pcm_t *pcm_spdif; /* SPDIF */
450
451 int chip_version;
452 int max_channels;
453 unsigned int has_dual_dac: 1;
454 unsigned int can_ac3_sw: 1;
455 unsigned int can_ac3_hw: 1;
456 unsigned int can_multi_ch: 1;
457 unsigned int do_soft_ac3: 1;
458
459 unsigned int spdif_playback_avail: 1; /* spdif ready? */
460 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
461 int spdif_counter; /* for software AC3 */
462
463 unsigned int dig_status;
464 unsigned int dig_pcm_status;
465
466 snd_pcm_hardware_t *hw_info[3]; /* for playbacks */
467
468 int opened[2]; /* open mode */
469 struct semaphore open_mutex;
470
471 unsigned int mixer_insensitive: 1;
472 snd_kcontrol_t *mixer_res_ctl[CM_SAVED_MIXERS];
473 int mixer_res_status[CM_SAVED_MIXERS];
474
475 opl3_t *opl3;
476 snd_hwdep_t *opl3hwdep;
477
478 cmipci_pcm_t channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
479
480 /* external MIDI */
481 snd_rawmidi_t *rmidi;
482
483 #ifdef SUPPORT_JOYSTICK
484 struct gameport *gameport;
485 #endif
486
487 spinlock_t reg_lock;
488 };
489
490
491 /* read/write operations for dword register */
492 static inline void snd_cmipci_write(cmipci_t *cm, unsigned int cmd, unsigned int data)
493 {
494 outl(data, cm->iobase + cmd);
495 }
496
497 static inline unsigned int snd_cmipci_read(cmipci_t *cm, unsigned int cmd)
498 {
499 return inl(cm->iobase + cmd);
500 }
501
502 /* read/write operations for word register */
503 static inline void snd_cmipci_write_w(cmipci_t *cm, unsigned int cmd, unsigned short data)
504 {
505 outw(data, cm->iobase + cmd);
506 }
507
508 static inline unsigned short snd_cmipci_read_w(cmipci_t *cm, unsigned int cmd)
509 {
510 return inw(cm->iobase + cmd);
511 }
512
513 /* read/write operations for byte register */
514 static inline void snd_cmipci_write_b(cmipci_t *cm, unsigned int cmd, unsigned char data)
515 {
516 outb(data, cm->iobase + cmd);
517 }
518
519 static inline unsigned char snd_cmipci_read_b(cmipci_t *cm, unsigned int cmd)
520 {
521 return inb(cm->iobase + cmd);
522 }
523
524 /* bit operations for dword register */
525 static int snd_cmipci_set_bit(cmipci_t *cm, unsigned int cmd, unsigned int flag)
526 {
527 unsigned int val, oval;
528 val = oval = inl(cm->iobase + cmd);
529 val |= flag;
530 if (val == oval)
531 return 0;
532 outl(val, cm->iobase + cmd);
533 return 1;
534 }
535
536 static int snd_cmipci_clear_bit(cmipci_t *cm, unsigned int cmd, unsigned int flag)
537 {
538 unsigned int val, oval;
539 val = oval = inl(cm->iobase + cmd);
540 val &= ~flag;
541 if (val == oval)
542 return 0;
543 outl(val, cm->iobase + cmd);
544 return 1;
545 }
546
547 /* bit operations for byte register */
548 static int snd_cmipci_set_bit_b(cmipci_t *cm, unsigned int cmd, unsigned char flag)
549 {
550 unsigned char val, oval;
551 val = oval = inb(cm->iobase + cmd);
552 val |= flag;
553 if (val == oval)
554 return 0;
555 outb(val, cm->iobase + cmd);
556 return 1;
557 }
558
559 static int snd_cmipci_clear_bit_b(cmipci_t *cm, unsigned int cmd, unsigned char flag)
560 {
561 unsigned char val, oval;
562 val = oval = inb(cm->iobase + cmd);
563 val &= ~flag;
564 if (val == oval)
565 return 0;
566 outb(val, cm->iobase + cmd);
567 return 1;
568 }
569
570
571 /*
572 * PCM interface
573 */
574
575 /*
576 * calculate frequency
577 */
578
579 static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
580
581 static unsigned int snd_cmipci_rate_freq(unsigned int rate)
582 {
583 unsigned int i;
584 for (i = 0; i < ARRAY_SIZE(rates); i++) {
585 if (rates[i] == rate)
586 return i;
587 }
588 snd_BUG();
589 return 0;
590 }
591
592 #ifdef USE_VAR48KRATE
593 /*
594 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
595 * does it this way .. maybe not. Never get any information from C-Media about
596 * that <werner@suse.de>.
597 */
598 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
599 {
600 unsigned int delta, tolerance;
601 int xm, xn, xr;
602
603 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
604 rate <<= 1;
605 *n = -1;
606 if (*r > 0xff)
607 goto out;
608 tolerance = rate*CM_TOLERANCE_RATE;
609
610 for (xn = (1+2); xn < (0x1f+2); xn++) {
611 for (xm = (1+2); xm < (0xff+2); xm++) {
612 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
613
614 if (xr < rate)
615 delta = rate - xr;
616 else
617 delta = xr - rate;
618
619 /*
620 * If we found one, remember this,
621 * and try to find a closer one
622 */
623 if (delta < tolerance) {
624 tolerance = delta;
625 *m = xm - 2;
626 *n = xn - 2;
627 }
628 }
629 }
630 out:
631 return (*n > -1);
632 }
633
634 /*
635 * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff
636 * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen
637 * at the register CM_REG_FUNCTRL1 (0x04).
638 * Problem: other ways are also possible (any information about that?)
639 */
640 static void snd_cmipci_set_pll(cmipci_t *cm, unsigned int rate, unsigned int slot)
641 {
642 unsigned int reg = CM_REG_PLL + slot;
643 /*
644 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
645 * for DSFC/ASFC (000 upto 111).
646 */
647
648 /* FIXME: Init (Do we've to set an other register first before programming?) */
649
650 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
651 snd_cmipci_write_b(cm, reg, rate>>8);
652 snd_cmipci_write_b(cm, reg, rate&0xff);
653
654 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
655 }
656 #endif /* USE_VAR48KRATE */
657
658 static int snd_cmipci_hw_params(snd_pcm_substream_t * substream,
659 snd_pcm_hw_params_t * hw_params)
660 {
661 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
662 }
663
664 static int snd_cmipci_playback2_hw_params(snd_pcm_substream_t * substream,
665 snd_pcm_hw_params_t * hw_params)
666 {
667 cmipci_t *cm = snd_pcm_substream_chip(substream);
668 if (params_channels(hw_params) > 2) {
669 down(&cm->open_mutex);
670 if (cm->opened[CM_CH_PLAY]) {
671 up(&cm->open_mutex);
672 return -EBUSY;
673 }
674 /* reserve the channel A */
675 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
676 up(&cm->open_mutex);
677 }
678 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
679 }
680
681 static void snd_cmipci_ch_reset(cmipci_t *cm, int ch)
682 {
683 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
684 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
685 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
686 udelay(10);
687 }
688
689 static int snd_cmipci_hw_free(snd_pcm_substream_t * substream)
690 {
691 return snd_pcm_lib_free_pages(substream);
692 }
693
694
695 /*
696 */
697
698 static unsigned int hw_channels[] = {1, 2, 4, 5, 6, 8};
699 static snd_pcm_hw_constraint_list_t hw_constraints_channels_4 = {
700 .count = 3,
701 .list = hw_channels,
702 .mask = 0,
703 };
704 static snd_pcm_hw_constraint_list_t hw_constraints_channels_6 = {
705 .count = 5,
706 .list = hw_channels,
707 .mask = 0,
708 };
709 static snd_pcm_hw_constraint_list_t hw_constraints_channels_8 = {
710 .count = 6,
711 .list = hw_channels,
712 .mask = 0,
713 };
714
715 static int set_dac_channels(cmipci_t *cm, cmipci_pcm_t *rec, int channels)
716 {
717 if (channels > 2) {
718 if (! cm->can_multi_ch)
719 return -EINVAL;
720 if (rec->fmt != 0x03) /* stereo 16bit only */
721 return -EINVAL;
722
723 spin_lock_irq(&cm->reg_lock);
724 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
725 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
726 if (channels > 4) {
727 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
728 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
729 } else {
730 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
731 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
732 }
733 if (channels >= 6) {
734 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
735 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
736 } else {
737 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
738 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
739 }
740 if (cm->chip_version == 68) {
741 if (channels == 8) {
742 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C);
743 } else {
744 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C);
745 }
746 }
747 spin_unlock_irq(&cm->reg_lock);
748
749 } else {
750 if (cm->can_multi_ch) {
751 spin_lock_irq(&cm->reg_lock);
752 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
753 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
754 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
755 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
756 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
757 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
758 spin_unlock_irq(&cm->reg_lock);
759 }
760 }
761 return 0;
762 }
763
764
765 /*
766 * prepare playback/capture channel
767 * channel to be used must have been set in rec->ch.
768 */
769 static int snd_cmipci_pcm_prepare(cmipci_t *cm, cmipci_pcm_t *rec,
770 snd_pcm_substream_t *substream)
771 {
772 unsigned int reg, freq, val;
773 snd_pcm_runtime_t *runtime = substream->runtime;
774
775 rec->fmt = 0;
776 rec->shift = 0;
777 if (snd_pcm_format_width(runtime->format) >= 16) {
778 rec->fmt |= 0x02;
779 if (snd_pcm_format_width(runtime->format) > 16)
780 rec->shift++; /* 24/32bit */
781 }
782 if (runtime->channels > 1)
783 rec->fmt |= 0x01;
784 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
785 snd_printd("cannot set dac channels\n");
786 return -EINVAL;
787 }
788
789 rec->offset = runtime->dma_addr;
790 /* buffer and period sizes in frame */
791 rec->dma_size = runtime->buffer_size << rec->shift;
792 rec->period_size = runtime->period_size << rec->shift;
793 if (runtime->channels > 2) {
794 /* multi-channels */
795 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
796 rec->period_size = (rec->period_size * runtime->channels) / 2;
797 }
798
799 spin_lock_irq(&cm->reg_lock);
800
801 /* set buffer address */
802 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
803 snd_cmipci_write(cm, reg, rec->offset);
804 /* program sample counts */
805 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
806 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
807 snd_cmipci_write_w(cm, reg + 2, rec->period_size - 1);
808
809 /* set adc/dac flag */
810 val = rec->ch ? CM_CHADC1 : CM_CHADC0;
811 if (rec->is_dac)
812 cm->ctrl &= ~val;
813 else
814 cm->ctrl |= val;
815 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
816 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
817
818 /* set sample rate */
819 freq = snd_cmipci_rate_freq(runtime->rate);
820 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
821 if (rec->ch) {
822 val &= ~CM_ASFC_MASK;
823 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
824 } else {
825 val &= ~CM_DSFC_MASK;
826 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
827 }
828 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
829 //snd_printd("cmipci: functrl1 = %08x\n", val);
830
831 /* set format */
832 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
833 if (rec->ch) {
834 val &= ~CM_CH1FMT_MASK;
835 val |= rec->fmt << CM_CH1FMT_SHIFT;
836 } else {
837 val &= ~CM_CH0FMT_MASK;
838 val |= rec->fmt << CM_CH0FMT_SHIFT;
839 }
840 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
841 //snd_printd("cmipci: chformat = %08x\n", val);
842
843 rec->running = 0;
844 spin_unlock_irq(&cm->reg_lock);
845
846 return 0;
847 }
848
849 /*
850 * PCM trigger/stop
851 */
852 static int snd_cmipci_pcm_trigger(cmipci_t *cm, cmipci_pcm_t *rec,
853 snd_pcm_substream_t *substream, int cmd)
854 {
855 unsigned int inthld, chen, reset, pause;
856 int result = 0;
857
858 inthld = CM_CH0_INT_EN << rec->ch;
859 chen = CM_CHEN0 << rec->ch;
860 reset = CM_RST_CH0 << rec->ch;
861 pause = CM_PAUSE0 << rec->ch;
862
863 spin_lock(&cm->reg_lock);
864 switch (cmd) {
865 case SNDRV_PCM_TRIGGER_START:
866 rec->running = 1;
867 /* set interrupt */
868 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
869 cm->ctrl |= chen;
870 /* enable channel */
871 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
872 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
873 break;
874 case SNDRV_PCM_TRIGGER_STOP:
875 rec->running = 0;
876 /* disable interrupt */
877 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
878 /* reset */
879 cm->ctrl &= ~chen;
880 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
881 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
882 break;
883 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
884 cm->ctrl |= pause;
885 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
886 break;
887 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
888 cm->ctrl &= ~pause;
889 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
890 break;
891 default:
892 result = -EINVAL;
893 break;
894 }
895 spin_unlock(&cm->reg_lock);
896 return result;
897 }
898
899 /*
900 * return the current pointer
901 */
902 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(cmipci_t *cm, cmipci_pcm_t *rec,
903 snd_pcm_substream_t *substream)
904 {
905 size_t ptr;
906 unsigned int reg;
907 if (!rec->running)
908 return 0;
909 #if 1 // this seems better..
910 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
911 ptr = rec->dma_size - (snd_cmipci_read_w(cm, reg) + 1);
912 ptr >>= rec->shift;
913 #else
914 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
915 ptr = snd_cmipci_read(cm, reg) - rec->offset;
916 ptr = bytes_to_frames(substream->runtime, ptr);
917 #endif
918 if (substream->runtime->channels > 2)
919 ptr = (ptr * 2) / substream->runtime->channels;
920 return ptr;
921 }
922
923 /*
924 * playback
925 */
926
927 static int snd_cmipci_playback_trigger(snd_pcm_substream_t *substream,
928 int cmd)
929 {
930 cmipci_t *cm = snd_pcm_substream_chip(substream);
931 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], substream, cmd);
932 }
933
934 static snd_pcm_uframes_t snd_cmipci_playback_pointer(snd_pcm_substream_t *substream)
935 {
936 cmipci_t *cm = snd_pcm_substream_chip(substream);
937 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
938 }
939
940
941
942 /*
943 * capture
944 */
945
946 static int snd_cmipci_capture_trigger(snd_pcm_substream_t *substream,
947 int cmd)
948 {
949 cmipci_t *cm = snd_pcm_substream_chip(substream);
950 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], substream, cmd);
951 }
952
953 static snd_pcm_uframes_t snd_cmipci_capture_pointer(snd_pcm_substream_t *substream)
954 {
955 cmipci_t *cm = snd_pcm_substream_chip(substream);
956 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
957 }
958
959
960 /*
961 * hw preparation for spdif
962 */
963
964 static int snd_cmipci_spdif_default_info(snd_kcontrol_t *kcontrol,
965 snd_ctl_elem_info_t *uinfo)
966 {
967 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
968 uinfo->count = 1;
969 return 0;
970 }
971
972 static int snd_cmipci_spdif_default_get(snd_kcontrol_t *kcontrol,
973 snd_ctl_elem_value_t *ucontrol)
974 {
975 cmipci_t *chip = snd_kcontrol_chip(kcontrol);
976 int i;
977
978 spin_lock_irq(&chip->reg_lock);
979 for (i = 0; i < 4; i++)
980 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
981 spin_unlock_irq(&chip->reg_lock);
982 return 0;
983 }
984
985 static int snd_cmipci_spdif_default_put(snd_kcontrol_t * kcontrol,
986 snd_ctl_elem_value_t * ucontrol)
987 {
988 cmipci_t *chip = snd_kcontrol_chip(kcontrol);
989 int i, change;
990 unsigned int val;
991
992 val = 0;
993 spin_lock_irq(&chip->reg_lock);
994 for (i = 0; i < 4; i++)
995 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
996 change = val != chip->dig_status;
997 chip->dig_status = val;
998 spin_unlock_irq(&chip->reg_lock);
999 return change;
1000 }
1001
1002 static snd_kcontrol_new_t snd_cmipci_spdif_default __devinitdata =
1003 {
1004 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1005 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1006 .info = snd_cmipci_spdif_default_info,
1007 .get = snd_cmipci_spdif_default_get,
1008 .put = snd_cmipci_spdif_default_put
1009 };
1010
1011 static int snd_cmipci_spdif_mask_info(snd_kcontrol_t *kcontrol,
1012 snd_ctl_elem_info_t *uinfo)
1013 {
1014 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1015 uinfo->count = 1;
1016 return 0;
1017 }
1018
1019 static int snd_cmipci_spdif_mask_get(snd_kcontrol_t * kcontrol,
1020 snd_ctl_elem_value_t *ucontrol)
1021 {
1022 ucontrol->value.iec958.status[0] = 0xff;
1023 ucontrol->value.iec958.status[1] = 0xff;
1024 ucontrol->value.iec958.status[2] = 0xff;
1025 ucontrol->value.iec958.status[3] = 0xff;
1026 return 0;
1027 }
1028
1029 static snd_kcontrol_new_t snd_cmipci_spdif_mask __devinitdata =
1030 {
1031 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1032 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1033 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1034 .info = snd_cmipci_spdif_mask_info,
1035 .get = snd_cmipci_spdif_mask_get,
1036 };
1037
1038 static int snd_cmipci_spdif_stream_info(snd_kcontrol_t *kcontrol,
1039 snd_ctl_elem_info_t *uinfo)
1040 {
1041 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1042 uinfo->count = 1;
1043 return 0;
1044 }
1045
1046 static int snd_cmipci_spdif_stream_get(snd_kcontrol_t *kcontrol,
1047 snd_ctl_elem_value_t *ucontrol)
1048 {
1049 cmipci_t *chip = snd_kcontrol_chip(kcontrol);
1050 int i;
1051
1052 spin_lock_irq(&chip->reg_lock);
1053 for (i = 0; i < 4; i++)
1054 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1055 spin_unlock_irq(&chip->reg_lock);
1056 return 0;
1057 }
1058
1059 static int snd_cmipci_spdif_stream_put(snd_kcontrol_t *kcontrol,
1060 snd_ctl_elem_value_t *ucontrol)
1061 {
1062 cmipci_t *chip = snd_kcontrol_chip(kcontrol);
1063 int i, change;
1064 unsigned int val;
1065
1066 val = 0;
1067 spin_lock_irq(&chip->reg_lock);
1068 for (i = 0; i < 4; i++)
1069 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1070 change = val != chip->dig_pcm_status;
1071 chip->dig_pcm_status = val;
1072 spin_unlock_irq(&chip->reg_lock);
1073 return change;
1074 }
1075
1076 static snd_kcontrol_new_t snd_cmipci_spdif_stream __devinitdata =
1077 {
1078 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1079 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1080 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1081 .info = snd_cmipci_spdif_stream_info,
1082 .get = snd_cmipci_spdif_stream_get,
1083 .put = snd_cmipci_spdif_stream_put
1084 };
1085
1086 /*
1087 */
1088
1089 /* save mixer setting and mute for AC3 playback */
1090 static int save_mixer_state(cmipci_t *cm)
1091 {
1092 if (! cm->mixer_insensitive) {
1093 snd_ctl_elem_value_t *val;
1094 unsigned int i;
1095
1096 val = kmalloc(sizeof(*val), GFP_ATOMIC);
1097 if (!val)
1098 return -ENOMEM;
1099 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1100 snd_kcontrol_t *ctl = cm->mixer_res_ctl[i];
1101 if (ctl) {
1102 int event;
1103 memset(val, 0, sizeof(*val));
1104 ctl->get(ctl, val);
1105 cm->mixer_res_status[i] = val->value.integer.value[0];
1106 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1107 event = SNDRV_CTL_EVENT_MASK_INFO;
1108 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1109 ctl->put(ctl, val); /* toggle */
1110 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1111 }
1112 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1113 snd_ctl_notify(cm->card, event, &ctl->id);
1114 }
1115 }
1116 kfree(val);
1117 cm->mixer_insensitive = 1;
1118 }
1119 return 0;
1120 }
1121
1122
1123 /* restore the previously saved mixer status */
1124 static void restore_mixer_state(cmipci_t *cm)
1125 {
1126 if (cm->mixer_insensitive) {
1127 snd_ctl_elem_value_t *val;
1128 unsigned int i;
1129
1130 val = kmalloc(sizeof(*val), GFP_KERNEL);
1131 if (!val)
1132 return;
1133 cm->mixer_insensitive = 0; /* at first clear this;
1134 otherwise the changes will be ignored */
1135 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1136 snd_kcontrol_t *ctl = cm->mixer_res_ctl[i];
1137 if (ctl) {
1138 int event;
1139
1140 memset(val, 0, sizeof(*val));
1141 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1142 ctl->get(ctl, val);
1143 event = SNDRV_CTL_EVENT_MASK_INFO;
1144 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1145 val->value.integer.value[0] = cm->mixer_res_status[i];
1146 ctl->put(ctl, val);
1147 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1148 }
1149 snd_ctl_notify(cm->card, event, &ctl->id);
1150 }
1151 }
1152 kfree(val);
1153 }
1154 }
1155
1156 /* spinlock held! */
1157 static void setup_ac3(cmipci_t *cm, snd_pcm_substream_t *subs, int do_ac3, int rate)
1158 {
1159 if (do_ac3) {
1160 /* AC3EN for 037 */
1161 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1162 /* AC3EN for 039 */
1163 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1164
1165 if (cm->can_ac3_hw) {
1166 /* SPD24SEL for 037, 0x02 */
1167 /* SPD24SEL for 039, 0x20, but cannot be set */
1168 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1169 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1170 } else { /* can_ac3_sw */
1171 /* SPD32SEL for 037 & 039, 0x20 */
1172 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1173 /* set 176K sample rate to fix 033 HW bug */
1174 if (cm->chip_version == 33) {
1175 if (rate >= 48000) {
1176 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1177 } else {
1178 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1179 }
1180 }
1181 }
1182
1183 } else {
1184 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1185 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1186
1187 if (cm->can_ac3_hw) {
1188 /* chip model >= 37 */
1189 if (snd_pcm_format_width(subs->runtime->format) > 16) {
1190 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1191 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1192 } else {
1193 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1194 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1195 }
1196 } else {
1197 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1198 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1199 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1200 }
1201 }
1202 }
1203
1204 static int setup_spdif_playback(cmipci_t *cm, snd_pcm_substream_t *subs, int up, int do_ac3)
1205 {
1206 int rate, err;
1207
1208 rate = subs->runtime->rate;
1209
1210 if (up && do_ac3)
1211 if ((err = save_mixer_state(cm)) < 0)
1212 return err;
1213
1214 spin_lock_irq(&cm->reg_lock);
1215 cm->spdif_playback_avail = up;
1216 if (up) {
1217 /* they are controlled via "IEC958 Output Switch" */
1218 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1219 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1220 if (cm->spdif_playback_enabled)
1221 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1222 setup_ac3(cm, subs, do_ac3, rate);
1223
1224 if (rate == 48000)
1225 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1226 else
1227 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1228
1229 } else {
1230 /* they are controlled via "IEC958 Output Switch" */
1231 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1232 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1233 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1234 setup_ac3(cm, subs, 0, 0);
1235 }
1236 spin_unlock_irq(&cm->reg_lock);
1237 return 0;
1238 }
1239
1240
1241 /*
1242 * preparation
1243 */
1244
1245 /* playback - enable spdif only on the certain condition */
1246 static int snd_cmipci_playback_prepare(snd_pcm_substream_t *substream)
1247 {
1248 cmipci_t *cm = snd_pcm_substream_chip(substream);
1249 int rate = substream->runtime->rate;
1250 int err, do_spdif, do_ac3 = 0;
1251
1252 do_spdif = ((rate == 44100 || rate == 48000) &&
1253 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1254 substream->runtime->channels == 2);
1255 if (do_spdif && cm->can_ac3_hw)
1256 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1257 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1258 return err;
1259 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1260 }
1261
1262 /* playback (via device #2) - enable spdif always */
1263 static int snd_cmipci_playback_spdif_prepare(snd_pcm_substream_t *substream)
1264 {
1265 cmipci_t *cm = snd_pcm_substream_chip(substream);
1266 int err, do_ac3;
1267
1268 if (cm->can_ac3_hw)
1269 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1270 else
1271 do_ac3 = 1; /* doesn't matter */
1272 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1273 return err;
1274 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1275 }
1276
1277 static int snd_cmipci_playback_hw_free(snd_pcm_substream_t *substream)
1278 {
1279 cmipci_t *cm = snd_pcm_substream_chip(substream);
1280 setup_spdif_playback(cm, substream, 0, 0);
1281 restore_mixer_state(cm);
1282 return snd_cmipci_hw_free(substream);
1283 }
1284
1285 /* capture */
1286 static int snd_cmipci_capture_prepare(snd_pcm_substream_t *substream)
1287 {
1288 cmipci_t *cm = snd_pcm_substream_chip(substream);
1289 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1290 }
1291
1292 /* capture with spdif (via device #2) */
1293 static int snd_cmipci_capture_spdif_prepare(snd_pcm_substream_t *substream)
1294 {
1295 cmipci_t *cm = snd_pcm_substream_chip(substream);
1296
1297 spin_lock_irq(&cm->reg_lock);
1298 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1299 spin_unlock_irq(&cm->reg_lock);
1300
1301 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1302 }
1303
1304 static int snd_cmipci_capture_spdif_hw_free(snd_pcm_substream_t *subs)
1305 {
1306 cmipci_t *cm = snd_pcm_substream_chip(subs);
1307
1308 spin_lock_irq(&cm->reg_lock);
1309 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1310 spin_unlock_irq(&cm->reg_lock);
1311
1312 return snd_cmipci_hw_free(subs);
1313 }
1314
1315
1316 /*
1317 * interrupt handler
1318 */
1319 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1320 {
1321 cmipci_t *cm = dev_id;
1322 unsigned int status, mask = 0;
1323
1324 /* fastpath out, to ease interrupt sharing */
1325 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1326 if (!(status & CM_INTR))
1327 return IRQ_NONE;
1328
1329 /* acknowledge interrupt */
1330 spin_lock(&cm->reg_lock);
1331 if (status & CM_CHINT0)
1332 mask |= CM_CH0_INT_EN;
1333 if (status & CM_CHINT1)
1334 mask |= CM_CH1_INT_EN;
1335 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1336 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1337 spin_unlock(&cm->reg_lock);
1338
1339 if (cm->rmidi && (status & CM_UARTINT))
1340 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data, regs);
1341
1342 if (cm->pcm) {
1343 if ((status & CM_CHINT0) && cm->channel[0].running)
1344 snd_pcm_period_elapsed(cm->channel[0].substream);
1345 if ((status & CM_CHINT1) && cm->channel[1].running)
1346 snd_pcm_period_elapsed(cm->channel[1].substream);
1347 }
1348 return IRQ_HANDLED;
1349 }
1350
1351 /*
1352 * h/w infos
1353 */
1354
1355 /* playback on channel A */
1356 static snd_pcm_hardware_t snd_cmipci_playback =
1357 {
1358 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1359 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1360 SNDRV_PCM_INFO_MMAP_VALID),
1361 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1362 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1363 .rate_min = 5512,
1364 .rate_max = 48000,
1365 .channels_min = 1,
1366 .channels_max = 2,
1367 .buffer_bytes_max = (128*1024),
1368 .period_bytes_min = 64,
1369 .period_bytes_max = (128*1024),
1370 .periods_min = 2,
1371 .periods_max = 1024,
1372 .fifo_size = 0,
1373 };
1374
1375 /* capture on channel B */
1376 static snd_pcm_hardware_t snd_cmipci_capture =
1377 {
1378 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1379 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1380 SNDRV_PCM_INFO_MMAP_VALID),
1381 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1382 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1383 .rate_min = 5512,
1384 .rate_max = 48000,
1385 .channels_min = 1,
1386 .channels_max = 2,
1387 .buffer_bytes_max = (128*1024),
1388 .period_bytes_min = 64,
1389 .period_bytes_max = (128*1024),
1390 .periods_min = 2,
1391 .periods_max = 1024,
1392 .fifo_size = 0,
1393 };
1394
1395 /* playback on channel B - stereo 16bit only? */
1396 static snd_pcm_hardware_t snd_cmipci_playback2 =
1397 {
1398 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1399 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1400 SNDRV_PCM_INFO_MMAP_VALID),
1401 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1402 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1403 .rate_min = 5512,
1404 .rate_max = 48000,
1405 .channels_min = 2,
1406 .channels_max = 2,
1407 .buffer_bytes_max = (128*1024),
1408 .period_bytes_min = 64,
1409 .period_bytes_max = (128*1024),
1410 .periods_min = 2,
1411 .periods_max = 1024,
1412 .fifo_size = 0,
1413 };
1414
1415 /* spdif playback on channel A */
1416 static snd_pcm_hardware_t snd_cmipci_playback_spdif =
1417 {
1418 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1419 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1420 SNDRV_PCM_INFO_MMAP_VALID),
1421 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1422 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1423 .rate_min = 44100,
1424 .rate_max = 48000,
1425 .channels_min = 2,
1426 .channels_max = 2,
1427 .buffer_bytes_max = (128*1024),
1428 .period_bytes_min = 64,
1429 .period_bytes_max = (128*1024),
1430 .periods_min = 2,
1431 .periods_max = 1024,
1432 .fifo_size = 0,
1433 };
1434
1435 /* spdif playback on channel A (32bit, IEC958 subframes) */
1436 static snd_pcm_hardware_t snd_cmipci_playback_iec958_subframe =
1437 {
1438 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1439 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1440 SNDRV_PCM_INFO_MMAP_VALID),
1441 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1442 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1443 .rate_min = 44100,
1444 .rate_max = 48000,
1445 .channels_min = 2,
1446 .channels_max = 2,
1447 .buffer_bytes_max = (128*1024),
1448 .period_bytes_min = 64,
1449 .period_bytes_max = (128*1024),
1450 .periods_min = 2,
1451 .periods_max = 1024,
1452 .fifo_size = 0,
1453 };
1454
1455 /* spdif capture on channel B */
1456 static snd_pcm_hardware_t snd_cmipci_capture_spdif =
1457 {
1458 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1459 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1460 SNDRV_PCM_INFO_MMAP_VALID),
1461 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1462 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1463 .rate_min = 44100,
1464 .rate_max = 48000,
1465 .channels_min = 2,
1466 .channels_max = 2,
1467 .buffer_bytes_max = (128*1024),
1468 .period_bytes_min = 64,
1469 .period_bytes_max = (128*1024),
1470 .periods_min = 2,
1471 .periods_max = 1024,
1472 .fifo_size = 0,
1473 };
1474
1475 /*
1476 * check device open/close
1477 */
1478 static int open_device_check(cmipci_t *cm, int mode, snd_pcm_substream_t *subs)
1479 {
1480 int ch = mode & CM_OPEN_CH_MASK;
1481
1482 /* FIXME: a file should wait until the device becomes free
1483 * when it's opened on blocking mode. however, since the current
1484 * pcm framework doesn't pass file pointer before actually opened,
1485 * we can't know whether blocking mode or not in open callback..
1486 */
1487 down(&cm->open_mutex);
1488 if (cm->opened[ch]) {
1489 up(&cm->open_mutex);
1490 return -EBUSY;
1491 }
1492 cm->opened[ch] = mode;
1493 cm->channel[ch].substream = subs;
1494 if (! (mode & CM_OPEN_DAC)) {
1495 /* disable dual DAC mode */
1496 cm->channel[ch].is_dac = 0;
1497 spin_lock_irq(&cm->reg_lock);
1498 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1499 spin_unlock_irq(&cm->reg_lock);
1500 }
1501 up(&cm->open_mutex);
1502 return 0;
1503 }
1504
1505 static void close_device_check(cmipci_t *cm, int mode)
1506 {
1507 int ch = mode & CM_OPEN_CH_MASK;
1508
1509 down(&cm->open_mutex);
1510 if (cm->opened[ch] == mode) {
1511 if (cm->channel[ch].substream) {
1512 snd_cmipci_ch_reset(cm, ch);
1513 cm->channel[ch].running = 0;
1514 cm->channel[ch].substream = NULL;
1515 }
1516 cm->opened[ch] = 0;
1517 if (! cm->channel[ch].is_dac) {
1518 /* enable dual DAC mode again */
1519 cm->channel[ch].is_dac = 1;
1520 spin_lock_irq(&cm->reg_lock);
1521 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1522 spin_unlock_irq(&cm->reg_lock);
1523 }
1524 }
1525 up(&cm->open_mutex);
1526 }
1527
1528 /*
1529 */
1530
1531 static int snd_cmipci_playback_open(snd_pcm_substream_t *substream)
1532 {
1533 cmipci_t *cm = snd_pcm_substream_chip(substream);
1534 snd_pcm_runtime_t *runtime = substream->runtime;
1535 int err;
1536
1537 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1538 return err;
1539 runtime->hw = snd_cmipci_playback;
1540 runtime->hw.channels_max = cm->max_channels;
1541 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1542 cm->dig_pcm_status = cm->dig_status;
1543 return 0;
1544 }
1545
1546 static int snd_cmipci_capture_open(snd_pcm_substream_t *substream)
1547 {
1548 cmipci_t *cm = snd_pcm_substream_chip(substream);
1549 snd_pcm_runtime_t *runtime = substream->runtime;
1550 int err;
1551
1552 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1553 return err;
1554 runtime->hw = snd_cmipci_capture;
1555 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1556 runtime->hw.rate_min = 41000;
1557 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1558 }
1559 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1560 return 0;
1561 }
1562
1563 static int snd_cmipci_playback2_open(snd_pcm_substream_t *substream)
1564 {
1565 cmipci_t *cm = snd_pcm_substream_chip(substream);
1566 snd_pcm_runtime_t *runtime = substream->runtime;
1567 int err;
1568
1569 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1570 return err;
1571 runtime->hw = snd_cmipci_playback2;
1572 down(&cm->open_mutex);
1573 if (! cm->opened[CM_CH_PLAY]) {
1574 if (cm->can_multi_ch) {
1575 runtime->hw.channels_max = cm->max_channels;
1576 if (cm->max_channels == 4)
1577 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1578 else if (cm->max_channels == 6)
1579 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1580 else if (cm->max_channels == 8)
1581 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1582 }
1583 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1584 }
1585 up(&cm->open_mutex);
1586 return 0;
1587 }
1588
1589 static int snd_cmipci_playback_spdif_open(snd_pcm_substream_t *substream)
1590 {
1591 cmipci_t *cm = snd_pcm_substream_chip(substream);
1592 snd_pcm_runtime_t *runtime = substream->runtime;
1593 int err;
1594
1595 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1596 return err;
1597 if (cm->can_ac3_hw) {
1598 runtime->hw = snd_cmipci_playback_spdif;
1599 if (cm->chip_version >= 37)
1600 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1601 } else {
1602 runtime->hw = snd_cmipci_playback_iec958_subframe;
1603 }
1604 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1605 cm->dig_pcm_status = cm->dig_status;
1606 return 0;
1607 }
1608
1609 static int snd_cmipci_capture_spdif_open(snd_pcm_substream_t * substream)
1610 {
1611 cmipci_t *cm = snd_pcm_substream_chip(substream);
1612 snd_pcm_runtime_t *runtime = substream->runtime;
1613 int err;
1614
1615 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1616 return err;
1617 runtime->hw = snd_cmipci_capture_spdif;
1618 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1619 return 0;
1620 }
1621
1622
1623 /*
1624 */
1625
1626 static int snd_cmipci_playback_close(snd_pcm_substream_t * substream)
1627 {
1628 cmipci_t *cm = snd_pcm_substream_chip(substream);
1629 close_device_check(cm, CM_OPEN_PLAYBACK);
1630 return 0;
1631 }
1632
1633 static int snd_cmipci_capture_close(snd_pcm_substream_t * substream)
1634 {
1635 cmipci_t *cm = snd_pcm_substream_chip(substream);
1636 close_device_check(cm, CM_OPEN_CAPTURE);
1637 return 0;
1638 }
1639
1640 static int snd_cmipci_playback2_close(snd_pcm_substream_t * substream)
1641 {
1642 cmipci_t *cm = snd_pcm_substream_chip(substream);
1643 close_device_check(cm, CM_OPEN_PLAYBACK2);
1644 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1645 return 0;
1646 }
1647
1648 static int snd_cmipci_playback_spdif_close(snd_pcm_substream_t * substream)
1649 {
1650 cmipci_t *cm = snd_pcm_substream_chip(substream);
1651 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1652 return 0;
1653 }
1654
1655 static int snd_cmipci_capture_spdif_close(snd_pcm_substream_t * substream)
1656 {
1657 cmipci_t *cm = snd_pcm_substream_chip(substream);
1658 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1659 return 0;
1660 }
1661
1662
1663 /*
1664 */
1665
1666 static snd_pcm_ops_t snd_cmipci_playback_ops = {
1667 .open = snd_cmipci_playback_open,
1668 .close = snd_cmipci_playback_close,
1669 .ioctl = snd_pcm_lib_ioctl,
1670 .hw_params = snd_cmipci_hw_params,
1671 .hw_free = snd_cmipci_playback_hw_free,
1672 .prepare = snd_cmipci_playback_prepare,
1673 .trigger = snd_cmipci_playback_trigger,
1674 .pointer = snd_cmipci_playback_pointer,
1675 };
1676
1677 static snd_pcm_ops_t snd_cmipci_capture_ops = {
1678 .open = snd_cmipci_capture_open,
1679 .close = snd_cmipci_capture_close,
1680 .ioctl = snd_pcm_lib_ioctl,
1681 .hw_params = snd_cmipci_hw_params,
1682 .hw_free = snd_cmipci_hw_free,
1683 .prepare = snd_cmipci_capture_prepare,
1684 .trigger = snd_cmipci_capture_trigger,
1685 .pointer = snd_cmipci_capture_pointer,
1686 };
1687
1688 static snd_pcm_ops_t snd_cmipci_playback2_ops = {
1689 .open = snd_cmipci_playback2_open,
1690 .close = snd_cmipci_playback2_close,
1691 .ioctl = snd_pcm_lib_ioctl,
1692 .hw_params = snd_cmipci_playback2_hw_params,
1693 .hw_free = snd_cmipci_hw_free,
1694 .prepare = snd_cmipci_capture_prepare, /* channel B */
1695 .trigger = snd_cmipci_capture_trigger, /* channel B */
1696 .pointer = snd_cmipci_capture_pointer, /* channel B */
1697 };
1698
1699 static snd_pcm_ops_t snd_cmipci_playback_spdif_ops = {
1700 .open = snd_cmipci_playback_spdif_open,
1701 .close = snd_cmipci_playback_spdif_close,
1702 .ioctl = snd_pcm_lib_ioctl,
1703 .hw_params = snd_cmipci_hw_params,
1704 .hw_free = snd_cmipci_playback_hw_free,
1705 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1706 .trigger = snd_cmipci_playback_trigger,
1707 .pointer = snd_cmipci_playback_pointer,
1708 };
1709
1710 static snd_pcm_ops_t snd_cmipci_capture_spdif_ops = {
1711 .open = snd_cmipci_capture_spdif_open,
1712 .close = snd_cmipci_capture_spdif_close,
1713 .ioctl = snd_pcm_lib_ioctl,
1714 .hw_params = snd_cmipci_hw_params,
1715 .hw_free = snd_cmipci_capture_spdif_hw_free,
1716 .prepare = snd_cmipci_capture_spdif_prepare,
1717 .trigger = snd_cmipci_capture_trigger,
1718 .pointer = snd_cmipci_capture_pointer,
1719 };
1720
1721
1722 /*
1723 */
1724
1725 static void snd_cmipci_pcm_free(snd_pcm_t *pcm)
1726 {
1727 snd_pcm_lib_preallocate_free_for_all(pcm);
1728 }
1729
1730 static int __devinit snd_cmipci_pcm_new(cmipci_t *cm, int device)
1731 {
1732 snd_pcm_t *pcm;
1733 int err;
1734
1735 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1736 if (err < 0)
1737 return err;
1738
1739 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1740 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1741
1742 pcm->private_data = cm;
1743 pcm->private_free = snd_cmipci_pcm_free;
1744 pcm->info_flags = 0;
1745 strcpy(pcm->name, "C-Media PCI DAC/ADC");
1746 cm->pcm = pcm;
1747
1748 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1749 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1750
1751 return 0;
1752 }
1753
1754 static int __devinit snd_cmipci_pcm2_new(cmipci_t *cm, int device)
1755 {
1756 snd_pcm_t *pcm;
1757 int err;
1758
1759 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1760 if (err < 0)
1761 return err;
1762
1763 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1764
1765 pcm->private_data = cm;
1766 pcm->private_free = snd_cmipci_pcm_free;
1767 pcm->info_flags = 0;
1768 strcpy(pcm->name, "C-Media PCI 2nd DAC");
1769 cm->pcm2 = pcm;
1770
1771 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1772 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1773
1774 return 0;
1775 }
1776
1777 static int __devinit snd_cmipci_pcm_spdif_new(cmipci_t *cm, int device)
1778 {
1779 snd_pcm_t *pcm;
1780 int err;
1781
1782 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1783 if (err < 0)
1784 return err;
1785
1786 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1787 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1788
1789 pcm->private_data = cm;
1790 pcm->private_free = snd_cmipci_pcm_free;
1791 pcm->info_flags = 0;
1792 strcpy(pcm->name, "C-Media PCI IEC958");
1793 cm->pcm_spdif = pcm;
1794
1795 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1796 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1797
1798 return 0;
1799 }
1800
1801 /*
1802 * mixer interface:
1803 * - CM8338/8738 has a compatible mixer interface with SB16, but
1804 * lack of some elements like tone control, i/o gain and AGC.
1805 * - Access to native registers:
1806 * - A 3D switch
1807 * - Output mute switches
1808 */
1809
1810 static void snd_cmipci_mixer_write(cmipci_t *s, unsigned char idx, unsigned char data)
1811 {
1812 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1813 outb(data, s->iobase + CM_REG_SB16_DATA);
1814 }
1815
1816 static unsigned char snd_cmipci_mixer_read(cmipci_t *s, unsigned char idx)
1817 {
1818 unsigned char v;
1819
1820 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1821 v = inb(s->iobase + CM_REG_SB16_DATA);
1822 return v;
1823 }
1824
1825 /*
1826 * general mixer element
1827 */
1828 typedef struct cmipci_sb_reg {
1829 unsigned int left_reg, right_reg;
1830 unsigned int left_shift, right_shift;
1831 unsigned int mask;
1832 unsigned int invert: 1;
1833 unsigned int stereo: 1;
1834 } cmipci_sb_reg_t;
1835
1836 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1837 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1838
1839 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1840 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1841 .info = snd_cmipci_info_volume, \
1842 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1843 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1844 }
1845
1846 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1847 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1848 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1849 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1850
1851 static void cmipci_sb_reg_decode(cmipci_sb_reg_t *r, unsigned long val)
1852 {
1853 r->left_reg = val & 0xff;
1854 r->right_reg = (val >> 8) & 0xff;
1855 r->left_shift = (val >> 16) & 0x07;
1856 r->right_shift = (val >> 19) & 0x07;
1857 r->invert = (val >> 22) & 1;
1858 r->stereo = (val >> 23) & 1;
1859 r->mask = (val >> 24) & 0xff;
1860 }
1861
1862 static int snd_cmipci_info_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1863 {
1864 cmipci_sb_reg_t reg;
1865
1866 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1867 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1868 uinfo->count = reg.stereo + 1;
1869 uinfo->value.integer.min = 0;
1870 uinfo->value.integer.max = reg.mask;
1871 return 0;
1872 }
1873
1874 static int snd_cmipci_get_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1875 {
1876 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1877 cmipci_sb_reg_t reg;
1878 int val;
1879
1880 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1881 spin_lock_irq(&cm->reg_lock);
1882 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
1883 if (reg.invert)
1884 val = reg.mask - val;
1885 ucontrol->value.integer.value[0] = val;
1886 if (reg.stereo) {
1887 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
1888 if (reg.invert)
1889 val = reg.mask - val;
1890 ucontrol->value.integer.value[1] = val;
1891 }
1892 spin_unlock_irq(&cm->reg_lock);
1893 return 0;
1894 }
1895
1896 static int snd_cmipci_put_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1897 {
1898 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1899 cmipci_sb_reg_t reg;
1900 int change;
1901 int left, right, oleft, oright;
1902
1903 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1904 left = ucontrol->value.integer.value[0] & reg.mask;
1905 if (reg.invert)
1906 left = reg.mask - left;
1907 left <<= reg.left_shift;
1908 if (reg.stereo) {
1909 right = ucontrol->value.integer.value[1] & reg.mask;
1910 if (reg.invert)
1911 right = reg.mask - right;
1912 right <<= reg.right_shift;
1913 } else
1914 right = 0;
1915 spin_lock_irq(&cm->reg_lock);
1916 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
1917 left |= oleft & ~(reg.mask << reg.left_shift);
1918 change = left != oleft;
1919 if (reg.stereo) {
1920 if (reg.left_reg != reg.right_reg) {
1921 snd_cmipci_mixer_write(cm, reg.left_reg, left);
1922 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
1923 } else
1924 oright = left;
1925 right |= oright & ~(reg.mask << reg.right_shift);
1926 change |= right != oright;
1927 snd_cmipci_mixer_write(cm, reg.right_reg, right);
1928 } else
1929 snd_cmipci_mixer_write(cm, reg.left_reg, left);
1930 spin_unlock_irq(&cm->reg_lock);
1931 return change;
1932 }
1933
1934 /*
1935 * input route (left,right) -> (left,right)
1936 */
1937 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
1938 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1939 .info = snd_cmipci_info_input_sw, \
1940 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
1941 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
1942 }
1943
1944 static int snd_cmipci_info_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1945 {
1946 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1947 uinfo->count = 4;
1948 uinfo->value.integer.min = 0;
1949 uinfo->value.integer.max = 1;
1950 return 0;
1951 }
1952
1953 static int snd_cmipci_get_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1954 {
1955 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1956 cmipci_sb_reg_t reg;
1957 int val1, val2;
1958
1959 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1960 spin_lock_irq(&cm->reg_lock);
1961 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1962 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1963 spin_unlock_irq(&cm->reg_lock);
1964 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
1965 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
1966 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
1967 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
1968 return 0;
1969 }
1970
1971 static int snd_cmipci_put_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1972 {
1973 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
1974 cmipci_sb_reg_t reg;
1975 int change;
1976 int val1, val2, oval1, oval2;
1977
1978 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1979 spin_lock_irq(&cm->reg_lock);
1980 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
1981 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
1982 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1983 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
1984 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
1985 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
1986 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
1987 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
1988 change = val1 != oval1 || val2 != oval2;
1989 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
1990 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
1991 spin_unlock_irq(&cm->reg_lock);
1992 return change;
1993 }
1994
1995 /*
1996 * native mixer switches/volumes
1997 */
1998
1999 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2000 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2001 .info = snd_cmipci_info_native_mixer, \
2002 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2003 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2004 }
2005
2006 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2007 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2008 .info = snd_cmipci_info_native_mixer, \
2009 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2010 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2011 }
2012
2013 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2014 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2015 .info = snd_cmipci_info_native_mixer, \
2016 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2017 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2018 }
2019
2020 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2021 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2022 .info = snd_cmipci_info_native_mixer, \
2023 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2024 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2025 }
2026
2027 static int snd_cmipci_info_native_mixer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
2028 {
2029 cmipci_sb_reg_t reg;
2030
2031 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2032 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2033 uinfo->count = reg.stereo + 1;
2034 uinfo->value.integer.min = 0;
2035 uinfo->value.integer.max = reg.mask;
2036 return 0;
2037
2038 }
2039
2040 static int snd_cmipci_get_native_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2041 {
2042 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2043 cmipci_sb_reg_t reg;
2044 unsigned char oreg, val;
2045
2046 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2047 spin_lock_irq(&cm->reg_lock);
2048 oreg = inb(cm->iobase + reg.left_reg);
2049 val = (oreg >> reg.left_shift) & reg.mask;
2050 if (reg.invert)
2051 val = reg.mask - val;
2052 ucontrol->value.integer.value[0] = val;
2053 if (reg.stereo) {
2054 val = (oreg >> reg.right_shift) & reg.mask;
2055 if (reg.invert)
2056 val = reg.mask - val;
2057 ucontrol->value.integer.value[1] = val;
2058 }
2059 spin_unlock_irq(&cm->reg_lock);
2060 return 0;
2061 }
2062
2063 static int snd_cmipci_put_native_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2064 {
2065 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2066 cmipci_sb_reg_t reg;
2067 unsigned char oreg, nreg, val;
2068
2069 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2070 spin_lock_irq(&cm->reg_lock);
2071 oreg = inb(cm->iobase + reg.left_reg);
2072 val = ucontrol->value.integer.value[0] & reg.mask;
2073 if (reg.invert)
2074 val = reg.mask - val;
2075 nreg = oreg & ~(reg.mask << reg.left_shift);
2076 nreg |= (val << reg.left_shift);
2077 if (reg.stereo) {
2078 val = ucontrol->value.integer.value[1] & reg.mask;
2079 if (reg.invert)
2080 val = reg.mask - val;
2081 nreg &= ~(reg.mask << reg.right_shift);
2082 nreg |= (val << reg.right_shift);
2083 }
2084 outb(nreg, cm->iobase + reg.left_reg);
2085 spin_unlock_irq(&cm->reg_lock);
2086 return (nreg != oreg);
2087 }
2088
2089 /*
2090 * special case - check mixer sensitivity
2091 */
2092 static int snd_cmipci_get_native_mixer_sensitive(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2093 {
2094 //cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2095 return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2096 }
2097
2098 static int snd_cmipci_put_native_mixer_sensitive(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2099 {
2100 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2101 if (cm->mixer_insensitive) {
2102 /* ignored */
2103 return 0;
2104 }
2105 return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2106 }
2107
2108
2109 static snd_kcontrol_new_t snd_cmipci_mixers[] __devinitdata = {
2110 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2111 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2112 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2113 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2114 { /* switch with sensitivity */
2115 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2116 .name = "PCM Playback Switch",
2117 .info = snd_cmipci_info_native_mixer,
2118 .get = snd_cmipci_get_native_mixer_sensitive,
2119 .put = snd_cmipci_put_native_mixer_sensitive,
2120 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2121 },
2122 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2123 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2124 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2125 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2126 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2127 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2128 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2129 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2130 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2131 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2132 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2133 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2134 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2135 CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2136 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2137 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2138 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2139 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2140 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2141 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2142 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2143 CMIPCI_DOUBLE("PC Speaker Playnack Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2144 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2145 };
2146
2147 /*
2148 * other switches
2149 */
2150
2151 typedef struct snd_cmipci_switch_args {
2152 int reg; /* register index */
2153 unsigned int mask; /* mask bits */
2154 unsigned int mask_on; /* mask bits to turn on */
2155 unsigned int is_byte: 1; /* byte access? */
2156 unsigned int ac3_sensitive: 1; /* access forbidden during non-audio operation? */
2157 } snd_cmipci_switch_args_t;
2158
2159 static int snd_cmipci_uswitch_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
2160 {
2161 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2162 uinfo->count = 1;
2163 uinfo->value.integer.min = 0;
2164 uinfo->value.integer.max = 1;
2165 return 0;
2166 }
2167
2168 static int _snd_cmipci_uswitch_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol, snd_cmipci_switch_args_t *args)
2169 {
2170 unsigned int val;
2171 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2172
2173 spin_lock_irq(&cm->reg_lock);
2174 if (args->ac3_sensitive && cm->mixer_insensitive) {
2175 ucontrol->value.integer.value[0] = 0;
2176 spin_unlock_irq(&cm->reg_lock);
2177 return 0;
2178 }
2179 if (args->is_byte)
2180 val = inb(cm->iobase + args->reg);
2181 else
2182 val = snd_cmipci_read(cm, args->reg);
2183 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2184 spin_unlock_irq(&cm->reg_lock);
2185 return 0;
2186 }
2187
2188 static int snd_cmipci_uswitch_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2189 {
2190 snd_cmipci_switch_args_t *args = (snd_cmipci_switch_args_t*)kcontrol->private_value;
2191 snd_assert(args != NULL, return -EINVAL);
2192 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2193 }
2194
2195 static int _snd_cmipci_uswitch_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol, snd_cmipci_switch_args_t *args)
2196 {
2197 unsigned int val;
2198 int change;
2199 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2200
2201 spin_lock_irq(&cm->reg_lock);
2202 if (args->ac3_sensitive && cm->mixer_insensitive) {
2203 /* ignored */
2204 spin_unlock_irq(&cm->reg_lock);
2205 return 0;
2206 }
2207 if (args->is_byte)
2208 val = inb(cm->iobase + args->reg);
2209 else
2210 val = snd_cmipci_read(cm, args->reg);
2211 change = (val & args->mask) != (ucontrol->value.integer.value[0] ? args->mask : 0);
2212 if (change) {
2213 val &= ~args->mask;
2214 if (ucontrol->value.integer.value[0])
2215 val |= args->mask_on;
2216 else
2217 val |= (args->mask & ~args->mask_on);
2218 if (args->is_byte)
2219 outb((unsigned char)val, cm->iobase + args->reg);
2220 else
2221 snd_cmipci_write(cm, args->reg, val);
2222 }
2223 spin_unlock_irq(&cm->reg_lock);
2224 return change;
2225 }
2226
2227 static int snd_cmipci_uswitch_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2228 {
2229 snd_cmipci_switch_args_t *args = (snd_cmipci_switch_args_t*)kcontrol->private_value;
2230 snd_assert(args != NULL, return -EINVAL);
2231 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2232 }
2233
2234 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2235 static snd_cmipci_switch_args_t cmipci_switch_arg_##sname = { \
2236 .reg = xreg, \
2237 .mask = xmask, \
2238 .mask_on = xmask_on, \
2239 .is_byte = xis_byte, \
2240 .ac3_sensitive = xac3, \
2241 }
2242
2243 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2244 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2245
2246 #if 0 /* these will be controlled in pcm device */
2247 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2248 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2249 #endif
2250 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2251 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2252 DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2253 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2254 DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2255 DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2256 DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2257 DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2258 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2259 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2260 DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2261 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2262 DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2263 DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2264 #if CM_CH_PLAY == 1
2265 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2266 #else
2267 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2268 #endif
2269 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2270 // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_SPK4, 1, 0);
2271 // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS, 0, 0);
2272 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2273 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2274
2275 #define DEFINE_SWITCH(sname, stype, sarg) \
2276 { .name = sname, \
2277 .iface = stype, \
2278 .info = snd_cmipci_uswitch_info, \
2279 .get = snd_cmipci_uswitch_get, \
2280 .put = snd_cmipci_uswitch_put, \
2281 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2282 }
2283
2284 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2285 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2286
2287
2288 /*
2289 * callbacks for spdif output switch
2290 * needs toggle two registers..
2291 */
2292 static int snd_cmipci_spdout_enable_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2293 {
2294 int changed;
2295 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2296 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2297 return changed;
2298 }
2299
2300 static int snd_cmipci_spdout_enable_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2301 {
2302 cmipci_t *chip = snd_kcontrol_chip(kcontrol);
2303 int changed;
2304 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2305 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2306 if (changed) {
2307 if (ucontrol->value.integer.value[0]) {
2308 if (chip->spdif_playback_avail)
2309 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2310 } else {
2311 if (chip->spdif_playback_avail)
2312 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2313 }
2314 }
2315 chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2316 return changed;
2317 }
2318
2319
2320 static int snd_cmipci_line_in_mode_info(snd_kcontrol_t *kcontrol,
2321 snd_ctl_elem_info_t *uinfo)
2322 {
2323 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2324 static char *texts[3] = { "Line-In", "Rear Output", "Bass Output" };
2325 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2326 uinfo->count = 1;
2327 uinfo->value.enumerated.items = cm->chip_version >= 39 ? 3 : 2;
2328 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2329 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2330 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2331 return 0;
2332 }
2333
2334 static inline unsigned int get_line_in_mode(cmipci_t *cm)
2335 {
2336 unsigned int val;
2337 if (cm->chip_version >= 39) {
2338 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2339 if (val & CM_LINE_AS_BASS)
2340 return 2;
2341 }
2342 val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2343 if (val & CM_SPK4)
2344 return 1;
2345 return 0;
2346 }
2347
2348 static int snd_cmipci_line_in_mode_get(snd_kcontrol_t *kcontrol,
2349 snd_ctl_elem_value_t *ucontrol)
2350 {
2351 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2352
2353 spin_lock_irq(&cm->reg_lock);
2354 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2355 spin_unlock_irq(&cm->reg_lock);
2356 return 0;
2357 }
2358
2359 static int snd_cmipci_line_in_mode_put(snd_kcontrol_t *kcontrol,
2360 snd_ctl_elem_value_t *ucontrol)
2361 {
2362 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2363 int change;
2364
2365 spin_lock_irq(&cm->reg_lock);
2366 if (ucontrol->value.enumerated.item[0] == 2)
2367 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS);
2368 else
2369 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS);
2370 if (ucontrol->value.enumerated.item[0] == 1)
2371 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_SPK4);
2372 else
2373 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_SPK4);
2374 spin_unlock_irq(&cm->reg_lock);
2375 return change;
2376 }
2377
2378 static int snd_cmipci_mic_in_mode_info(snd_kcontrol_t *kcontrol,
2379 snd_ctl_elem_info_t *uinfo)
2380 {
2381 static char *texts[2] = { "Mic-In", "Center/LFE Output" };
2382 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2383 uinfo->count = 1;
2384 uinfo->value.enumerated.items = 2;
2385 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2386 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2387 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2388 return 0;
2389 }
2390
2391 static int snd_cmipci_mic_in_mode_get(snd_kcontrol_t *kcontrol,
2392 snd_ctl_elem_value_t *ucontrol)
2393 {
2394 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2395 /* same bit as spdi_phase */
2396 spin_lock_irq(&cm->reg_lock);
2397 ucontrol->value.enumerated.item[0] =
2398 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2399 spin_unlock_irq(&cm->reg_lock);
2400 return 0;
2401 }
2402
2403 static int snd_cmipci_mic_in_mode_put(snd_kcontrol_t *kcontrol,
2404 snd_ctl_elem_value_t *ucontrol)
2405 {
2406 cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2407 int change;
2408
2409 spin_lock_irq(&cm->reg_lock);
2410 if (ucontrol->value.enumerated.item[0])
2411 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2412 else
2413 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2414 spin_unlock_irq(&cm->reg_lock);
2415 return change;
2416 }
2417
2418 /* both for CM8338/8738 */
2419 static snd_kcontrol_new_t snd_cmipci_mixer_switches[] __devinitdata = {
2420 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2421 {
2422 .name = "Line-In Mode",
2423 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2424 .info = snd_cmipci_line_in_mode_info,
2425 .get = snd_cmipci_line_in_mode_get,
2426 .put = snd_cmipci_line_in_mode_put,
2427 },
2428 };
2429
2430 /* for non-multichannel chips */
2431 static snd_kcontrol_new_t snd_cmipci_nomulti_switch __devinitdata =
2432 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2433
2434 /* only for CM8738 */
2435 static snd_kcontrol_new_t snd_cmipci_8738_mixer_switches[] __devinitdata = {
2436 #if 0 /* controlled in pcm device */
2437 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2438 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2439 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2440 #endif
2441 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2442 { .name = "IEC958 Output Switch",
2443 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2444 .info = snd_cmipci_uswitch_info,
2445 .get = snd_cmipci_spdout_enable_get,
2446 .put = snd_cmipci_spdout_enable_put,
2447 },
2448 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2449 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2450 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2451 // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2452 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2453 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2454 };
2455
2456 /* only for model 033/037 */
2457 static snd_kcontrol_new_t snd_cmipci_old_mixer_switches[] __devinitdata = {
2458 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2459 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2460 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2461 };
2462
2463 /* only for model 039 or later */
2464 static snd_kcontrol_new_t snd_cmipci_extra_mixer_switches[] __devinitdata = {
2465 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2466 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2467 {
2468 .name = "Mic-In Mode",
2469 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2470 .info = snd_cmipci_mic_in_mode_info,
2471 .get = snd_cmipci_mic_in_mode_get,
2472 .put = snd_cmipci_mic_in_mode_put,
2473 }
2474 };
2475
2476 /* card control switches */
2477 static snd_kcontrol_new_t snd_cmipci_control_switches[] __devinitdata = {
2478 // DEFINE_CARD_SWITCH("Joystick", joystick), /* now module option */
2479 DEFINE_CARD_SWITCH("Modem", modem),
2480 };
2481
2482
2483 static int __devinit snd_cmipci_mixer_new(cmipci_t *cm, int pcm_spdif_device)
2484 {
2485 snd_card_t *card;
2486 snd_kcontrol_new_t *sw;
2487 snd_kcontrol_t *kctl;
2488 unsigned int idx;
2489 int err;
2490
2491 snd_assert(cm != NULL && cm->card != NULL, return -EINVAL);
2492
2493 card = cm->card;
2494
2495 strcpy(card->mixername, "CMedia PCI");
2496
2497 spin_lock_irq(&cm->reg_lock);
2498 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2499 spin_unlock_irq(&cm->reg_lock);
2500
2501 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2502 if (cm->chip_version == 68) { // 8768 has no PCM volume
2503 if (!strcmp(snd_cmipci_mixers[idx].name,
2504 "PCM Playback Volume"))
2505 continue;
2506 }
2507 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2508 return err;
2509 }
2510
2511 /* mixer switches */
2512 sw = snd_cmipci_mixer_switches;
2513 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2514 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2515 if (err < 0)
2516 return err;
2517 }
2518 if (! cm->can_multi_ch) {
2519 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2520 if (err < 0)
2521 return err;
2522 }
2523 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2524 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2525 sw = snd_cmipci_8738_mixer_switches;
2526 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2527 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2528 if (err < 0)
2529 return err;
2530 }
2531 if (cm->can_ac3_hw) {
2532 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2533 return err;
2534 kctl->id.device = pcm_spdif_device;
2535 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2536 return err;
2537 kctl->id.device = pcm_spdif_device;
2538 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2539 return err;
2540 kctl->id.device = pcm_spdif_device;
2541 }
2542 if (cm->chip_version <= 37) {
2543 sw = snd_cmipci_old_mixer_switches;
2544 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2545 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2546 if (err < 0)
2547 return err;
2548 }
2549 }
2550 }
2551 if (cm->chip_version >= 39) {
2552 sw = snd_cmipci_extra_mixer_switches;
2553 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2554 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2555 if (err < 0)
2556 return err;
2557 }
2558 }
2559
2560 /* card switches */
2561 sw = snd_cmipci_control_switches;
2562 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_control_switches); idx++, sw++) {
2563 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2564 if (err < 0)
2565 return err;
2566 }
2567
2568 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2569 snd_ctl_elem_id_t id;
2570 snd_kcontrol_t *ctl;
2571 memset(&id, 0, sizeof(id));
2572 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2573 strcpy(id.name, cm_saved_mixer[idx].name);
2574 if ((ctl = snd_ctl_find_id(cm->card, &id)) != NULL)
2575 cm->mixer_res_ctl[idx] = ctl;
2576 }
2577
2578 return 0;
2579 }
2580
2581
2582 /*
2583 * proc interface
2584 */
2585
2586 #ifdef CONFIG_PROC_FS
2587 static void snd_cmipci_proc_read(snd_info_entry_t *entry,
2588 snd_info_buffer_t *buffer)
2589 {
2590 cmipci_t *cm = entry->private_data;
2591 int i;
2592
2593 snd_iprintf(buffer, "%s\n\n", cm->card->longname);
2594 for (i = 0; i < 0x40; i++) {
2595 int v = inb(cm->iobase + i);
2596 if (i % 4 == 0)
2597 snd_iprintf(buffer, "%02x: ", i);
2598 snd_iprintf(buffer, "%02x", v);
2599 if (i % 4 == 3)
2600 snd_iprintf(buffer, "\n");
2601 else
2602 snd_iprintf(buffer, " ");
2603 }
2604 }
2605
2606 static void __devinit snd_cmipci_proc_init(cmipci_t *cm)
2607 {
2608 snd_info_entry_t *entry;
2609
2610 if (! snd_card_proc_new(cm->card, "cmipci", &entry))
2611 snd_info_set_text_ops(entry, cm, 1024, snd_cmipci_proc_read);
2612 }
2613 #else /* !CONFIG_PROC_FS */
2614 static inline void snd_cmipci_proc_init(cmipci_t *cm) {}
2615 #endif
2616
2617
2618 static struct pci_device_id snd_cmipci_ids[] = {
2619 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2620 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2621 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2622 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2623 {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2624 {0,},
2625 };
2626
2627
2628 /*
2629 * check chip version and capabilities
2630 * driver name is modified according to the chip model
2631 */
2632 static void __devinit query_chip(cmipci_t *cm)
2633 {
2634 unsigned int detect;
2635
2636 /* check reg 0Ch, bit 24-31 */
2637 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2638 if (! detect) {
2639 /* check reg 08h, bit 24-28 */
2640 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2641 if (! detect) {
2642 cm->chip_version = 33;
2643 cm->max_channels = 2;
2644 if (cm->do_soft_ac3)
2645 cm->can_ac3_sw = 1;
2646 else
2647 cm->can_ac3_hw = 1;
2648 cm->has_dual_dac = 1;
2649 } else {
2650 cm->chip_version = 37;
2651 cm->max_channels = 2;
2652 cm->can_ac3_hw = 1;
2653 cm->has_dual_dac = 1;
2654 }
2655 } else {
2656 /* check reg 0Ch, bit 26 */
2657 if (detect & CM_CHIP_8768) {
2658 cm->chip_version = 68;
2659 cm->max_channels = 8;
2660 cm->can_ac3_hw = 1;
2661 cm->has_dual_dac = 1;
2662 cm->can_multi_ch = 1;
2663 } else if (detect & CM_CHIP_055) {
2664 cm->chip_version = 55;
2665 cm->max_channels = 6;
2666 cm->can_ac3_hw = 1;
2667 cm->has_dual_dac = 1;
2668 cm->can_multi_ch = 1;
2669 } else if (detect & CM_CHIP_039) {
2670 cm->chip_version = 39;
2671 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2672 cm->max_channels = 6;
2673 else
2674 cm->max_channels = 4;
2675 cm->can_ac3_hw = 1;
2676 cm->has_dual_dac = 1;
2677 cm->can_multi_ch = 1;
2678 } else {
2679 printk(KERN_ERR "chip %x version not supported\n", detect);
2680 }
2681 }
2682 }
2683
2684 #ifdef SUPPORT_JOYSTICK
2685 static int __devinit snd_cmipci_create_gameport(cmipci_t *cm, int dev)
2686 {
2687 static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2688 struct gameport *gp;
2689 struct resource *r = NULL;
2690 int i, io_port = 0;
2691
2692 if (joystick_port[dev] == 0)
2693 return -ENODEV;
2694
2695 if (joystick_port[dev] == 1) { /* auto-detect */
2696 for (i = 0; ports[i]; i++) {
2697 io_port = ports[i];
2698 r = request_region(io_port, 1, "CMIPCI gameport");
2699 if (r)
2700 break;
2701 }
2702 } else {
2703 io_port = joystick_port[dev];
2704 r = request_region(io_port, 1, "CMIPCI gameport");
2705 }
2706
2707 if (!r) {
2708 printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n");
2709 return -EBUSY;
2710 }
2711
2712 cm->gameport = gp = gameport_allocate_port();
2713 if (!gp) {
2714 printk(KERN_ERR "cmipci: cannot allocate memory for gameport\n");
2715 release_resource(r);
2716 kfree_nocheck(r);
2717 return -ENOMEM;
2718 }
2719 gameport_set_name(gp, "C-Media Gameport");
2720 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2721 gameport_set_dev_parent(gp, &cm->pci->dev);
2722 gp->io = io_port;
2723 gameport_set_port_data(gp, r);
2724
2725 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2726
2727 gameport_register_port(cm->gameport);
2728
2729 return 0;
2730 }
2731
2732 static void snd_cmipci_free_gameport(cmipci_t *cm)
2733 {
2734 if (cm->gameport) {
2735 struct resource *r = gameport_get_port_data(cm->gameport);
2736
2737 gameport_unregister_port(cm->gameport);
2738 cm->gameport = NULL;
2739
2740 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2741 release_resource(r);
2742 kfree_nocheck(r);
2743 }
2744 }
2745 #else
2746 static inline int snd_cmipci_create_gameport(cmipci_t *cm, int dev) { return -ENOSYS; }
2747 static inline void snd_cmipci_free_gameport(cmipci_t *cm) { }
2748 #endif
2749
2750 static int snd_cmipci_free(cmipci_t *cm)
2751 {
2752 if (cm->irq >= 0) {
2753 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2754 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2755 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2756 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2757 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2758 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2759 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2760
2761 /* reset mixer */
2762 snd_cmipci_mixer_write(cm, 0, 0);
2763
2764 synchronize_irq(cm->irq);
2765
2766 free_irq(cm->irq, (void *)cm);
2767 }
2768
2769 snd_cmipci_free_gameport(cm);
2770 pci_release_regions(cm->pci);
2771 pci_disable_device(cm->pci);
2772 kfree(cm);
2773 return 0;
2774 }
2775
2776 static int snd_cmipci_dev_free(snd_device_t *device)
2777 {
2778 cmipci_t *cm = device->device_data;
2779 return snd_cmipci_free(cm);
2780 }
2781
2782 static int __devinit snd_cmipci_create(snd_card_t *card, struct pci_dev *pci,
2783 int dev, cmipci_t **rcmipci)
2784 {
2785 cmipci_t *cm;
2786 int err;
2787 static snd_device_ops_t ops = {
2788 .dev_free = snd_cmipci_dev_free,
2789 };
2790 unsigned int val = 0;
2791 long iomidi = mpu_port[dev];
2792 long iosynth = fm_port[dev];
2793 int pcm_index, pcm_spdif_index;
2794 static struct pci_device_id intel_82437vx[] = {
2795 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
2796 { },
2797 };
2798
2799 *rcmipci = NULL;
2800
2801 if ((err = pci_enable_device(pci)) < 0)
2802 return err;
2803
2804 cm = kcalloc(1, sizeof(*cm), GFP_KERNEL);
2805 if (cm == NULL) {
2806 pci_disable_device(pci);
2807 return -ENOMEM;
2808 }
2809
2810 spin_lock_init(&cm->reg_lock);
2811 init_MUTEX(&cm->open_mutex);
2812 cm->device = pci->device;
2813 cm->card = card;
2814 cm->pci = pci;
2815 cm->irq = -1;
2816 cm->channel[0].ch = 0;
2817 cm->channel[1].ch = 1;
2818 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
2819
2820 if ((err = pci_request_regions(pci, card->driver)) < 0) {
2821 kfree(cm);
2822 pci_disable_device(pci);
2823 return err;
2824 }
2825 cm->iobase = pci_resource_start(pci, 0);
2826
2827 if (request_irq(pci->irq, snd_cmipci_interrupt, SA_INTERRUPT|SA_SHIRQ, card->driver, (void *)cm)) {
2828 snd_printk("unable to grab IRQ %d\n", pci->irq);
2829 snd_cmipci_free(cm);
2830 return -EBUSY;
2831 }
2832 cm->irq = pci->irq;
2833
2834 pci_set_master(cm->pci);
2835
2836 /*
2837 * check chip version, max channels and capabilities
2838 */
2839
2840 cm->chip_version = 0;
2841 cm->max_channels = 2;
2842 cm->do_soft_ac3 = soft_ac3[dev];
2843
2844 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
2845 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
2846 query_chip(cm);
2847 /* added -MCx suffix for chip supporting multi-channels */
2848 if (cm->can_multi_ch)
2849 sprintf(cm->card->driver + strlen(cm->card->driver),
2850 "-MC%d", cm->max_channels);
2851 else if (cm->can_ac3_sw)
2852 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
2853
2854 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2855 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2856
2857 #if CM_CH_PLAY == 1
2858 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
2859 #else
2860 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
2861 #endif
2862
2863 /* initialize codec registers */
2864 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2865 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2866 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2867 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2868 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2869
2870 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
2871 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
2872 #if CM_CH_PLAY == 1
2873 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2874 #else
2875 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2876 #endif
2877 /* Set Bus Master Request */
2878 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
2879
2880 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
2881 switch (pci->device) {
2882 case PCI_DEVICE_ID_CMEDIA_CM8738:
2883 case PCI_DEVICE_ID_CMEDIA_CM8738B:
2884 if (!pci_dev_present(intel_82437vx))
2885 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
2886 break;
2887 default:
2888 break;
2889 }
2890
2891 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
2892 snd_cmipci_free(cm);
2893 return err;
2894 }
2895
2896 /* set MPU address */
2897 switch (iomidi) {
2898 case 0x320: val = CM_VMPU_320; break;
2899 case 0x310: val = CM_VMPU_310; break;
2900 case 0x300: val = CM_VMPU_300; break;
2901 case 0x330: val = CM_VMPU_330; break;
2902 default:
2903 iomidi = 0; break;
2904 }
2905 if (iomidi > 0) {
2906 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2907 /* enable UART */
2908 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
2909 }
2910
2911 /* set FM address */
2912 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2913 switch (iosynth) {
2914 case 0x3E8: val |= CM_FMSEL_3E8; break;
2915 case 0x3E0: val |= CM_FMSEL_3E0; break;
2916 case 0x3C8: val |= CM_FMSEL_3C8; break;
2917 case 0x388: val |= CM_FMSEL_388; break;
2918 default:
2919 iosynth = 0; break;
2920 }
2921 if (iosynth > 0) {
2922 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2923 /* enable FM */
2924 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2925
2926 if (snd_opl3_create(card, iosynth, iosynth + 2,
2927 OPL3_HW_OPL3, 0, &cm->opl3) < 0) {
2928 printk(KERN_ERR "cmipci: no OPL device at 0x%lx, skipping...\n", iosynth);
2929 iosynth = 0;
2930 } else {
2931 if ((err = snd_opl3_hwdep_new(cm->opl3, 0, 1, &cm->opl3hwdep)) < 0) {
2932 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n");
2933 return err;
2934 }
2935 }
2936 }
2937 if (! iosynth) {
2938 /* disable FM */
2939 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val & ~CM_FMSEL_MASK);
2940 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2941 }
2942
2943 /* reset mixer */
2944 snd_cmipci_mixer_write(cm, 0, 0);
2945
2946 snd_cmipci_proc_init(cm);
2947
2948 /* create pcm devices */
2949 pcm_index = pcm_spdif_index = 0;
2950 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
2951 return err;
2952 pcm_index++;
2953 if (cm->has_dual_dac) {
2954 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
2955 return err;
2956 pcm_index++;
2957 }
2958 if (cm->can_ac3_hw || cm->can_ac3_sw) {
2959 pcm_spdif_index = pcm_index;
2960 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
2961 return err;
2962 }
2963
2964 /* create mixer interface & switches */
2965 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
2966 return err;
2967
2968 if (iomidi > 0) {
2969 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
2970 iomidi, 0,
2971 cm->irq, 0, &cm->rmidi)) < 0) {
2972 printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi);
2973 }
2974 }
2975
2976 #ifdef USE_VAR48KRATE
2977 for (val = 0; val < ARRAY_SIZE(rates); val++)
2978 snd_cmipci_set_pll(cm, rates[val], val);
2979
2980 /*
2981 * (Re-)Enable external switch spdo_48k
2982 */
2983 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
2984 #endif /* USE_VAR48KRATE */
2985
2986 if (snd_cmipci_create_gameport(cm, dev) < 0)
2987 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2988
2989 snd_card_set_dev(card, &pci->dev);
2990
2991 *rcmipci = cm;
2992 return 0;
2993 }
2994
2995 /*
2996 */
2997
2998 MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
2999
3000 static int __devinit snd_cmipci_probe(struct pci_dev *pci,
3001 const struct pci_device_id *pci_id)
3002 {
3003 static int dev;
3004 snd_card_t *card;
3005 cmipci_t *cm;
3006 int err;
3007
3008 if (dev >= SNDRV_CARDS)
3009 return -ENODEV;
3010 if (! enable[dev]) {
3011 dev++;
3012 return -ENOENT;
3013 }
3014
3015 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
3016 if (card == NULL)
3017 return -ENOMEM;
3018
3019 switch (pci->device) {
3020 case PCI_DEVICE_ID_CMEDIA_CM8738:
3021 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3022 strcpy(card->driver, "CMI8738");
3023 break;
3024 case PCI_DEVICE_ID_CMEDIA_CM8338A:
3025 case PCI_DEVICE_ID_CMEDIA_CM8338B:
3026 strcpy(card->driver, "CMI8338");
3027 break;
3028 default:
3029 strcpy(card->driver, "CMIPCI");
3030 break;
3031 }
3032
3033 if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) {
3034 snd_card_free(card);
3035 return err;
3036 }
3037
3038 sprintf(card->shortname, "C-Media PCI %s", card->driver);
3039 sprintf(card->longname, "%s (model %d) at 0x%lx, irq %i",
3040 card->shortname,
3041 cm->chip_version,
3042 cm->iobase,
3043 cm->irq);
3044
3045 //snd_printd("%s is detected\n", card->longname);
3046
3047 if ((err = snd_card_register(card)) < 0) {
3048 snd_card_free(card);
3049 return err;
3050 }
3051 pci_set_drvdata(pci, card);
3052 dev++;
3053 return 0;
3054
3055 }
3056
3057 static void __devexit snd_cmipci_remove(struct pci_dev *pci)
3058 {
3059 snd_card_free(pci_get_drvdata(pci));
3060 pci_set_drvdata(pci, NULL);
3061 }
3062
3063
3064 static struct pci_driver driver = {
3065 .name = "C-Media PCI",
3066 .id_table = snd_cmipci_ids,
3067 .probe = snd_cmipci_probe,
3068 .remove = __devexit_p(snd_cmipci_remove),
3069 };
3070
3071 static int __init alsa_card_cmipci_init(void)
3072 {
3073 return pci_register_driver(&driver);
3074 }
3075
3076 static void __exit alsa_card_cmipci_exit(void)
3077 {
3078 pci_unregister_driver(&driver);
3079 }
3080
3081 module_init(alsa_card_cmipci_init)
3082 module_exit(alsa_card_cmipci_exit)
Linux for Ginger Game Console