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omap_hsmmc: Flush posted write to IRQ
[linux-ginger.git] / arch / mips / alchemy / common / dbdma.c
blob3ab6d80d150d742b42daea99d652b7a04734c662
1 /*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * The Descriptor Based DMA channel manager that first appeared
5 * on the Au1550. I started with dma.c, but I think all that is
6 * left is this initial comment :-)
7 *
8 * Copyright 2004 Embedded Edge, LLC
9 * dan@embeddededge.com
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/slab.h>
35 #include <linux/spinlock.h>
36 #include <linux/interrupt.h>
37 #include <linux/module.h>
38 #include <asm/mach-au1x00/au1000.h>
39 #include <asm/mach-au1x00/au1xxx_dbdma.h>
40
41 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
42
43 /*
44 * The Descriptor Based DMA supports up to 16 channels.
45 *
46 * There are 32 devices defined. We keep an internal structure
47 * of devices using these channels, along with additional
48 * information.
49 *
50 * We allocate the descriptors and allow access to them through various
51 * functions. The drivers allocate the data buffers and assign them
52 * to the descriptors.
53 */
54 static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock);
55
56 /* I couldn't find a macro that did this... */
57 #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1))
58
59 static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
60 static int dbdma_initialized;
61 static void au1xxx_dbdma_init(void);
62
63 static dbdev_tab_t dbdev_tab[] = {
64 #ifdef CONFIG_SOC_AU1550
65 /* UARTS */
66 { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
67 { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
68 { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },
69 { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },
70
71 /* EXT DMA */
72 { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
73 { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
74 { DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },
75 { DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },
76
77 /* USB DEV */
78 { DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },
79 { DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },
80 { DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },
81 { DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },
82 { DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 },
83 { DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 },
84
85 /* PSC 0 */
86 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
87 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
88
89 /* PSC 1 */
90 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
91 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
92
93 /* PSC 2 */
94 { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },
95 { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 },
96
97 /* PSC 3 */
98 { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },
99 { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 },
100
101 { DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */
102 { DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */
103
104 /* MAC 0 */
105 { DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
106 { DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
107
108 /* MAC 1 */
109 { DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
110 { DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
111
112 #endif /* CONFIG_SOC_AU1550 */
113
114 #ifdef CONFIG_SOC_AU1200
115 { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
116 { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
117 { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },
118 { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 },
119
120 { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
121 { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
122
123 { DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
124 { DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
125 { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
126 { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
127
128 { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
129 { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
130 { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
131 { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
132
133 { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
134 { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
135
136 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 },
137 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 },
138 { DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
139
140 { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 },
141 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 },
142 { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
143
144 { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
145 { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
146 { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
147 { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
148
149 { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
150
151 #endif /* CONFIG_SOC_AU1200 */
152
153 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
154 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
155
156 /* Provide 16 user definable device types */
157 { ~0, 0, 0, 0, 0, 0, 0 },
158 { ~0, 0, 0, 0, 0, 0, 0 },
159 { ~0, 0, 0, 0, 0, 0, 0 },
160 { ~0, 0, 0, 0, 0, 0, 0 },
161 { ~0, 0, 0, 0, 0, 0, 0 },
162 { ~0, 0, 0, 0, 0, 0, 0 },
163 { ~0, 0, 0, 0, 0, 0, 0 },
164 { ~0, 0, 0, 0, 0, 0, 0 },
165 { ~0, 0, 0, 0, 0, 0, 0 },
166 { ~0, 0, 0, 0, 0, 0, 0 },
167 { ~0, 0, 0, 0, 0, 0, 0 },
168 { ~0, 0, 0, 0, 0, 0, 0 },
169 { ~0, 0, 0, 0, 0, 0, 0 },
170 { ~0, 0, 0, 0, 0, 0, 0 },
171 { ~0, 0, 0, 0, 0, 0, 0 },
172 { ~0, 0, 0, 0, 0, 0, 0 },
173 };
174
175 #define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab)
176
177 #ifdef CONFIG_PM
178 static u32 au1xxx_dbdma_pm_regs[NUM_DBDMA_CHANS + 1][8];
179 #endif
180
181
182 static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
183
184 static dbdev_tab_t *find_dbdev_id(u32 id)
185 {
186 int i;
187 dbdev_tab_t *p;
188 for (i = 0; i < DBDEV_TAB_SIZE; ++i) {
189 p = &dbdev_tab[i];
190 if (p->dev_id == id)
191 return p;
192 }
193 return NULL;
194 }
195
196 void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp)
197 {
198 return phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
199 }
200 EXPORT_SYMBOL(au1xxx_ddma_get_nextptr_virt);
201
202 u32 au1xxx_ddma_add_device(dbdev_tab_t *dev)
203 {
204 u32 ret = 0;
205 dbdev_tab_t *p;
206 static u16 new_id = 0x1000;
207
208 p = find_dbdev_id(~0);
209 if (NULL != p) {
210 memcpy(p, dev, sizeof(dbdev_tab_t));
211 p->dev_id = DSCR_DEV2CUSTOM_ID(new_id, dev->dev_id);
212 ret = p->dev_id;
213 new_id++;
214 #if 0
215 printk(KERN_DEBUG "add_device: id:%x flags:%x padd:%x\n",
216 p->dev_id, p->dev_flags, p->dev_physaddr);
217 #endif
218 }
219
220 return ret;
221 }
222 EXPORT_SYMBOL(au1xxx_ddma_add_device);
223
224 void au1xxx_ddma_del_device(u32 devid)
225 {
226 dbdev_tab_t *p = find_dbdev_id(devid);
227
228 if (p != NULL) {
229 memset(p, 0, sizeof(dbdev_tab_t));
230 p->dev_id = ~0;
231 }
232 }
233 EXPORT_SYMBOL(au1xxx_ddma_del_device);
234
235 /* Allocate a channel and return a non-zero descriptor if successful. */
236 u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
237 void (*callback)(int, void *), void *callparam)
238 {
239 unsigned long flags;
240 u32 used, chan, rv;
241 u32 dcp;
242 int i;
243 dbdev_tab_t *stp, *dtp;
244 chan_tab_t *ctp;
245 au1x_dma_chan_t *cp;
246
247 /*
248 * We do the intialization on the first channel allocation.
249 * We have to wait because of the interrupt handler initialization
250 * which can't be done successfully during board set up.
251 */
252 if (!dbdma_initialized)
253 au1xxx_dbdma_init();
254 dbdma_initialized = 1;
255
256 stp = find_dbdev_id(srcid);
257 if (stp == NULL)
258 return 0;
259 dtp = find_dbdev_id(destid);
260 if (dtp == NULL)
261 return 0;
262
263 used = 0;
264 rv = 0;
265
266 /* Check to see if we can get both channels. */
267 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
268 if (!(stp->dev_flags & DEV_FLAGS_INUSE) ||
269 (stp->dev_flags & DEV_FLAGS_ANYUSE)) {
270 /* Got source */
271 stp->dev_flags |= DEV_FLAGS_INUSE;
272 if (!(dtp->dev_flags & DEV_FLAGS_INUSE) ||
273 (dtp->dev_flags & DEV_FLAGS_ANYUSE)) {
274 /* Got destination */
275 dtp->dev_flags |= DEV_FLAGS_INUSE;
276 } else {
277 /* Can't get dest. Release src. */
278 stp->dev_flags &= ~DEV_FLAGS_INUSE;
279 used++;
280 }
281 } else
282 used++;
283 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
284
285 if (!used) {
286 /* Let's see if we can allocate a channel for it. */
287 ctp = NULL;
288 chan = 0;
289 spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
290 for (i = 0; i < NUM_DBDMA_CHANS; i++)
291 if (chan_tab_ptr[i] == NULL) {
292 /*
293 * If kmalloc fails, it is caught below same
294 * as a channel not available.
295 */
296 ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC);
297 chan_tab_ptr[i] = ctp;
298 break;
299 }
300 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
301
302 if (ctp != NULL) {
303 memset(ctp, 0, sizeof(chan_tab_t));
304 ctp->chan_index = chan = i;
305 dcp = DDMA_CHANNEL_BASE;
306 dcp += (0x0100 * chan);
307 ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
308 cp = (au1x_dma_chan_t *)dcp;
309 ctp->chan_src = stp;
310 ctp->chan_dest = dtp;
311 ctp->chan_callback = callback;
312 ctp->chan_callparam = callparam;
313
314 /* Initialize channel configuration. */
315 i = 0;
316 if (stp->dev_intlevel)
317 i |= DDMA_CFG_SED;
318 if (stp->dev_intpolarity)
319 i |= DDMA_CFG_SP;
320 if (dtp->dev_intlevel)
321 i |= DDMA_CFG_DED;
322 if (dtp->dev_intpolarity)
323 i |= DDMA_CFG_DP;
324 if ((stp->dev_flags & DEV_FLAGS_SYNC) ||
325 (dtp->dev_flags & DEV_FLAGS_SYNC))
326 i |= DDMA_CFG_SYNC;
327 cp->ddma_cfg = i;
328 au_sync();
329
330 /* Return a non-zero value that can be used to
331 * find the channel information in subsequent
332 * operations.
333 */
334 rv = (u32)(&chan_tab_ptr[chan]);
335 } else {
336 /* Release devices */
337 stp->dev_flags &= ~DEV_FLAGS_INUSE;
338 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
339 }
340 }
341 return rv;
342 }
343 EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc);
344
345 /*
346 * Set the device width if source or destination is a FIFO.
347 * Should be 8, 16, or 32 bits.
348 */
349 u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits)
350 {
351 u32 rv;
352 chan_tab_t *ctp;
353 dbdev_tab_t *stp, *dtp;
354
355 ctp = *((chan_tab_t **)chanid);
356 stp = ctp->chan_src;
357 dtp = ctp->chan_dest;
358 rv = 0;
359
360 if (stp->dev_flags & DEV_FLAGS_IN) { /* Source in fifo */
361 rv = stp->dev_devwidth;
362 stp->dev_devwidth = bits;
363 }
364 if (dtp->dev_flags & DEV_FLAGS_OUT) { /* Destination out fifo */
365 rv = dtp->dev_devwidth;
366 dtp->dev_devwidth = bits;
367 }
368
369 return rv;
370 }
371 EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth);
372
373 /* Allocate a descriptor ring, initializing as much as possible. */
374 u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
375 {
376 int i;
377 u32 desc_base, srcid, destid;
378 u32 cmd0, cmd1, src1, dest1;
379 u32 src0, dest0;
380 chan_tab_t *ctp;
381 dbdev_tab_t *stp, *dtp;
382 au1x_ddma_desc_t *dp;
383
384 /*
385 * I guess we could check this to be within the
386 * range of the table......
387 */
388 ctp = *((chan_tab_t **)chanid);
389 stp = ctp->chan_src;
390 dtp = ctp->chan_dest;
391
392 /*
393 * The descriptors must be 32-byte aligned. There is a
394 * possibility the allocation will give us such an address,
395 * and if we try that first we are likely to not waste larger
396 * slabs of memory.
397 */
398 desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t),
399 GFP_KERNEL|GFP_DMA);
400 if (desc_base == 0)
401 return 0;
402
403 if (desc_base & 0x1f) {
404 /*
405 * Lost....do it again, allocate extra, and round
406 * the address base.
407 */
408 kfree((const void *)desc_base);
409 i = entries * sizeof(au1x_ddma_desc_t);
410 i += (sizeof(au1x_ddma_desc_t) - 1);
411 desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA);
412 if (desc_base == 0)
413 return 0;
414
415 desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t));
416 }
417 dp = (au1x_ddma_desc_t *)desc_base;
418
419 /* Keep track of the base descriptor. */
420 ctp->chan_desc_base = dp;
421
422 /* Initialize the rings with as much information as we know. */
423 srcid = stp->dev_id;
424 destid = dtp->dev_id;
425
426 cmd0 = cmd1 = src1 = dest1 = 0;
427 src0 = dest0 = 0;
428
429 cmd0 |= DSCR_CMD0_SID(srcid);
430 cmd0 |= DSCR_CMD0_DID(destid);
431 cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV;
432 cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_NOCHANGE);
433
434 /* Is it mem to mem transfer? */
435 if (((DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_THROTTLE) ||
436 (DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_ALWAYS)) &&
437 ((DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_THROTTLE) ||
438 (DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_ALWAYS)))
439 cmd0 |= DSCR_CMD0_MEM;
440
441 switch (stp->dev_devwidth) {
442 case 8:
443 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_BYTE);
444 break;
445 case 16:
446 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_HALFWORD);
447 break;
448 case 32:
449 default:
450 cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_WORD);
451 break;
452 }
453
454 switch (dtp->dev_devwidth) {
455 case 8:
456 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_BYTE);
457 break;
458 case 16:
459 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_HALFWORD);
460 break;
461 case 32:
462 default:
463 cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_WORD);
464 break;
465 }
466
467 /*
468 * If the device is marked as an in/out FIFO, ensure it is
469 * set non-coherent.
470 */
471 if (stp->dev_flags & DEV_FLAGS_IN)
472 cmd0 |= DSCR_CMD0_SN; /* Source in FIFO */
473 if (dtp->dev_flags & DEV_FLAGS_OUT)
474 cmd0 |= DSCR_CMD0_DN; /* Destination out FIFO */
475
476 /*
477 * Set up source1. For now, assume no stride and increment.
478 * A channel attribute update can change this later.
479 */
480 switch (stp->dev_tsize) {
481 case 1:
482 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE1);
483 break;
484 case 2:
485 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE2);
486 break;
487 case 4:
488 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE4);
489 break;
490 case 8:
491 default:
492 src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE8);
493 break;
494 }
495
496 /* If source input is FIFO, set static address. */
497 if (stp->dev_flags & DEV_FLAGS_IN) {
498 if (stp->dev_flags & DEV_FLAGS_BURSTABLE)
499 src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST);
500 else
501 src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
502 }
503
504 if (stp->dev_physaddr)
505 src0 = stp->dev_physaddr;
506
507 /*
508 * Set up dest1. For now, assume no stride and increment.
509 * A channel attribute update can change this later.
510 */
511 switch (dtp->dev_tsize) {
512 case 1:
513 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE1);
514 break;
515 case 2:
516 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE2);
517 break;
518 case 4:
519 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE4);
520 break;
521 case 8:
522 default:
523 dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE8);
524 break;
525 }
526
527 /* If destination output is FIFO, set static address. */
528 if (dtp->dev_flags & DEV_FLAGS_OUT) {
529 if (dtp->dev_flags & DEV_FLAGS_BURSTABLE)
530 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST);
531 else
532 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC);
533 }
534
535 if (dtp->dev_physaddr)
536 dest0 = dtp->dev_physaddr;
537
538 #if 0
539 printk(KERN_DEBUG "did:%x sid:%x cmd0:%x cmd1:%x source0:%x "
540 "source1:%x dest0:%x dest1:%x\n",
541 dtp->dev_id, stp->dev_id, cmd0, cmd1, src0,
542 src1, dest0, dest1);
543 #endif
544 for (i = 0; i < entries; i++) {
545 dp->dscr_cmd0 = cmd0;
546 dp->dscr_cmd1 = cmd1;
547 dp->dscr_source0 = src0;
548 dp->dscr_source1 = src1;
549 dp->dscr_dest0 = dest0;
550 dp->dscr_dest1 = dest1;
551 dp->dscr_stat = 0;
552 dp->sw_context = 0;
553 dp->sw_status = 0;
554 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1));
555 dp++;
556 }
557
558 /* Make last descrptor point to the first. */
559 dp--;
560 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base));
561 ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
562
563 return (u32)ctp->chan_desc_base;
564 }
565 EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc);
566
567 /*
568 * Put a source buffer into the DMA ring.
569 * This updates the source pointer and byte count. Normally used
570 * for memory to fifo transfers.
571 */
572 u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags)
573 {
574 chan_tab_t *ctp;
575 au1x_ddma_desc_t *dp;
576
577 /*
578 * I guess we could check this to be within the
579 * range of the table......
580 */
581 ctp = *(chan_tab_t **)chanid;
582
583 /*
584 * We should have multiple callers for a particular channel,
585 * an interrupt doesn't affect this pointer nor the descriptor,
586 * so no locking should be needed.
587 */
588 dp = ctp->put_ptr;
589
590 /*
591 * If the descriptor is valid, we are way ahead of the DMA
592 * engine, so just return an error condition.
593 */
594 if (dp->dscr_cmd0 & DSCR_CMD0_V)
595 return 0;
596
597 /* Load up buffer address and byte count. */
598 dp->dscr_source0 = virt_to_phys(buf);
599 dp->dscr_cmd1 = nbytes;
600 /* Check flags */
601 if (flags & DDMA_FLAGS_IE)
602 dp->dscr_cmd0 |= DSCR_CMD0_IE;
603 if (flags & DDMA_FLAGS_NOIE)
604 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
605
606 /*
607 * There is an errata on the Au1200/Au1550 parts that could result
608 * in "stale" data being DMA'ed. It has to do with the snoop logic on
609 * the cache eviction buffer. DMA_NONCOHERENT is on by default for
610 * these parts. If it is fixed in the future, these dma_cache_inv will
611 * just be nothing more than empty macros. See io.h.
612 */
613 dma_cache_wback_inv((unsigned long)buf, nbytes);
614 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
615 au_sync();
616 dma_cache_wback_inv((unsigned long)dp, sizeof(dp));
617 ctp->chan_ptr->ddma_dbell = 0;
618
619 /* Get next descriptor pointer. */
620 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
621
622 /* Return something non-zero. */
623 return nbytes;
624 }
625 EXPORT_SYMBOL(_au1xxx_dbdma_put_source);
626
627 /* Put a destination buffer into the DMA ring.
628 * This updates the destination pointer and byte count. Normally used
629 * to place an empty buffer into the ring for fifo to memory transfers.
630 */
631 u32
632 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
633 {
634 chan_tab_t *ctp;
635 au1x_ddma_desc_t *dp;
636
637 /* I guess we could check this to be within the
638 * range of the table......
639 */
640 ctp = *((chan_tab_t **)chanid);
641
642 /* We should have multiple callers for a particular channel,
643 * an interrupt doesn't affect this pointer nor the descriptor,
644 * so no locking should be needed.
645 */
646 dp = ctp->put_ptr;
647
648 /* If the descriptor is valid, we are way ahead of the DMA
649 * engine, so just return an error condition.
650 */
651 if (dp->dscr_cmd0 & DSCR_CMD0_V)
652 return 0;
653
654 /* Load up buffer address and byte count */
655
656 /* Check flags */
657 if (flags & DDMA_FLAGS_IE)
658 dp->dscr_cmd0 |= DSCR_CMD0_IE;
659 if (flags & DDMA_FLAGS_NOIE)
660 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
661
662 dp->dscr_dest0 = virt_to_phys(buf);
663 dp->dscr_cmd1 = nbytes;
664 #if 0
665 printk(KERN_DEBUG "cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
666 dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0,
667 dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1);
668 #endif
669 /*
670 * There is an errata on the Au1200/Au1550 parts that could result in
671 * "stale" data being DMA'ed. It has to do with the snoop logic on the
672 * cache eviction buffer. DMA_NONCOHERENT is on by default for these
673 * parts. If it is fixed in the future, these dma_cache_inv will just
674 * be nothing more than empty macros. See io.h.
675 */
676 dma_cache_inv((unsigned long)buf, nbytes);
677 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
678 au_sync();
679 dma_cache_wback_inv((unsigned long)dp, sizeof(dp));
680 ctp->chan_ptr->ddma_dbell = 0;
681
682 /* Get next descriptor pointer. */
683 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
684
685 /* Return something non-zero. */
686 return nbytes;
687 }
688 EXPORT_SYMBOL(_au1xxx_dbdma_put_dest);
689
690 /*
691 * Get a destination buffer into the DMA ring.
692 * Normally used to get a full buffer from the ring during fifo
693 * to memory transfers. This does not set the valid bit, you will
694 * have to put another destination buffer to keep the DMA going.
695 */
696 u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes)
697 {
698 chan_tab_t *ctp;
699 au1x_ddma_desc_t *dp;
700 u32 rv;
701
702 /*
703 * I guess we could check this to be within the
704 * range of the table......
705 */
706 ctp = *((chan_tab_t **)chanid);
707
708 /*
709 * We should have multiple callers for a particular channel,
710 * an interrupt doesn't affect this pointer nor the descriptor,
711 * so no locking should be needed.
712 */
713 dp = ctp->get_ptr;
714
715 /*
716 * If the descriptor is valid, we are way ahead of the DMA
717 * engine, so just return an error condition.
718 */
719 if (dp->dscr_cmd0 & DSCR_CMD0_V)
720 return 0;
721
722 /* Return buffer address and byte count. */
723 *buf = (void *)(phys_to_virt(dp->dscr_dest0));
724 *nbytes = dp->dscr_cmd1;
725 rv = dp->dscr_stat;
726
727 /* Get next descriptor pointer. */
728 ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
729
730 /* Return something non-zero. */
731 return rv;
732 }
733 EXPORT_SYMBOL_GPL(au1xxx_dbdma_get_dest);
734
735 void au1xxx_dbdma_stop(u32 chanid)
736 {
737 chan_tab_t *ctp;
738 au1x_dma_chan_t *cp;
739 int halt_timeout = 0;
740
741 ctp = *((chan_tab_t **)chanid);
742
743 cp = ctp->chan_ptr;
744 cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */
745 au_sync();
746 while (!(cp->ddma_stat & DDMA_STAT_H)) {
747 udelay(1);
748 halt_timeout++;
749 if (halt_timeout > 100) {
750 printk(KERN_WARNING "warning: DMA channel won't halt\n");
751 break;
752 }
753 }
754 /* clear current desc valid and doorbell */
755 cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
756 au_sync();
757 }
758 EXPORT_SYMBOL(au1xxx_dbdma_stop);
759
760 /*
761 * Start using the current descriptor pointer. If the DBDMA encounters
762 * a non-valid descriptor, it will stop. In this case, we can just
763 * continue by adding a buffer to the list and starting again.
764 */
765 void au1xxx_dbdma_start(u32 chanid)
766 {
767 chan_tab_t *ctp;
768 au1x_dma_chan_t *cp;
769
770 ctp = *((chan_tab_t **)chanid);
771 cp = ctp->chan_ptr;
772 cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
773 cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */
774 au_sync();
775 cp->ddma_dbell = 0;
776 au_sync();
777 }
778 EXPORT_SYMBOL(au1xxx_dbdma_start);
779
780 void au1xxx_dbdma_reset(u32 chanid)
781 {
782 chan_tab_t *ctp;
783 au1x_ddma_desc_t *dp;
784
785 au1xxx_dbdma_stop(chanid);
786
787 ctp = *((chan_tab_t **)chanid);
788 ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
789
790 /* Run through the descriptors and reset the valid indicator. */
791 dp = ctp->chan_desc_base;
792
793 do {
794 dp->dscr_cmd0 &= ~DSCR_CMD0_V;
795 /*
796 * Reset our software status -- this is used to determine
797 * if a descriptor is in use by upper level software. Since
798 * posting can reset 'V' bit.
799 */
800 dp->sw_status = 0;
801 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
802 } while (dp != ctp->chan_desc_base);
803 }
804 EXPORT_SYMBOL(au1xxx_dbdma_reset);
805
806 u32 au1xxx_get_dma_residue(u32 chanid)
807 {
808 chan_tab_t *ctp;
809 au1x_dma_chan_t *cp;
810 u32 rv;
811
812 ctp = *((chan_tab_t **)chanid);
813 cp = ctp->chan_ptr;
814
815 /* This is only valid if the channel is stopped. */
816 rv = cp->ddma_bytecnt;
817 au_sync();
818
819 return rv;
820 }
821 EXPORT_SYMBOL_GPL(au1xxx_get_dma_residue);
822
823 void au1xxx_dbdma_chan_free(u32 chanid)
824 {
825 chan_tab_t *ctp;
826 dbdev_tab_t *stp, *dtp;
827
828 ctp = *((chan_tab_t **)chanid);
829 stp = ctp->chan_src;
830 dtp = ctp->chan_dest;
831
832 au1xxx_dbdma_stop(chanid);
833
834 kfree((void *)ctp->chan_desc_base);
835
836 stp->dev_flags &= ~DEV_FLAGS_INUSE;
837 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
838 chan_tab_ptr[ctp->chan_index] = NULL;
839
840 kfree(ctp);
841 }
842 EXPORT_SYMBOL(au1xxx_dbdma_chan_free);
843
844 static irqreturn_t dbdma_interrupt(int irq, void *dev_id)
845 {
846 u32 intstat;
847 u32 chan_index;
848 chan_tab_t *ctp;
849 au1x_ddma_desc_t *dp;
850 au1x_dma_chan_t *cp;
851
852 intstat = dbdma_gptr->ddma_intstat;
853 au_sync();
854 chan_index = __ffs(intstat);
855
856 ctp = chan_tab_ptr[chan_index];
857 cp = ctp->chan_ptr;
858 dp = ctp->cur_ptr;
859
860 /* Reset interrupt. */
861 cp->ddma_irq = 0;
862 au_sync();
863
864 if (ctp->chan_callback)
865 ctp->chan_callback(irq, ctp->chan_callparam);
866
867 ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
868 return IRQ_RETVAL(1);
869 }
870
871 static void au1xxx_dbdma_init(void)
872 {
873 int irq_nr;
874
875 dbdma_gptr->ddma_config = 0;
876 dbdma_gptr->ddma_throttle = 0;
877 dbdma_gptr->ddma_inten = 0xffff;
878 au_sync();
879
880 #if defined(CONFIG_SOC_AU1550)
881 irq_nr = AU1550_DDMA_INT;
882 #elif defined(CONFIG_SOC_AU1200)
883 irq_nr = AU1200_DDMA_INT;
884 #else
885 #error Unknown Au1x00 SOC
886 #endif
887
888 if (request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED,
889 "Au1xxx dbdma", (void *)dbdma_gptr))
890 printk(KERN_ERR "Can't get 1550 dbdma irq");
891 }
892
893 void au1xxx_dbdma_dump(u32 chanid)
894 {
895 chan_tab_t *ctp;
896 au1x_ddma_desc_t *dp;
897 dbdev_tab_t *stp, *dtp;
898 au1x_dma_chan_t *cp;
899 u32 i = 0;
900
901 ctp = *((chan_tab_t **)chanid);
902 stp = ctp->chan_src;
903 dtp = ctp->chan_dest;
904 cp = ctp->chan_ptr;
905
906 printk(KERN_DEBUG "Chan %x, stp %x (dev %d) dtp %x (dev %d) \n",
907 (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp,
908 dtp - dbdev_tab);
909 printk(KERN_DEBUG "desc base %x, get %x, put %x, cur %x\n",
910 (u32)(ctp->chan_desc_base), (u32)(ctp->get_ptr),
911 (u32)(ctp->put_ptr), (u32)(ctp->cur_ptr));
912
913 printk(KERN_DEBUG "dbdma chan %x\n", (u32)cp);
914 printk(KERN_DEBUG "cfg %08x, desptr %08x, statptr %08x\n",
915 cp->ddma_cfg, cp->ddma_desptr, cp->ddma_statptr);
916 printk(KERN_DEBUG "dbell %08x, irq %08x, stat %08x, bytecnt %08x\n",
917 cp->ddma_dbell, cp->ddma_irq, cp->ddma_stat,
918 cp->ddma_bytecnt);
919
920 /* Run through the descriptors */
921 dp = ctp->chan_desc_base;
922
923 do {
924 printk(KERN_DEBUG "Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n",
925 i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
926 printk(KERN_DEBUG "src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n",
927 dp->dscr_source0, dp->dscr_source1,
928 dp->dscr_dest0, dp->dscr_dest1);
929 printk(KERN_DEBUG "stat %08x, nxtptr %08x\n",
930 dp->dscr_stat, dp->dscr_nxtptr);
931 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
932 } while (dp != ctp->chan_desc_base);
933 }
934
935 /* Put a descriptor into the DMA ring.
936 * This updates the source/destination pointers and byte count.
937 */
938 u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr)
939 {
940 chan_tab_t *ctp;
941 au1x_ddma_desc_t *dp;
942 u32 nbytes = 0;
943
944 /*
945 * I guess we could check this to be within the
946 * range of the table......
947 */
948 ctp = *((chan_tab_t **)chanid);
949
950 /*
951 * We should have multiple callers for a particular channel,
952 * an interrupt doesn't affect this pointer nor the descriptor,
953 * so no locking should be needed.
954 */
955 dp = ctp->put_ptr;
956
957 /*
958 * If the descriptor is valid, we are way ahead of the DMA
959 * engine, so just return an error condition.
960 */
961 if (dp->dscr_cmd0 & DSCR_CMD0_V)
962 return 0;
963
964 /* Load up buffer addresses and byte count. */
965 dp->dscr_dest0 = dscr->dscr_dest0;
966 dp->dscr_source0 = dscr->dscr_source0;
967 dp->dscr_dest1 = dscr->dscr_dest1;
968 dp->dscr_source1 = dscr->dscr_source1;
969 dp->dscr_cmd1 = dscr->dscr_cmd1;
970 nbytes = dscr->dscr_cmd1;
971 /* Allow the caller to specifiy if an interrupt is generated */
972 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
973 dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
974 ctp->chan_ptr->ddma_dbell = 0;
975
976 /* Get next descriptor pointer. */
977 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
978
979 /* Return something non-zero. */
980 return nbytes;
981 }
982
983 #ifdef CONFIG_PM
984 void au1xxx_dbdma_suspend(void)
985 {
986 int i;
987 u32 addr;
988
989 addr = DDMA_GLOBAL_BASE;
990 au1xxx_dbdma_pm_regs[0][0] = au_readl(addr + 0x00);
991 au1xxx_dbdma_pm_regs[0][1] = au_readl(addr + 0x04);
992 au1xxx_dbdma_pm_regs[0][2] = au_readl(addr + 0x08);
993 au1xxx_dbdma_pm_regs[0][3] = au_readl(addr + 0x0c);
994
995 /* save channel configurations */
996 for (i = 1, addr = DDMA_CHANNEL_BASE; i < NUM_DBDMA_CHANS; i++) {
997 au1xxx_dbdma_pm_regs[i][0] = au_readl(addr + 0x00);
998 au1xxx_dbdma_pm_regs[i][1] = au_readl(addr + 0x04);
999 au1xxx_dbdma_pm_regs[i][2] = au_readl(addr + 0x08);
1000 au1xxx_dbdma_pm_regs[i][3] = au_readl(addr + 0x0c);
1001 au1xxx_dbdma_pm_regs[i][4] = au_readl(addr + 0x10);
1002 au1xxx_dbdma_pm_regs[i][5] = au_readl(addr + 0x14);
1003 au1xxx_dbdma_pm_regs[i][6] = au_readl(addr + 0x18);
1004
1005 /* halt channel */
1006 au_writel(au1xxx_dbdma_pm_regs[i][0] & ~1, addr + 0x00);
1007 au_sync();
1008 while (!(au_readl(addr + 0x14) & 1))
1009 au_sync();
1010
1011 addr += 0x100; /* next channel base */
1012 }
1013 /* disable channel interrupts */
1014 au_writel(0, DDMA_GLOBAL_BASE + 0x0c);
1015 au_sync();
1016 }
1017
1018 void au1xxx_dbdma_resume(void)
1019 {
1020 int i;
1021 u32 addr;
1022
1023 addr = DDMA_GLOBAL_BASE;
1024 au_writel(au1xxx_dbdma_pm_regs[0][0], addr + 0x00);
1025 au_writel(au1xxx_dbdma_pm_regs[0][1], addr + 0x04);
1026 au_writel(au1xxx_dbdma_pm_regs[0][2], addr + 0x08);
1027 au_writel(au1xxx_dbdma_pm_regs[0][3], addr + 0x0c);
1028
1029 /* restore channel configurations */
1030 for (i = 1, addr = DDMA_CHANNEL_BASE; i < NUM_DBDMA_CHANS; i++) {
1031 au_writel(au1xxx_dbdma_pm_regs[i][0], addr + 0x00);
1032 au_writel(au1xxx_dbdma_pm_regs[i][1], addr + 0x04);
1033 au_writel(au1xxx_dbdma_pm_regs[i][2], addr + 0x08);
1034 au_writel(au1xxx_dbdma_pm_regs[i][3], addr + 0x0c);
1035 au_writel(au1xxx_dbdma_pm_regs[i][4], addr + 0x10);
1036 au_writel(au1xxx_dbdma_pm_regs[i][5], addr + 0x14);
1037 au_writel(au1xxx_dbdma_pm_regs[i][6], addr + 0x18);
1038 au_sync();
1039 addr += 0x100; /* next channel base */
1040 }
1041 }
1042 #endif /* CONFIG_PM */
1043 #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
Linux for Ginger Game Console