arch/mips/alchemy/common/reset.c

   1 /*
   2  *
   3  * BRIEF MODULE DESCRIPTION
   4  *      Au1xx0 reset routines.
   5  *
   6  * Copyright 2001, 2006, 2008 MontaVista Software Inc.
   7  * Author: MontaVista Software, Inc. <source@mvista.com>
   8  *
   9  *  This program is free software; you can redistribute  it and/or modify it
  10  *  under  the terms of  the GNU General  Public License as published by the
  11  *  Free Software Foundation;  either version 2 of the  License, or (at your
  12  *  option) any later version.
  13  *
  14  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  15  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  16  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  17  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  18  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  19  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  20  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  21  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  22  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  23  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24  *
  25  *  You should have received a copy of the  GNU General Public License along
  26  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  27  *  675 Mass Ave, Cambridge, MA 02139, USA.
  28  */
  29
  30 #include <asm/cacheflush.h>
  31
  32 #include <asm/mach-au1x00/au1000.h>
  33
  34 void au1000_restart(char *command)
  35 {
  36         /* Set all integrated peripherals to disabled states */
  37         extern void board_reset(void);
  38         u32 prid = read_c0_prid();
  39
  40         printk(KERN_NOTICE "\n** Resetting Integrated Peripherals\n");
  41
  42         switch (prid & 0xFF000000) {
  43         case 0x00000000: /* Au1000 */
  44                 au_writel(0x02, 0xb0000010); /* ac97_enable */
  45                 au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
  46                 asm("sync");
  47                 au_writel(0x00, 0xb017fffc); /* usbh_enable */
  48                 au_writel(0x00, 0xb0200058); /* usbd_enable */
  49                 au_writel(0x00, 0xb0300040); /* ir_enable */
  50                 au_writel(0x00, 0xb4004104); /* mac dma */
  51                 au_writel(0x00, 0xb4004114); /* mac dma */
  52                 au_writel(0x00, 0xb4004124); /* mac dma */
  53                 au_writel(0x00, 0xb4004134); /* mac dma */
  54                 au_writel(0x00, 0xb0520000); /* macen0 */
  55                 au_writel(0x00, 0xb0520004); /* macen1 */
  56                 au_writel(0x00, 0xb1000008); /* i2s_enable  */
  57                 au_writel(0x00, 0xb1100100); /* uart0_enable */
  58                 au_writel(0x00, 0xb1200100); /* uart1_enable */
  59                 au_writel(0x00, 0xb1300100); /* uart2_enable */
  60                 au_writel(0x00, 0xb1400100); /* uart3_enable */
  61                 au_writel(0x02, 0xb1600100); /* ssi0_enable */
  62                 au_writel(0x02, 0xb1680100); /* ssi1_enable */
  63                 au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
  64                 au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
  65                 au_writel(0x00, 0xb1900028); /* sys_clksrc */
  66                 au_writel(0x10, 0xb1900060); /* sys_cpupll */
  67                 au_writel(0x00, 0xb1900064); /* sys_auxpll */
  68                 au_writel(0x00, 0xb1900100); /* sys_pininputen */
  69                 break;
  70         case 0x01000000: /* Au1500 */
  71                 au_writel(0x02, 0xb0000010); /* ac97_enable */
  72                 au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
  73                 asm("sync");
  74                 au_writel(0x00, 0xb017fffc); /* usbh_enable */
  75                 au_writel(0x00, 0xb0200058); /* usbd_enable */
  76                 au_writel(0x00, 0xb4004104); /* mac dma */
  77                 au_writel(0x00, 0xb4004114); /* mac dma */
  78                 au_writel(0x00, 0xb4004124); /* mac dma */
  79                 au_writel(0x00, 0xb4004134); /* mac dma */
  80                 au_writel(0x00, 0xb1520000); /* macen0 */
  81                 au_writel(0x00, 0xb1520004); /* macen1 */
  82                 au_writel(0x00, 0xb1100100); /* uart0_enable */
  83                 au_writel(0x00, 0xb1400100); /* uart3_enable */
  84                 au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
  85                 au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
  86                 au_writel(0x00, 0xb1900028); /* sys_clksrc */
  87                 au_writel(0x10, 0xb1900060); /* sys_cpupll */
  88                 au_writel(0x00, 0xb1900064); /* sys_auxpll */
  89                 au_writel(0x00, 0xb1900100); /* sys_pininputen */
  90                 break;
  91         case 0x02000000: /* Au1100 */
  92                 au_writel(0x02, 0xb0000010); /* ac97_enable */
  93                 au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
  94                 asm("sync");
  95                 au_writel(0x00, 0xb017fffc); /* usbh_enable */
  96                 au_writel(0x00, 0xb0200058); /* usbd_enable */
  97                 au_writel(0x00, 0xb0300040); /* ir_enable */
  98                 au_writel(0x00, 0xb4004104); /* mac dma */
  99                 au_writel(0x00, 0xb4004114); /* mac dma */
 100                 au_writel(0x00, 0xb4004124); /* mac dma */
 101                 au_writel(0x00, 0xb4004134); /* mac dma */
 102                 au_writel(0x00, 0xb0520000); /* macen0 */
 103                 au_writel(0x00, 0xb1000008); /* i2s_enable  */
 104                 au_writel(0x00, 0xb1100100); /* uart0_enable */
 105                 au_writel(0x00, 0xb1200100); /* uart1_enable */
 106                 au_writel(0x00, 0xb1400100); /* uart3_enable */
 107                 au_writel(0x02, 0xb1600100); /* ssi0_enable */
 108                 au_writel(0x02, 0xb1680100); /* ssi1_enable */
 109                 au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
 110                 au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
 111                 au_writel(0x00, 0xb1900028); /* sys_clksrc */
 112                 au_writel(0x10, 0xb1900060); /* sys_cpupll */
 113                 au_writel(0x00, 0xb1900064); /* sys_auxpll */
 114                 au_writel(0x00, 0xb1900100); /* sys_pininputen */
 115                 break;
 116         case 0x03000000: /* Au1550 */
 117                 au_writel(0x00, 0xb1a00004); /* psc 0 */
 118                 au_writel(0x00, 0xb1b00004); /* psc 1 */
 119                 au_writel(0x00, 0xb0a00004); /* psc 2 */
 120                 au_writel(0x00, 0xb0b00004); /* psc 3 */
 121                 au_writel(0x00, 0xb017fffc); /* usbh_enable */
 122                 au_writel(0x00, 0xb0200058); /* usbd_enable */
 123                 au_writel(0x00, 0xb4004104); /* mac dma */
 124                 au_writel(0x00, 0xb4004114); /* mac dma */
 125                 au_writel(0x00, 0xb4004124); /* mac dma */
 126                 au_writel(0x00, 0xb4004134); /* mac dma */
 127                 au_writel(0x00, 0xb1520000); /* macen0 */
 128                 au_writel(0x00, 0xb1520004); /* macen1 */
 129                 au_writel(0x00, 0xb1100100); /* uart0_enable */
 130                 au_writel(0x00, 0xb1200100); /* uart1_enable */
 131                 au_writel(0x00, 0xb1400100); /* uart3_enable */
 132                 au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
 133                 au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
 134                 au_writel(0x00, 0xb1900028); /* sys_clksrc */
 135                 au_writel(0x10, 0xb1900060); /* sys_cpupll */
 136                 au_writel(0x00, 0xb1900064); /* sys_auxpll */
 137                 au_writel(0x00, 0xb1900100); /* sys_pininputen */
 138                 break;
 139         }
 140
 141         set_c0_status(ST0_BEV | ST0_ERL);
 142         change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
 143         flush_cache_all();
 144         write_c0_wired(0);
 145
 146         /* Give board a chance to do a hardware reset */
 147         board_reset();
 148
 149         /* Jump to the beggining in case board_reset() is empty */
 150         __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
 151 }
 152
 153 void au1000_halt(void)
 154 {
 155 #if defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550)
 156         /* Power off system */
 157         printk(KERN_NOTICE "\n** Powering off...\n");
 158         au_writew(au_readw(0xAF00001C) | (3 << 14), 0xAF00001C);
 159         au_sync();
 160         while (1); /* should not get here */
 161 #else
 162         printk(KERN_NOTICE "\n** You can safely turn off the power\n");
 163 #ifdef CONFIG_MIPS_MIRAGE
 164         au_writel((1 << 26) | (1 << 10), GPIO2_OUTPUT);
 165 #endif
 166 #ifdef CONFIG_MIPS_DB1200
 167         au_writew(au_readw(0xB980001C) | (1 << 14), 0xB980001C);
 168 #endif
 169 #ifdef CONFIG_PM
 170         au_sleep();
 171
 172         /* Should not get here */
 173         printk(KERN_ERR "Unable to put CPU in sleep mode\n");
 174         while (1);
 175 #else
 176         while (1)
 177                 __asm__(".set\tmips3\n\t"
 178                         "wait\n\t"
 179                         ".set\tmips0");
 180 #endif
 181 #endif /* defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550) */
 182 }
 183
 184 void au1000_power_off(void)
 185 {
 186         au1000_halt();
 187 }