arch/mips/kernel/smp-cmp.c

   1 /*
   2  *  This program is free software; you can distribute it and/or modify it
   3  *  under the terms of the GNU General Public License (Version 2) as
   4  *  published by the Free Software Foundation.
   5  *
   6  *  This program is distributed in the hope it will be useful, but WITHOUT
   7  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   8  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
   9  *  for more details.
  10  *
  11  *  You should have received a copy of the GNU General Public License along
  12  *  with this program; if not, write to the Free Software Foundation, Inc.,
  13  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  14  *
  15  * Copyright (C) 2007 MIPS Technologies, Inc.
  16  *    Chris Dearman (chris@mips.com)
  17  */
  18
  19 #undef DEBUG
  20
  21 #include <linux/kernel.h>
  22 #include <linux/sched.h>
  23 #include <linux/cpumask.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/compiler.h>
  26
  27 #include <asm/atomic.h>
  28 #include <asm/cacheflush.h>
  29 #include <asm/cpu.h>
  30 #include <asm/processor.h>
  31 #include <asm/system.h>
  32 #include <asm/hardirq.h>
  33 #include <asm/mmu_context.h>
  34 #include <asm/smp.h>
  35 #include <asm/time.h>
  36 #include <asm/mipsregs.h>
  37 #include <asm/mipsmtregs.h>
  38 #include <asm/mips_mt.h>
  39
  40 /*
  41  * Crude manipulation of the CPU masks to control which
  42  * which CPU's are brought online during initialisation
  43  *
  44  * Beware... this needs to be called after CPU discovery
  45  * but before CPU bringup
  46  */
  47 static int __init allowcpus(char *str)
  48 {
  49         cpumask_t cpu_allow_map;
  50         char buf[256];
  51         int len;
  52
  53         cpus_clear(cpu_allow_map);
  54         if (cpulist_parse(str, &cpu_allow_map) == 0) {
  55                 cpu_set(0, cpu_allow_map);
  56                 cpus_and(cpu_possible_map, cpu_possible_map, cpu_allow_map);
  57                 len = cpulist_scnprintf(buf, sizeof(buf)-1, &cpu_possible_map);
  58                 buf[len] = '\0';
  59                 pr_debug("Allowable CPUs: %s\n", buf);
  60                 return 1;
  61         } else
  62                 return 0;
  63 }
  64 __setup("allowcpus=", allowcpus);
  65
  66 static void ipi_call_function(unsigned int cpu)
  67 {
  68         unsigned int action = 0;
  69
  70         pr_debug("CPU%d: %s cpu %d status %08x\n",
  71                  smp_processor_id(), __func__, cpu, read_c0_status());
  72
  73         switch (cpu) {
  74         case 0:
  75                 action = GIC_IPI_EXT_INTR_CALLFNC_VPE0;
  76                 break;
  77         case 1:
  78                 action = GIC_IPI_EXT_INTR_CALLFNC_VPE1;
  79                 break;
  80         case 2:
  81                 action = GIC_IPI_EXT_INTR_CALLFNC_VPE2;
  82                 break;
  83         case 3:
  84                 action = GIC_IPI_EXT_INTR_CALLFNC_VPE3;
  85                 break;
  86         }
  87         gic_send_ipi(action);
  88 }
  89
  90
  91 static void ipi_resched(unsigned int cpu)
  92 {
  93         unsigned int action = 0;
  94
  95         pr_debug("CPU%d: %s cpu %d status %08x\n",
  96                  smp_processor_id(), __func__, cpu, read_c0_status());
  97
  98         switch (cpu) {
  99         case 0:
 100                 action = GIC_IPI_EXT_INTR_RESCHED_VPE0;
 101                 break;
 102         case 1:
 103                 action = GIC_IPI_EXT_INTR_RESCHED_VPE1;
 104                 break;
 105         case 2:
 106                 action = GIC_IPI_EXT_INTR_RESCHED_VPE2;
 107                 break;
 108         case 3:
 109                 action = GIC_IPI_EXT_INTR_RESCHED_VPE3;
 110                 break;
 111         }
 112         gic_send_ipi(action);
 113 }
 114
 115 /*
 116  * FIXME: This isn't restricted to CMP
 117  * The SMVP kernel could use GIC interrupts if available
 118  */
 119 void cmp_send_ipi_single(int cpu, unsigned int action)
 120 {
 121         unsigned long flags;
 122
 123         local_irq_save(flags);
 124
 125         switch (action) {
 126         case SMP_CALL_FUNCTION:
 127                 ipi_call_function(cpu);
 128                 break;
 129
 130         case SMP_RESCHEDULE_YOURSELF:
 131                 ipi_resched(cpu);
 132                 break;
 133         }
 134
 135         local_irq_restore(flags);
 136 }
 137
 138 static void cmp_send_ipi_mask(cpumask_t mask, unsigned int action)
 139 {
 140         unsigned int i;
 141
 142         for_each_cpu_mask(i, mask)
 143                 cmp_send_ipi_single(i, action);
 144 }
 145
 146 static void cmp_init_secondary(void)
 147 {
 148         struct cpuinfo_mips *c = &current_cpu_data;
 149
 150         /* Assume GIC is present */
 151         change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP6 |
 152                                  STATUSF_IP7);
 153
 154         /* Enable per-cpu interrupts: platform specific */
 155
 156         c->core = (read_c0_ebase() >> 1) & 0xff;
 157 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
 158         c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE;
 159 #endif
 160 #ifdef CONFIG_MIPS_MT_SMTC
 161         c->tc_id  = (read_c0_tcbind() >> TCBIND_CURTC_SHIFT) & TCBIND_CURTC;
 162 #endif
 163 }
 164
 165 static void cmp_smp_finish(void)
 166 {
 167         pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);
 168
 169         /* CDFIXME: remove this? */
 170         write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
 171
 172 #ifdef CONFIG_MIPS_MT_FPAFF
 173         /* If we have an FPU, enroll ourselves in the FPU-full mask */
 174         if (cpu_has_fpu)
 175                 cpu_set(smp_processor_id(), mt_fpu_cpumask);
 176 #endif /* CONFIG_MIPS_MT_FPAFF */
 177
 178         local_irq_enable();
 179 }
 180
 181 static void cmp_cpus_done(void)
 182 {
 183         pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);
 184 }
 185
 186 /*
 187  * Setup the PC, SP, and GP of a secondary processor and start it running
 188  * smp_bootstrap is the place to resume from
 189  * __KSTK_TOS(idle) is apparently the stack pointer
 190  * (unsigned long)idle->thread_info the gp
 191  */
 192 static void cmp_boot_secondary(int cpu, struct task_struct *idle)
 193 {
 194         struct thread_info *gp = task_thread_info(idle);
 195         unsigned long sp = __KSTK_TOS(idle);
 196         unsigned long pc = (unsigned long)&smp_bootstrap;
 197         unsigned long a0 = 0;
 198
 199         pr_debug("SMPCMP: CPU%d: %s cpu %d\n", smp_processor_id(),
 200                 __func__, cpu);
 201
 202 #if 0
 203         /* Needed? */
 204         flush_icache_range((unsigned long)gp,
 205                            (unsigned long)(gp + sizeof(struct thread_info)));
 206 #endif
 207
 208         amon_cpu_start(cpu, pc, sp, gp, a0);
 209 }
 210
 211 /*
 212  * Common setup before any secondaries are started
 213  */
 214 void __init cmp_smp_setup(void)
 215 {
 216         int i;
 217         int ncpu = 0;
 218
 219         pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);
 220
 221 #ifdef CONFIG_MIPS_MT_FPAFF
 222         /* If we have an FPU, enroll ourselves in the FPU-full mask */
 223         if (cpu_has_fpu)
 224                 cpu_set(0, mt_fpu_cpumask);
 225 #endif /* CONFIG_MIPS_MT_FPAFF */
 226
 227         for (i = 1; i < NR_CPUS; i++) {
 228                 if (amon_cpu_avail(i)) {
 229                         cpu_set(i, cpu_possible_map);
 230                         __cpu_number_map[i]     = ++ncpu;
 231                         __cpu_logical_map[ncpu] = i;
 232                 }
 233         }
 234
 235         if (cpu_has_mipsmt) {
 236                 unsigned int nvpe, mvpconf0 = read_c0_mvpconf0();
 237
 238                 nvpe = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
 239                 smp_num_siblings = nvpe;
 240         }
 241         pr_info("Detected %i available secondary CPU(s)\n", ncpu);
 242 }
 243
 244 void __init cmp_prepare_cpus(unsigned int max_cpus)
 245 {
 246         pr_debug("SMPCMP: CPU%d: %s max_cpus=%d\n",
 247                  smp_processor_id(), __func__, max_cpus);
 248
 249         /*
 250          * FIXME: some of these options are per-system, some per-core and
 251          * some per-cpu
 252          */
 253         mips_mt_set_cpuoptions();
 254 }
 255
 256 struct plat_smp_ops cmp_smp_ops = {
 257         .send_ipi_single        = cmp_send_ipi_single,
 258         .send_ipi_mask          = cmp_send_ipi_mask,
 259         .init_secondary         = cmp_init_secondary,
 260         .smp_finish             = cmp_smp_finish,
 261         .cpus_done              = cmp_cpus_done,
 262         .boot_secondary         = cmp_boot_secondary,
 263         .smp_setup              = cmp_smp_setup,
 264         .prepare_cpus           = cmp_prepare_cpus,
 265 };