omap_hsmmc: Flush posted write to IRQ
[linux-ginger.git] / arch / sh / include / asm / dma-sh.h
blob0c8f8e14622a73c8eb99f0ddc7e0a816670f3098
1 /*
2 * arch/sh/include/asm/dma-sh.h
4 * Copyright (C) 2000 Takashi YOSHII
5 * Copyright (C) 2003 Paul Mundt
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
11 #ifndef __DMA_SH_H
12 #define __DMA_SH_H
14 #include <asm/dma.h>
15 #include <cpu/dma.h>
17 /* DMAOR contorl: The DMAOR access size is different by CPU.*/
18 #if defined(CONFIG_CPU_SUBTYPE_SH7723) || \
19 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
20 defined(CONFIG_CPU_SUBTYPE_SH7785)
21 #define dmaor_read_reg(n) \
22 (n ? ctrl_inw(SH_DMAC_BASE1 + DMAOR) \
23 : ctrl_inw(SH_DMAC_BASE0 + DMAOR))
24 #define dmaor_write_reg(n, data) \
25 (n ? ctrl_outw(data, SH_DMAC_BASE1 + DMAOR) \
26 : ctrl_outw(data, SH_DMAC_BASE0 + DMAOR))
27 #else /* Other CPU */
28 #define dmaor_read_reg(n) ctrl_inw(SH_DMAC_BASE0 + DMAOR)
29 #define dmaor_write_reg(n, data) ctrl_outw(data, SH_DMAC_BASE0 + DMAOR)
30 #endif
32 static int dmte_irq_map[] __maybe_unused = {
33 #if (MAX_DMA_CHANNELS >= 4)
34 DMTE0_IRQ,
35 DMTE0_IRQ + 1,
36 DMTE0_IRQ + 2,
37 DMTE0_IRQ + 3,
38 #endif
39 #if (MAX_DMA_CHANNELS >= 6)
40 DMTE4_IRQ,
41 DMTE4_IRQ + 1,
42 #endif
43 #if (MAX_DMA_CHANNELS >= 8)
44 DMTE6_IRQ,
45 DMTE6_IRQ + 1,
46 #endif
47 #if (MAX_DMA_CHANNELS >= 12)
48 DMTE8_IRQ,
49 DMTE9_IRQ,
50 DMTE10_IRQ,
51 DMTE11_IRQ,
52 #endif
55 /* Definitions for the SuperH DMAC */
56 #define REQ_L 0x00000000
57 #define REQ_E 0x00080000
58 #define RACK_H 0x00000000
59 #define RACK_L 0x00040000
60 #define ACK_R 0x00000000
61 #define ACK_W 0x00020000
62 #define ACK_H 0x00000000
63 #define ACK_L 0x00010000
64 #define DM_INC 0x00004000
65 #define DM_DEC 0x00008000
66 #define SM_INC 0x00001000
67 #define SM_DEC 0x00002000
68 #define RS_IN 0x00000200
69 #define RS_OUT 0x00000300
70 #define TS_BLK 0x00000040
71 #define TM_BUR 0x00000020
72 #define CHCR_DE 0x00000001
73 #define CHCR_TE 0x00000002
74 #define CHCR_IE 0x00000004
76 /* DMAOR definitions */
77 #define DMAOR_AE 0x00000004
78 #define DMAOR_NMIF 0x00000002
79 #define DMAOR_DME 0x00000001
82 * Define the default configuration for dual address memory-memory transfer.
83 * The 0x400 value represents auto-request, external->external.
85 #define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_32)
87 /* DMA base address */
88 static u32 dma_base_addr[] __maybe_unused = {
89 #if (MAX_DMA_CHANNELS >= 4)
90 SH_DMAC_BASE0 + 0x00, /* channel 0 */
91 SH_DMAC_BASE0 + 0x10,
92 SH_DMAC_BASE0 + 0x20,
93 SH_DMAC_BASE0 + 0x30,
94 #endif
95 #if (MAX_DMA_CHANNELS >= 6)
96 SH_DMAC_BASE0 + 0x50,
97 SH_DMAC_BASE0 + 0x60,
98 #endif
99 #if (MAX_DMA_CHANNELS >= 8)
100 SH_DMAC_BASE1 + 0x00,
101 SH_DMAC_BASE1 + 0x10,
102 #endif
103 #if (MAX_DMA_CHANNELS >= 12)
104 SH_DMAC_BASE1 + 0x20,
105 SH_DMAC_BASE1 + 0x30,
106 SH_DMAC_BASE1 + 0x50,
107 SH_DMAC_BASE1 + 0x60, /* channel 11 */
108 #endif
111 /* DMA register */
112 #define SAR 0x00
113 #define DAR 0x04
114 #define TCR 0x08
115 #define CHCR 0x0C
116 #define DMAOR 0x40
118 #endif /* __DMA_SH_H */