1 #ifndef __ASM_SH_SYSTEM_H
2 #define __ASM_SH_SYSTEM_H
5 * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
6 * Copyright (C) 2002 Paul Mundt
9 #include <linux/irqflags.h>
10 #include <linux/compiler.h>
11 #include <linux/linkage.h>
12 #include <asm/types.h>
13 #include <asm/ptrace.h>
15 #define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */
17 #if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
20 unsigned long __addr; \
21 __addr = 0xa8000000; \
22 __asm__ __volatile__( \
25 : "m" (__m(__addr))); \
30 * A brief note on ctrl_barrier(), the control register write barrier.
32 * Legacy SH cores typically require a sequence of 8 nops after
33 * modification of a control register in order for the changes to take
34 * effect. On newer cores (like the sh4a and sh5) this is accomplished
37 * Also note that on sh4a in the icbi case we can forego a synco for the
38 * write barrier, as it's not necessary for control registers.
40 * Historically we have only done this type of barrier for the MMUCR, but
41 * it's also necessary for the CCR, so we make it generic here instead.
43 #if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
44 #define mb() __asm__ __volatile__ ("synco": : :"memory")
46 #define wmb() __asm__ __volatile__ ("synco": : :"memory")
47 #define ctrl_barrier() __icbi()
48 #define read_barrier_depends() do { } while(0)
50 #define mb() __asm__ __volatile__ ("": : :"memory")
52 #define wmb() __asm__ __volatile__ ("": : :"memory")
53 #define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
54 #define read_barrier_depends() do { } while(0)
59 #define smp_rmb() rmb()
60 #define smp_wmb() wmb()
61 #define smp_read_barrier_depends() read_barrier_depends()
63 #define smp_mb() barrier()
64 #define smp_rmb() barrier()
65 #define smp_wmb() barrier()
66 #define smp_read_barrier_depends() do { } while(0)
69 #define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
72 #include <asm/cmpxchg-grb.h>
73 #elif defined(CONFIG_CPU_SH4A)
74 #include <asm/cmpxchg-llsc.h>
76 #include <asm/cmpxchg-irq.h>
79 extern void __xchg_called_with_bad_pointer(void);
81 #define __xchg(ptr, x, size) \
83 unsigned long __xchg__res; \
84 volatile void *__xchg_ptr = (ptr); \
87 __xchg__res = xchg_u32(__xchg_ptr, x); \
90 __xchg__res = xchg_u8(__xchg_ptr, x); \
93 __xchg_called_with_bad_pointer(); \
101 #define xchg(ptr,x) \
102 ((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))
104 /* This function doesn't exist, so you'll get a linker error
105 * if something tries to do an invalid cmpxchg(). */
106 extern void __cmpxchg_called_with_bad_pointer(void);
108 #define __HAVE_ARCH_CMPXCHG 1
110 static inline unsigned long __cmpxchg(volatile void * ptr
, unsigned long old
,
111 unsigned long new, int size
)
115 return __cmpxchg_u32(ptr
, old
, new);
117 __cmpxchg_called_with_bad_pointer();
121 #define cmpxchg(ptr,o,n) \
123 __typeof__(*(ptr)) _o_ = (o); \
124 __typeof__(*(ptr)) _n_ = (n); \
125 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
126 (unsigned long)_n_, sizeof(*(ptr))); \
129 extern void die(const char *str
, struct pt_regs
*regs
, long err
) __attribute__ ((noreturn
));
130 void free_initmem(void);
131 void free_initrd_mem(unsigned long start
, unsigned long end
);
133 extern void *set_exception_table_vec(unsigned int vec
, void *handler
);
135 static inline void *set_exception_table_evt(unsigned int evt
, void *handler
)
137 return set_exception_table_vec(evt
>> 5, handler
);
141 * SH-2A has both 16 and 32-bit opcodes, do lame encoding checks.
143 #ifdef CONFIG_CPU_SH2A
144 extern unsigned int instruction_size(unsigned int insn
);
145 #elif defined(CONFIG_SUPERH32)
146 #define instruction_size(insn) (2)
148 #define instruction_size(insn) (4)
151 extern unsigned long cached_to_uncached
;
153 extern struct dentry
*sh_debugfs_root
;
155 void per_cpu_trap_init(void);
157 asmlinkage
void break_point_trap(void);
159 #ifdef CONFIG_SUPERH32
160 #define BUILD_TRAP_HANDLER(name) \
161 asmlinkage void name##_trap_handler(unsigned long r4, unsigned long r5, \
162 unsigned long r6, unsigned long r7, \
163 struct pt_regs __regs)
165 #define TRAP_HANDLER_DECL \
166 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); \
167 unsigned int vec = regs->tra; \
170 #define BUILD_TRAP_HANDLER(name) \
171 asmlinkage void name##_trap_handler(unsigned int vec, struct pt_regs *regs)
172 #define TRAP_HANDLER_DECL
175 BUILD_TRAP_HANDLER(address_error
);
176 BUILD_TRAP_HANDLER(debug
);
177 BUILD_TRAP_HANDLER(bug
);
178 BUILD_TRAP_HANDLER(breakpoint
);
179 BUILD_TRAP_HANDLER(singlestep
);
180 BUILD_TRAP_HANDLER(fpu_error
);
181 BUILD_TRAP_HANDLER(fpu_state_restore
);
183 #define arch_align_stack(x) (x)
186 unsigned long (*from
)(void *dst
, const void __user
*src
, unsigned long cnt
);
187 unsigned long (*to
)(void __user
*dst
, const void *src
, unsigned long cnt
);
190 #ifdef CONFIG_SUPERH32
191 # include "system_32.h"
193 # include "system_64.h"