arch/arm/mach-omap2/memory.c

   1 /*
   2  * linux/arch/arm/mach-omap2/memory.c
   3  *
   4  * Memory timing related functions for OMAP24XX
   5  *
   6  * Copyright (C) 2005 Texas Instruments Inc.
   7  * Richard Woodruff <r-woodruff2@ti.com>
   8  *
   9  * Copyright (C) 2005 Nokia Corporation
  10  * Tony Lindgren <tony@atomide.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/device.h>
  20 #include <linux/list.h>
  21 #include <linux/errno.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk.h>
  24 #include <linux/io.h>
  25
  26 #include <mach/common.h>
  27 #include <mach/clock.h>
  28 #include <mach/sram.h>
  29
  30 #include "prm.h"
  31
  32 #include <mach/sdrc.h>
  33 #include "sdrc.h"
  34
  35 /* Memory timing, DLL mode flags */
  36 #define M_DDR           1
  37 #define M_LOCK_CTRL     (1 << 2)
  38 #define M_UNLOCK        0
  39 #define M_LOCK          1
  40
  41
  42 void __iomem *omap2_sdrc_base;
  43 void __iomem *omap2_sms_base;
  44
  45 static struct memory_timings mem_timings;
  46 static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
  47
  48 u32 omap2_memory_get_slow_dll_ctrl(void)
  49 {
  50         return mem_timings.slow_dll_ctrl;
  51 }
  52
  53 u32 omap2_memory_get_fast_dll_ctrl(void)
  54 {
  55         return mem_timings.fast_dll_ctrl;
  56 }
  57
  58 u32 omap2_memory_get_type(void)
  59 {
  60         return mem_timings.m_type;
  61 }
  62
  63 /*
  64  * Check the DLL lock state, and return tue if running in unlock mode.
  65  * This is needed to compensate for the shifted DLL value in unlock mode.
  66  */
  67 u32 omap2_dll_force_needed(void)
  68 {
  69         /* dlla and dllb are a set */
  70         u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
  71
  72         if ((dll_state & (1 << 2)) == (1 << 2))
  73                 return 1;
  74         else
  75                 return 0;
  76 }
  77
  78 /*
  79  * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
  80  * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
  81  * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
  82  */
  83 u32 omap2_reprogram_sdrc(u32 level, u32 force)
  84 {
  85         u32 dll_ctrl, m_type;
  86         u32 prev = curr_perf_level;
  87         unsigned long flags;
  88
  89         if ((curr_perf_level == level) && !force)
  90                 return prev;
  91
  92         if (level == CORE_CLK_SRC_DPLL) {
  93                 dll_ctrl = omap2_memory_get_slow_dll_ctrl();
  94         } else if (level == CORE_CLK_SRC_DPLL_X2) {
  95                 dll_ctrl = omap2_memory_get_fast_dll_ctrl();
  96         } else {
  97                 return prev;
  98         }
  99
 100         m_type = omap2_memory_get_type();
 101
 102         local_irq_save(flags);
 103         __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP);
 104         omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
 105         curr_perf_level = level;
 106         local_irq_restore(flags);
 107
 108         return prev;
 109 }
 110
 111 #if !defined(CONFIG_ARCH_OMAP2)
 112 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 113                                 u32 base_cs, u32 force_unlock)
 114 {
 115 }
 116 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
 117                                       u32 mem_type)
 118 {
 119 }
 120 #endif
 121
 122 void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
 123 {
 124         unsigned long dll_cnt;
 125         u32 fast_dll = 0;
 126
 127         mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
 128
 129         /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
 130          * In the case of 2422, its ok to use CS1 instead of CS0.
 131          */
 132         if (cpu_is_omap2422())
 133                 mem_timings.base_cs = 1;
 134         else
 135                 mem_timings.base_cs = 0;
 136
 137         if (mem_timings.m_type != M_DDR)
 138                 return;
 139
 140         /* With DDR we need to determine the low frequency DLL value */
 141         if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
 142                 mem_timings.dll_mode = M_UNLOCK;
 143         else
 144                 mem_timings.dll_mode = M_LOCK;
 145
 146         if (mem_timings.base_cs == 0) {
 147                 fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
 148                 dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
 149         } else {
 150                 fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
 151                 dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
 152         }
 153         if (force_lock_to_unlock_mode) {
 154                 fast_dll &= ~0xff00;
 155                 fast_dll |= dll_cnt;            /* Current lock mode */
 156         }
 157         /* set fast timings with DLL filter disabled */
 158         mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));
 159
 160         /* No disruptions, DDR will be offline & C-ABI not followed */
 161         omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
 162                             mem_timings.fast_dll_ctrl,
 163                             mem_timings.base_cs,
 164                             force_lock_to_unlock_mode);
 165         mem_timings.slow_dll_ctrl &= 0xff00;    /* Keep lock value */
 166
 167         /* Turn status into unlock ctrl */
 168         mem_timings.slow_dll_ctrl |=
 169                 ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
 170
 171         /* 90 degree phase for anything below 133Mhz + disable DLL filter */
 172         mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
 173 }
 174
 175 void __init omap2_set_globals_memory(struct omap_globals *omap2_globals)
 176 {
 177         omap2_sdrc_base = omap2_globals->sdrc;
 178         omap2_sms_base = omap2_globals->sms;
 179 }
 180
 181 /* turn on smart idle modes for SDRAM scheduler and controller */
 182 void __init omap2_init_memory(void)
 183 {
 184         u32 l;
 185
 186         if (!cpu_is_omap2420())
 187                 return;
 188
 189         l = sms_read_reg(SMS_SYSCONFIG);
 190         l &= ~(0x3 << 3);
 191         l |= (0x2 << 3);
 192         sms_write_reg(l, SMS_SYSCONFIG);
 193
 194         l = sdrc_read_reg(SDRC_SYSCONFIG);
 195         l &= ~(0x3 << 3);
 196         l |= (0x2 << 3);
 197         sdrc_write_reg(l, SDRC_SYSCONFIG);
 198 }