arch/arm/mach-omap2/powerdomains34xx.h

   1 /*
   2  * OMAP34XX powerdomain definitions
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * Debugging and integration fixes by Jouni Högander
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
  16 #define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
  17
  18 /*
  19  * N.B. If powerdomains are added or removed from this file, update
  20  * the array in mach-omap2/powerdomains.h.
  21  */
  22
  23 #include <plat/powerdomain.h>
  24
  25 #include "prcm-common.h"
  26 #include "prm.h"
  27 #include "prm-regbits-34xx.h"
  28 #include "cm.h"
  29 #include "cm-regbits-34xx.h"
  30
  31 /*
  32  * 34XX-specific powerdomains, dependencies
  33  */
  34
  35 #ifdef CONFIG_ARCH_OMAP34XX
  36
  37 /*
  38  * 3430: PM_WKDEP_{PER,USBHOST}: CORE, IVA2, MPU, WKUP
  39  * (USBHOST is ES2 only)
  40  */
  41 static struct pwrdm_dep per_usbhost_wkdeps[] = {
  42         {
  43                 .pwrdm_name = "core_pwrdm",
  44                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  45         },
  46         {
  47                 .pwrdm_name = "iva2_pwrdm",
  48                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  49         },
  50         {
  51                 .pwrdm_name = "mpu_pwrdm",
  52                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  53         },
  54         {
  55                 .pwrdm_name = "wkup_pwrdm",
  56                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  57         },
  58         { NULL },
  59 };
  60
  61 /*
  62  * 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER
  63  */
  64 static struct pwrdm_dep mpu_34xx_wkdeps[] = {
  65         {
  66                 .pwrdm_name = "core_pwrdm",
  67                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  68         },
  69         {
  70                 .pwrdm_name = "iva2_pwrdm",
  71                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  72         },
  73         {
  74                 .pwrdm_name = "dss_pwrdm",
  75                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  76         },
  77         {
  78                 .pwrdm_name = "per_pwrdm",
  79                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  80         },
  81         { NULL },
  82 };
  83
  84 /*
  85  * 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER
  86  */
  87 static struct pwrdm_dep iva2_wkdeps[] = {
  88         {
  89                 .pwrdm_name = "core_pwrdm",
  90                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  91         },
  92         {
  93                 .pwrdm_name = "mpu_pwrdm",
  94                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  95         },
  96         {
  97                 .pwrdm_name = "wkup_pwrdm",
  98                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  99         },
 100         {
 101                 .pwrdm_name = "dss_pwrdm",
 102                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 103         },
 104         {
 105                 .pwrdm_name = "per_pwrdm",
 106                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 107         },
 108         { NULL },
 109 };
 110
 111
 112 /* 3430 PM_WKDEP_{CAM,DSS}: IVA2, MPU, WKUP */
 113 static struct pwrdm_dep cam_dss_wkdeps[] = {
 114         {
 115                 .pwrdm_name = "iva2_pwrdm",
 116                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 117         },
 118         {
 119                 .pwrdm_name = "mpu_pwrdm",
 120                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 121         },
 122         {
 123                 .pwrdm_name = "wkup_pwrdm",
 124                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 125         },
 126         { NULL },
 127 };
 128
 129 /* 3430: PM_WKDEP_NEON: MPU */
 130 static struct pwrdm_dep neon_wkdeps[] = {
 131         {
 132                 .pwrdm_name = "mpu_pwrdm",
 133                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 134         },
 135         { NULL },
 136 };
 137
 138
 139 /* Sleep dependency source arrays for 34xx-specific pwrdms - 34XX only */
 140
 141 /*
 142  * 3430: CM_SLEEPDEP_{DSS,PER}: MPU, IVA
 143  * 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA
 144  */
 145 static struct pwrdm_dep dss_per_usbhost_sleepdeps[] = {
 146         {
 147                 .pwrdm_name = "mpu_pwrdm",
 148                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 149         },
 150         {
 151                 .pwrdm_name = "iva2_pwrdm",
 152                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 153         },
 154         { NULL },
 155 };
 156
 157
 158 /*
 159  * Powerdomains
 160  */
 161
 162 static struct powerdomain iva2_pwrdm = {
 163         .name             = "iva2_pwrdm",
 164         .prcm_offs        = OMAP3430_IVA2_MOD,
 165         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 166         .dep_bit          = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
 167         .wkdep_srcs       = iva2_wkdeps,
 168         .pwrsts           = PWRSTS_OFF_RET_ON,
 169         .pwrsts_logic_ret = PWRSTS_OFF_RET,
 170         .banks            = 4,
 171         .pwrsts_mem_ret   = {
 172                 [0] = PWRSTS_OFF_RET,
 173                 [1] = PWRSTS_OFF_RET,
 174                 [2] = PWRSTS_OFF_RET,
 175                 [3] = PWRSTS_OFF_RET,
 176         },
 177         .pwrsts_mem_on    = {
 178                 [0] = PWRDM_POWER_ON,
 179                 [1] = PWRDM_POWER_ON,
 180                 [2] = PWRSTS_OFF_ON,
 181                 [3] = PWRDM_POWER_ON,
 182         },
 183 };
 184
 185 static struct powerdomain mpu_34xx_pwrdm = {
 186         .name             = "mpu_pwrdm",
 187         .prcm_offs        = MPU_MOD,
 188         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 189         .dep_bit          = OMAP3430_EN_MPU_SHIFT,
 190         .wkdep_srcs       = mpu_34xx_wkdeps,
 191         .pwrsts           = PWRSTS_OFF_RET_ON,
 192         .pwrsts_logic_ret = PWRSTS_OFF_RET,
 193         .banks            = 1,
 194         .pwrsts_mem_ret   = {
 195                 [0] = PWRSTS_OFF_RET,
 196         },
 197         .pwrsts_mem_on    = {
 198                 [0] = PWRSTS_OFF_ON,
 199         },
 200 };
 201
 202 /* No wkdeps or sleepdeps for 34xx core apparently */
 203 static struct powerdomain core_34xx_pre_es3_1_pwrdm = {
 204         .name             = "core_pwrdm",
 205         .prcm_offs        = CORE_MOD,
 206         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
 207                                            CHIP_IS_OMAP3430ES2 |
 208                                            CHIP_IS_OMAP3430ES3_0),
 209         .pwrsts           = PWRSTS_OFF_RET_ON,
 210         .dep_bit          = OMAP3430_EN_CORE_SHIFT,
 211         .banks            = 2,
 212         .pwrsts_mem_ret   = {
 213                 [0] = PWRSTS_OFF_RET,    /* MEM1RETSTATE */
 214                 [1] = PWRSTS_OFF_RET,    /* MEM2RETSTATE */
 215         },
 216         .pwrsts_mem_on    = {
 217                 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
 218                 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
 219         },
 220 };
 221
 222 /* No wkdeps or sleepdeps for 34xx core apparently */
 223 static struct powerdomain core_34xx_es3_1_pwrdm = {
 224         .name             = "core_pwrdm",
 225         .prcm_offs        = CORE_MOD,
 226         .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1),
 227         .pwrsts           = PWRSTS_OFF_RET_ON,
 228         .dep_bit          = OMAP3430_EN_CORE_SHIFT,
 229         .flags            = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
 230         .banks            = 2,
 231         .pwrsts_mem_ret   = {
 232                 [0] = PWRSTS_OFF_RET,    /* MEM1RETSTATE */
 233                 [1] = PWRSTS_OFF_RET,    /* MEM2RETSTATE */
 234         },
 235         .pwrsts_mem_on    = {
 236                 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
 237                 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
 238         },
 239 };
 240
 241 /* Another case of bit name collisions between several registers: EN_DSS */
 242 static struct powerdomain dss_pwrdm = {
 243         .name             = "dss_pwrdm",
 244         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 245         .prcm_offs        = OMAP3430_DSS_MOD,
 246         .dep_bit          = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
 247         .wkdep_srcs       = cam_dss_wkdeps,
 248         .sleepdep_srcs    = dss_per_usbhost_sleepdeps,
 249         .pwrsts           = PWRSTS_OFF_RET_ON,
 250         .pwrsts_logic_ret = PWRDM_POWER_RET,
 251         .banks            = 1,
 252         .pwrsts_mem_ret   = {
 253                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
 254         },
 255         .pwrsts_mem_on    = {
 256                 [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
 257         },
 258 };
 259
 260 /*
 261  * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
 262  * possible SGX powerstate, the SGX device itself does not support
 263  * retention.
 264  */
 265 static struct powerdomain sgx_pwrdm = {
 266         .name             = "sgx_pwrdm",
 267         .prcm_offs        = OMAP3430ES2_SGX_MOD,
 268         .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 269         .wkdep_srcs       = gfx_sgx_wkdeps,
 270         .sleepdep_srcs    = cam_gfx_sleepdeps,
 271         /* XXX This is accurate for 3430 SGX, but what about GFX? */
 272         .pwrsts           = PWRSTS_OFF_ON,
 273         .pwrsts_logic_ret = PWRDM_POWER_RET,
 274         .banks            = 1,
 275         .pwrsts_mem_ret   = {
 276                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
 277         },
 278         .pwrsts_mem_on    = {
 279                 [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
 280         },
 281 };
 282
 283 static struct powerdomain cam_pwrdm = {
 284         .name             = "cam_pwrdm",
 285         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 286         .prcm_offs        = OMAP3430_CAM_MOD,
 287         .wkdep_srcs       = cam_dss_wkdeps,
 288         .sleepdep_srcs    = cam_gfx_sleepdeps,
 289         .pwrsts           = PWRSTS_OFF_RET_ON,
 290         .pwrsts_logic_ret = PWRDM_POWER_RET,
 291         .banks            = 1,
 292         .pwrsts_mem_ret   = {
 293                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
 294         },
 295         .pwrsts_mem_on    = {
 296                 [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
 297         },
 298 };
 299
 300 static struct powerdomain per_pwrdm = {
 301         .name             = "per_pwrdm",
 302         .prcm_offs        = OMAP3430_PER_MOD,
 303         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 304         .dep_bit          = OMAP3430_EN_PER_SHIFT,
 305         .wkdep_srcs       = per_usbhost_wkdeps,
 306         .sleepdep_srcs    = dss_per_usbhost_sleepdeps,
 307         .pwrsts           = PWRSTS_OFF_RET_ON,
 308         .pwrsts_logic_ret = PWRSTS_OFF_RET,
 309         .banks            = 1,
 310         .pwrsts_mem_ret   = {
 311                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
 312         },
 313         .pwrsts_mem_on    = {
 314                 [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
 315         },
 316 };
 317
 318 static struct powerdomain emu_pwrdm = {
 319         .name           = "emu_pwrdm",
 320         .prcm_offs      = OMAP3430_EMU_MOD,
 321         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 322 };
 323
 324 static struct powerdomain neon_pwrdm = {
 325         .name             = "neon_pwrdm",
 326         .prcm_offs        = OMAP3430_NEON_MOD,
 327         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 328         .wkdep_srcs       = neon_wkdeps,
 329         .pwrsts           = PWRSTS_OFF_RET_ON,
 330         .pwrsts_logic_ret = PWRDM_POWER_RET,
 331 };
 332
 333 static struct powerdomain usbhost_pwrdm = {
 334         .name             = "usbhost_pwrdm",
 335         .prcm_offs        = OMAP3430ES2_USBHOST_MOD,
 336         .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 337         .wkdep_srcs       = per_usbhost_wkdeps,
 338         .sleepdep_srcs    = dss_per_usbhost_sleepdeps,
 339         .pwrsts           = PWRSTS_OFF_RET_ON,
 340         .pwrsts_logic_ret = PWRDM_POWER_RET,
 341         /*
 342          * REVISIT: Enabling usb host save and restore mechanism seems to
 343          * leave the usb host domain permanently in ACTIVE mode after
 344          * changing the usb host power domain state from OFF to active once.
 345          * Disabling for now.
 346          */
 347         /*.flags          = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
 348         .banks            = 1,
 349         .pwrsts_mem_ret   = {
 350                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
 351         },
 352         .pwrsts_mem_on    = {
 353                 [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
 354         },
 355 };
 356
 357 static struct powerdomain dpll1_pwrdm = {
 358         .name           = "dpll1_pwrdm",
 359         .prcm_offs      = MPU_MOD,
 360         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 361 };
 362
 363 static struct powerdomain dpll2_pwrdm = {
 364         .name           = "dpll2_pwrdm",
 365         .prcm_offs      = OMAP3430_IVA2_MOD,
 366         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 367 };
 368
 369 static struct powerdomain dpll3_pwrdm = {
 370         .name           = "dpll3_pwrdm",
 371         .prcm_offs      = PLL_MOD,
 372         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 373 };
 374
 375 static struct powerdomain dpll4_pwrdm = {
 376         .name           = "dpll4_pwrdm",
 377         .prcm_offs      = PLL_MOD,
 378         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 379 };
 380
 381 static struct powerdomain dpll5_pwrdm = {
 382         .name           = "dpll5_pwrdm",
 383         .prcm_offs      = PLL_MOD,
 384         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 385 };
 386
 387
 388 #endif    /* CONFIG_ARCH_OMAP34XX */
 389
 390
 391 #endif