| commit | 1aa1d190b89541b94758420b000dd5f58e867557 | |
| author | Paul Walmsley <paul@pwsan.com> | |
| Mon, 15 Jun 2009 08:00:44 +0000 (15 02:00 -0600) | ||
| committer | paul <paul@twilight.(none)> | |
| Mon, 15 Jun 2009 08:00:44 +0000 (15 02:00 -0600) | ||
| tree | 72e82d7a90abd0159a30d5e5b62604447a3290c4 | treesnapshot (tar.gz zip) |
| parent | 4179f88d226abc21698b8f3bc6e2b1930c43e4f6 | commitdiff |
OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change
Program the SDRC_MR_0 register as well during SDRC clock changes.
This register allows selection of the memory CAS latency. Some SDRAM
chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency
at lower clock rates.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Program the SDRC_MR_0 register as well during SDRC clock changes.
This register allows selection of the memory CAS latency. Some SDRAM
chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency
at lower clock rates.
Signed-off-by: Paul Walmsley <paul@pwsan.com>