arch/arm/plat-s3c64xx/s3c6400-clock.c

   1 /* linux/arch/arm/plat-s3c64xx/s3c6400-clock.c
   2  *
   3  * Copyright 2008 Openmoko, Inc.
   4  * Copyright 2008 Simtec Electronics
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *      http://armlinux.simtec.co.uk/
   7  *
   8  * S3C6400 based common clock support
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13 */
  14
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17 #include <linux/kernel.h>
  18 #include <linux/list.h>
  19 #include <linux/errno.h>
  20 #include <linux/err.h>
  21 #include <linux/clk.h>
  22 #include <linux/sysdev.h>
  23 #include <linux/io.h>
  24
  25 #include <mach/hardware.h>
  26 #include <mach/map.h>
  27
  28 #include <plat/cpu-freq.h>
  29
  30 #include <plat/regs-clock.h>
  31 #include <plat/clock.h>
  32 #include <plat/cpu.h>
  33 #include <plat/pll.h>
  34
  35 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
  36  * ext_xtal_mux for want of an actual name from the manual.
  37 */
  38
  39 static struct clk clk_ext_xtal_mux = {
  40         .name           = "ext_xtal",
  41         .id             = -1,
  42 };
  43
  44 #define clk_fin_apll clk_ext_xtal_mux
  45 #define clk_fin_mpll clk_ext_xtal_mux
  46 #define clk_fin_epll clk_ext_xtal_mux
  47
  48 #define clk_fout_mpll   clk_mpll
  49
  50 struct clk_sources {
  51         unsigned int    nr_sources;
  52         struct clk      **sources;
  53 };
  54
  55 struct clksrc_clk {
  56         struct clk              clk;
  57         unsigned int            mask;
  58         unsigned int            shift;
  59
  60         struct clk_sources      *sources;
  61
  62         unsigned int            divider_shift;
  63         void __iomem            *reg_divider;
  64 };
  65
  66 static struct clk clk_fout_apll = {
  67         .name           = "fout_apll",
  68         .id             = -1,
  69 };
  70
  71 static struct clk *clk_src_apll_list[] = {
  72         [0] = &clk_fin_apll,
  73         [1] = &clk_fout_apll,
  74 };
  75
  76 static struct clk_sources clk_src_apll = {
  77         .sources        = clk_src_apll_list,
  78         .nr_sources     = ARRAY_SIZE(clk_src_apll_list),
  79 };
  80
  81 static struct clksrc_clk clk_mout_apll = {
  82         .clk    = {
  83                 .name           = "mout_apll",
  84                 .id             = -1,
  85         },
  86         .shift          = S3C6400_CLKSRC_APLL_MOUT_SHIFT,
  87         .mask           = S3C6400_CLKSRC_APLL_MOUT,
  88         .sources        = &clk_src_apll,
  89 };
  90
  91 static struct clk clk_fout_epll = {
  92         .name           = "fout_epll",
  93         .id             = -1,
  94 };
  95
  96 static struct clk *clk_src_epll_list[] = {
  97         [0] = &clk_fin_epll,
  98         [1] = &clk_fout_epll,
  99 };
 100
 101 static struct clk_sources clk_src_epll = {
 102         .sources        = clk_src_epll_list,
 103         .nr_sources     = ARRAY_SIZE(clk_src_epll_list),
 104 };
 105
 106 static struct clksrc_clk clk_mout_epll = {
 107         .clk    = {
 108                 .name           = "mout_epll",
 109                 .id             = -1,
 110         },
 111         .shift          = S3C6400_CLKSRC_EPLL_MOUT_SHIFT,
 112         .mask           = S3C6400_CLKSRC_EPLL_MOUT,
 113         .sources        = &clk_src_epll,
 114 };
 115
 116 static struct clk *clk_src_mpll_list[] = {
 117         [0] = &clk_fin_mpll,
 118         [1] = &clk_fout_mpll,
 119 };
 120
 121 static struct clk_sources clk_src_mpll = {
 122         .sources        = clk_src_mpll_list,
 123         .nr_sources     = ARRAY_SIZE(clk_src_mpll_list),
 124 };
 125
 126 static struct clksrc_clk clk_mout_mpll = {
 127         .clk = {
 128                 .name           = "mout_mpll",
 129                 .id             = -1,
 130         },
 131         .shift          = S3C6400_CLKSRC_MPLL_MOUT_SHIFT,
 132         .mask           = S3C6400_CLKSRC_MPLL_MOUT,
 133         .sources        = &clk_src_mpll,
 134 };
 135
 136 static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
 137 {
 138         unsigned long rate = clk_get_rate(clk->parent);
 139
 140         printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
 141
 142         if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
 143                 rate /= 2;
 144
 145         return rate;
 146 }
 147
 148 static struct clk clk_dout_mpll = {
 149         .name           = "dout_mpll",
 150         .id             = -1,
 151         .parent         = &clk_mout_mpll.clk,
 152         .get_rate       = s3c64xx_clk_doutmpll_get_rate,
 153 };
 154
 155 static struct clk *clkset_spi_mmc_list[] = {
 156         &clk_mout_epll.clk,
 157         &clk_dout_mpll,
 158         &clk_fin_epll,
 159         &clk_27m,
 160 };
 161
 162 static struct clk_sources clkset_spi_mmc = {
 163         .sources        = clkset_spi_mmc_list,
 164         .nr_sources     = ARRAY_SIZE(clkset_spi_mmc_list),
 165 };
 166
 167 static struct clk *clkset_irda_list[] = {
 168         &clk_mout_epll.clk,
 169         &clk_dout_mpll,
 170         NULL,
 171         &clk_27m,
 172 };
 173
 174 static struct clk_sources clkset_irda = {
 175         .sources        = clkset_irda_list,
 176         .nr_sources     = ARRAY_SIZE(clkset_irda_list),
 177 };
 178
 179 static struct clk *clkset_uart_list[] = {
 180         &clk_mout_epll.clk,
 181         &clk_dout_mpll,
 182         NULL,
 183         NULL
 184 };
 185
 186 static struct clk_sources clkset_uart = {
 187         .sources        = clkset_uart_list,
 188         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 189 };
 190
 191 static struct clk *clkset_uhost_list[] = {
 192         &clk_48m,
 193         &clk_mout_epll.clk,
 194         &clk_dout_mpll,
 195         &clk_fin_epll,
 196 };
 197
 198 static struct clk_sources clkset_uhost = {
 199         .sources        = clkset_uhost_list,
 200         .nr_sources     = ARRAY_SIZE(clkset_uhost_list),
 201 };
 202
 203
 204 /* The peripheral clocks are all controlled via clocksource followed
 205  * by an optional divider and gate stage. We currently roll this into
 206  * one clock which hides the intermediate clock from the mux.
 207  *
 208  * Note, the JPEG clock can only be an even divider...
 209  *
 210  * The scaler and LCD clocks depend on the S3C64XX version, and also
 211  * have a common parent divisor so are not included here.
 212  */
 213
 214 static inline struct clksrc_clk *to_clksrc(struct clk *clk)
 215 {
 216         return container_of(clk, struct clksrc_clk, clk);
 217 }
 218
 219 static unsigned long s3c64xx_getrate_clksrc(struct clk *clk)
 220 {
 221         struct clksrc_clk *sclk = to_clksrc(clk);
 222         unsigned long rate = clk_get_rate(clk->parent);
 223         u32 clkdiv = __raw_readl(sclk->reg_divider);
 224
 225         clkdiv >>= sclk->divider_shift;
 226         clkdiv &= 0xf;
 227         clkdiv++;
 228
 229         rate /= clkdiv;
 230         return rate;
 231 }
 232
 233 static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate)
 234 {
 235         struct clksrc_clk *sclk = to_clksrc(clk);
 236         void __iomem *reg = sclk->reg_divider;
 237         unsigned int div;
 238         u32 val;
 239
 240         rate = clk_round_rate(clk, rate);
 241         div = clk_get_rate(clk->parent) / rate;
 242         if (div > 16)
 243                 return -EINVAL;
 244
 245         val = __raw_readl(reg);
 246         val &= ~(0xf << sclk->shift);
 247         val |= (div - 1) << sclk->shift;
 248         __raw_writel(val, reg);
 249
 250         return 0;
 251 }
 252
 253 static int s3c64xx_setparent_clksrc(struct clk *clk, struct clk *parent)
 254 {
 255         struct clksrc_clk *sclk = to_clksrc(clk);
 256         struct clk_sources *srcs = sclk->sources;
 257         u32 clksrc = __raw_readl(S3C_CLK_SRC);
 258         int src_nr = -1;
 259         int ptr;
 260
 261         for (ptr = 0; ptr < srcs->nr_sources; ptr++)
 262                 if (srcs->sources[ptr] == parent) {
 263                         src_nr = ptr;
 264                         break;
 265                 }
 266
 267         if (src_nr >= 0) {
 268                 clksrc &= ~sclk->mask;
 269                 clksrc |= src_nr << sclk->shift;
 270
 271                 __raw_writel(clksrc, S3C_CLK_SRC);
 272                 return 0;
 273         }
 274
 275         return -EINVAL;
 276 }
 277
 278 static unsigned long s3c64xx_roundrate_clksrc(struct clk *clk,
 279                                               unsigned long rate)
 280 {
 281         unsigned long parent_rate = clk_get_rate(clk->parent);
 282         int div;
 283
 284         if (rate > parent_rate)
 285                 rate = parent_rate;
 286         else {
 287                 div = rate / parent_rate;
 288
 289                 if (div == 0)
 290                         div = 1;
 291                 if (div > 16)
 292                         div = 16;
 293
 294                 rate = parent_rate / div;
 295         }
 296
 297         return rate;
 298 }
 299
 300 static struct clksrc_clk clk_mmc0 = {
 301         .clk    = {
 302                 .name           = "mmc_bus",
 303                 .id             = 0,
 304                 .ctrlbit        = S3C_CLKCON_SCLK_MMC0,
 305                 .enable         = s3c64xx_sclk_ctrl,
 306                 .set_parent     = s3c64xx_setparent_clksrc,
 307                 .get_rate       = s3c64xx_getrate_clksrc,
 308                 .set_rate       = s3c64xx_setrate_clksrc,
 309                 .round_rate     = s3c64xx_roundrate_clksrc,
 310         },
 311         .shift          = S3C6400_CLKSRC_MMC0_SHIFT,
 312         .mask           = S3C6400_CLKSRC_MMC0_MASK,
 313         .sources        = &clkset_spi_mmc,
 314         .divider_shift  = S3C6400_CLKDIV1_MMC0_SHIFT,
 315         .reg_divider    = S3C_CLK_DIV1,
 316 };
 317
 318 static struct clksrc_clk clk_mmc1 = {
 319         .clk    = {
 320                 .name           = "mmc_bus",
 321                 .id             = 1,
 322                 .ctrlbit        = S3C_CLKCON_SCLK_MMC1,
 323                 .enable         = s3c64xx_sclk_ctrl,
 324                 .get_rate       = s3c64xx_getrate_clksrc,
 325                 .set_rate       = s3c64xx_setrate_clksrc,
 326                 .set_parent     = s3c64xx_setparent_clksrc,
 327                 .round_rate     = s3c64xx_roundrate_clksrc,
 328         },
 329         .shift          = S3C6400_CLKSRC_MMC1_SHIFT,
 330         .mask           = S3C6400_CLKSRC_MMC1_MASK,
 331         .sources        = &clkset_spi_mmc,
 332         .divider_shift  = S3C6400_CLKDIV1_MMC1_SHIFT,
 333         .reg_divider    = S3C_CLK_DIV1,
 334 };
 335
 336 static struct clksrc_clk clk_mmc2 = {
 337         .clk    = {
 338                 .name           = "mmc_bus",
 339                 .id             = 2,
 340                 .ctrlbit        = S3C_CLKCON_SCLK_MMC2,
 341                 .enable         = s3c64xx_sclk_ctrl,
 342                 .get_rate       = s3c64xx_getrate_clksrc,
 343                 .set_rate       = s3c64xx_setrate_clksrc,
 344                 .set_parent     = s3c64xx_setparent_clksrc,
 345                 .round_rate     = s3c64xx_roundrate_clksrc,
 346         },
 347         .shift          = S3C6400_CLKSRC_MMC2_SHIFT,
 348         .mask           = S3C6400_CLKSRC_MMC2_MASK,
 349         .sources        = &clkset_spi_mmc,
 350         .divider_shift  = S3C6400_CLKDIV1_MMC2_SHIFT,
 351         .reg_divider    = S3C_CLK_DIV1,
 352 };
 353
 354 static struct clksrc_clk clk_usbhost = {
 355         .clk    = {
 356                 .name           = "usb-bus-host",
 357                 .id             = -1,
 358                 .ctrlbit        = S3C_CLKCON_SCLK_UHOST,
 359                 .enable         = s3c64xx_sclk_ctrl,
 360                 .set_parent     = s3c64xx_setparent_clksrc,
 361                 .get_rate       = s3c64xx_getrate_clksrc,
 362                 .set_rate       = s3c64xx_setrate_clksrc,
 363                 .round_rate     = s3c64xx_roundrate_clksrc,
 364         },
 365         .shift          = S3C6400_CLKSRC_UHOST_SHIFT,
 366         .mask           = S3C6400_CLKSRC_UHOST_MASK,
 367         .sources        = &clkset_uhost,
 368         .divider_shift  = S3C6400_CLKDIV1_UHOST_SHIFT,
 369         .reg_divider    = S3C_CLK_DIV1,
 370 };
 371
 372 static struct clksrc_clk clk_uart_uclk1 = {
 373         .clk    = {
 374                 .name           = "uclk1",
 375                 .id             = -1,
 376                 .ctrlbit        = S3C_CLKCON_SCLK_UART,
 377                 .enable         = s3c64xx_sclk_ctrl,
 378                 .set_parent     = s3c64xx_setparent_clksrc,
 379                 .get_rate       = s3c64xx_getrate_clksrc,
 380                 .set_rate       = s3c64xx_setrate_clksrc,
 381                 .round_rate     = s3c64xx_roundrate_clksrc,
 382         },
 383         .shift          = S3C6400_CLKSRC_UART_SHIFT,
 384         .mask           = S3C6400_CLKSRC_UART_MASK,
 385         .sources        = &clkset_uart,
 386         .divider_shift  = S3C6400_CLKDIV2_UART_SHIFT,
 387         .reg_divider    = S3C_CLK_DIV2,
 388 };
 389
 390 /* Where does UCLK0 come from? */
 391
 392 static struct clksrc_clk clk_spi0 = {
 393         .clk    = {
 394                 .name           = "spi-bus",
 395                 .id             = 0,
 396                 .ctrlbit        = S3C_CLKCON_SCLK_SPI0,
 397                 .enable         = s3c64xx_sclk_ctrl,
 398                 .set_parent     = s3c64xx_setparent_clksrc,
 399                 .get_rate       = s3c64xx_getrate_clksrc,
 400                 .set_rate       = s3c64xx_setrate_clksrc,
 401                 .round_rate     = s3c64xx_roundrate_clksrc,
 402         },
 403         .shift          = S3C6400_CLKSRC_SPI0_SHIFT,
 404         .mask           = S3C6400_CLKSRC_SPI0_MASK,
 405         .sources        = &clkset_spi_mmc,
 406         .divider_shift  = S3C6400_CLKDIV2_SPI0_SHIFT,
 407         .reg_divider    = S3C_CLK_DIV2,
 408 };
 409
 410 static struct clksrc_clk clk_spi1 = {
 411         .clk    = {
 412                 .name           = "spi-bus",
 413                 .id             = 1,
 414                 .ctrlbit        = S3C_CLKCON_SCLK_SPI1,
 415                 .enable         = s3c64xx_sclk_ctrl,
 416                 .set_parent     = s3c64xx_setparent_clksrc,
 417                 .get_rate       = s3c64xx_getrate_clksrc,
 418                 .set_rate       = s3c64xx_setrate_clksrc,
 419                 .round_rate     = s3c64xx_roundrate_clksrc,
 420         },
 421         .shift          = S3C6400_CLKSRC_SPI1_SHIFT,
 422         .mask           = S3C6400_CLKSRC_SPI1_MASK,
 423         .sources        = &clkset_spi_mmc,
 424         .divider_shift  = S3C6400_CLKDIV2_SPI1_SHIFT,
 425         .reg_divider    = S3C_CLK_DIV2,
 426 };
 427
 428 static struct clk clk_iis_cd0 = {
 429         .name           = "iis_cdclk0",
 430         .id             = -1,
 431 };
 432
 433 static struct clk clk_iis_cd1 = {
 434         .name           = "iis_cdclk1",
 435         .id             = -1,
 436 };
 437
 438 static struct clk clk_pcm_cd = {
 439         .name           = "pcm_cdclk",
 440         .id             = -1,
 441 };
 442
 443 static struct clk *clkset_audio0_list[] = {
 444         [0] = &clk_mout_epll.clk,
 445         [1] = &clk_dout_mpll,
 446         [2] = &clk_fin_epll,
 447         [3] = &clk_iis_cd0,
 448         [4] = &clk_pcm_cd,
 449 };
 450
 451 static struct clk_sources clkset_audio0 = {
 452         .sources        = clkset_audio0_list,
 453         .nr_sources     = ARRAY_SIZE(clkset_audio0_list),
 454 };
 455
 456 static struct clksrc_clk clk_audio0 = {
 457         .clk    = {
 458                 .name           = "audio-bus",
 459                 .id             = 0,
 460                 .ctrlbit        = S3C_CLKCON_SCLK_AUDIO0,
 461                 .enable         = s3c64xx_sclk_ctrl,
 462                 .set_parent     = s3c64xx_setparent_clksrc,
 463                 .get_rate       = s3c64xx_getrate_clksrc,
 464                 .set_rate       = s3c64xx_setrate_clksrc,
 465                 .round_rate     = s3c64xx_roundrate_clksrc,
 466         },
 467         .shift          = S3C6400_CLKSRC_AUDIO0_SHIFT,
 468         .mask           = S3C6400_CLKSRC_AUDIO0_MASK,
 469         .sources        = &clkset_audio0,
 470         .divider_shift  = S3C6400_CLKDIV2_AUDIO0_SHIFT,
 471         .reg_divider    = S3C_CLK_DIV2,
 472 };
 473
 474 static struct clk *clkset_audio1_list[] = {
 475         [0] = &clk_mout_epll.clk,
 476         [1] = &clk_dout_mpll,
 477         [2] = &clk_fin_epll,
 478         [3] = &clk_iis_cd1,
 479         [4] = &clk_pcm_cd,
 480 };
 481
 482 static struct clk_sources clkset_audio1 = {
 483         .sources        = clkset_audio1_list,
 484         .nr_sources     = ARRAY_SIZE(clkset_audio1_list),
 485 };
 486
 487 static struct clksrc_clk clk_audio1 = {
 488         .clk    = {
 489                 .name           = "audio-bus",
 490                 .id             = 1,
 491                 .ctrlbit        = S3C_CLKCON_SCLK_AUDIO1,
 492                 .enable         = s3c64xx_sclk_ctrl,
 493                 .set_parent     = s3c64xx_setparent_clksrc,
 494                 .get_rate       = s3c64xx_getrate_clksrc,
 495                 .set_rate       = s3c64xx_setrate_clksrc,
 496                 .round_rate     = s3c64xx_roundrate_clksrc,
 497         },
 498         .shift          = S3C6400_CLKSRC_AUDIO1_SHIFT,
 499         .mask           = S3C6400_CLKSRC_AUDIO1_MASK,
 500         .sources        = &clkset_audio1,
 501         .divider_shift  = S3C6400_CLKDIV2_AUDIO1_SHIFT,
 502         .reg_divider    = S3C_CLK_DIV2,
 503 };
 504
 505 static struct clksrc_clk clk_irda = {
 506         .clk    = {
 507                 .name           = "irda-bus",
 508                 .id             = 0,
 509                 .ctrlbit        = S3C_CLKCON_SCLK_IRDA,
 510                 .enable         = s3c64xx_sclk_ctrl,
 511                 .set_parent     = s3c64xx_setparent_clksrc,
 512                 .get_rate       = s3c64xx_getrate_clksrc,
 513                 .set_rate       = s3c64xx_setrate_clksrc,
 514                 .round_rate     = s3c64xx_roundrate_clksrc,
 515         },
 516         .shift          = S3C6400_CLKSRC_IRDA_SHIFT,
 517         .mask           = S3C6400_CLKSRC_IRDA_MASK,
 518         .sources        = &clkset_irda,
 519         .divider_shift  = S3C6400_CLKDIV2_IRDA_SHIFT,
 520         .reg_divider    = S3C_CLK_DIV2,
 521 };
 522
 523 /* Clock initialisation code */
 524
 525 static struct clksrc_clk *init_parents[] = {
 526         &clk_mout_apll,
 527         &clk_mout_epll,
 528         &clk_mout_mpll,
 529         &clk_mmc0,
 530         &clk_mmc1,
 531         &clk_mmc2,
 532         &clk_usbhost,
 533         &clk_uart_uclk1,
 534         &clk_spi0,
 535         &clk_spi1,
 536         &clk_audio0,
 537         &clk_audio1,
 538         &clk_irda,
 539 };
 540
 541 static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk)
 542 {
 543         struct clk_sources *srcs = clk->sources;
 544         u32 clksrc = __raw_readl(S3C_CLK_SRC);
 545
 546         clksrc &= clk->mask;
 547         clksrc >>= clk->shift;
 548
 549         if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
 550                 printk(KERN_ERR "%s: bad source %d\n",
 551                        clk->clk.name, clksrc);
 552                 return;
 553         }
 554
 555         clk->clk.parent = srcs->sources[clksrc];
 556
 557         printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
 558                clk->clk.name, clk->clk.parent->name, clksrc,
 559                clk_get_rate(&clk->clk));
 560 }
 561
 562 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
 563
 564 void __init_or_cpufreq s3c6400_setup_clocks(void)
 565 {
 566         struct clk *xtal_clk;
 567         unsigned long xtal;
 568         unsigned long fclk;
 569         unsigned long hclk;
 570         unsigned long hclk2;
 571         unsigned long pclk;
 572         unsigned long epll;
 573         unsigned long apll;
 574         unsigned long mpll;
 575         unsigned int ptr;
 576         u32 clkdiv0;
 577
 578         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
 579
 580         clkdiv0 = __raw_readl(S3C_CLK_DIV0);
 581         printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
 582
 583         xtal_clk = clk_get(NULL, "xtal");
 584         BUG_ON(IS_ERR(xtal_clk));
 585
 586         xtal = clk_get_rate(xtal_clk);
 587         clk_put(xtal_clk);
 588
 589         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
 590
 591         epll = s3c6400_get_epll(xtal);
 592         mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
 593         apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
 594
 595         fclk = mpll;
 596
 597         printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
 598                apll, mpll, epll);
 599
 600         hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
 601         hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
 602         pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
 603
 604         printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
 605                hclk2, hclk, pclk);
 606
 607         clk_fout_mpll.rate = mpll;
 608         clk_fout_epll.rate = epll;
 609         clk_fout_apll.rate = apll;
 610
 611         clk_h.rate = hclk;
 612         clk_p.rate = pclk;
 613         clk_f.rate = fclk;
 614
 615         for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
 616                 s3c6400_set_clksrc(init_parents[ptr]);
 617 }
 618
 619 static struct clk *clks[] __initdata = {
 620         &clk_ext_xtal_mux,
 621         &clk_iis_cd0,
 622         &clk_iis_cd1,
 623         &clk_pcm_cd,
 624         &clk_mout_epll.clk,
 625         &clk_fout_epll,
 626         &clk_mout_mpll.clk,
 627         &clk_dout_mpll,
 628         &clk_mmc0.clk,
 629         &clk_mmc1.clk,
 630         &clk_mmc2.clk,
 631         &clk_usbhost.clk,
 632         &clk_uart_uclk1.clk,
 633         &clk_spi0.clk,
 634         &clk_spi1.clk,
 635         &clk_audio0.clk,
 636         &clk_audio1.clk,
 637         &clk_irda.clk,
 638 };
 639
 640 void __init s3c6400_register_clocks(void)
 641 {
 642         struct clk *clkp;
 643         int ret;
 644         int ptr;
 645
 646         for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
 647                 clkp = clks[ptr];
 648                 ret = s3c24xx_register_clock(clkp);
 649                 if (ret < 0) {
 650                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 651                                clkp->name, ret);
 652                 }
 653         }
 654
 655         clk_mpll.parent = &clk_mout_mpll.clk;
 656         clk_epll.parent = &clk_mout_epll.clk;
 657 }