repo init
[linux-rt-nao.git] / arch / blackfin / include / asm / bfin_sport.h
blob65a651db5b072bf72d22b544ac9d3f1b7a809056
1 /*
2 * bfin_sport.h - userspace header for bfin sport driver
4 * Copyright 2004-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
7 */
9 #ifndef __BFIN_SPORT_H__
10 #define __BFIN_SPORT_H__
12 #define SPORT_MAJOR 237
13 #define SPORT_NR_DEVS 2
15 /* Sport mode: it can be set to TDM, i2s or others */
16 #define NORM_MODE 0x0
17 #define TDM_MODE 0x1
18 #define I2S_MODE 0x2
20 /* Data format, normal, a-law or u-law */
21 #define NORM_FORMAT 0x0
22 #define ALAW_FORMAT 0x2
23 #define ULAW_FORMAT 0x3
25 /* Function driver which use sport must initialize the structure */
26 struct sport_config {
27 /* TDM (multichannels), I2S or other mode */
28 unsigned int mode:3;
30 /* if TDM mode is selected, channels must be set */
31 int channels; /* Must be in 8 units */
32 unsigned int frame_delay:4; /* Delay between frame sync pulse and first bit */
34 /* I2S mode */
35 unsigned int right_first:1; /* Right stereo channel first */
37 /* In mormal mode, the following item need to be set */
38 unsigned int lsb_first:1; /* order of transmit or receive data */
39 unsigned int fsync:1; /* Frame sync required */
40 unsigned int data_indep:1; /* data independent frame sync generated */
41 unsigned int act_low:1; /* Active low TFS */
42 unsigned int late_fsync:1; /* Late frame sync */
43 unsigned int tckfe:1;
44 unsigned int sec_en:1; /* Secondary side enabled */
46 /* Choose clock source */
47 unsigned int int_clk:1; /* Internal or external clock */
49 /* If external clock is used, the following fields are ignored */
50 int serial_clk;
51 int fsync_clk;
53 unsigned int data_format:2; /* Normal, u-law or a-law */
55 int word_len; /* How length of the word in bits, 3-32 bits */
56 int dma_enabled;
59 /* Userspace interface */
60 #define SPORT_IOC_MAGIC 'P'
61 #define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config)
63 #ifdef __KERNEL__
65 struct sport_register {
66 unsigned short tcr1;
67 unsigned short reserved0;
68 unsigned short tcr2;
69 unsigned short reserved1;
70 unsigned short tclkdiv;
71 unsigned short reserved2;
72 unsigned short tfsdiv;
73 unsigned short reserved3;
74 unsigned long tx;
75 unsigned long reserved_l0;
76 unsigned long rx;
77 unsigned long reserved_l1;
78 unsigned short rcr1;
79 unsigned short reserved4;
80 unsigned short rcr2;
81 unsigned short reserved5;
82 unsigned short rclkdiv;
83 unsigned short reserved6;
84 unsigned short rfsdiv;
85 unsigned short reserved7;
86 unsigned short stat;
87 unsigned short reserved8;
88 unsigned short chnl;
89 unsigned short reserved9;
90 unsigned short mcmc1;
91 unsigned short reserved10;
92 unsigned short mcmc2;
93 unsigned short reserved11;
94 unsigned long mtcs0;
95 unsigned long mtcs1;
96 unsigned long mtcs2;
97 unsigned long mtcs3;
98 unsigned long mrcs0;
99 unsigned long mrcs1;
100 unsigned long mrcs2;
101 unsigned long mrcs3;
104 struct sport_dev {
105 struct cdev cdev; /* Char device structure */
107 int sport_num;
109 int dma_rx_chan;
110 int dma_tx_chan;
112 int rx_irq;
113 unsigned char *rx_buf; /* Buffer store the received data */
114 int rx_len; /* How many bytes will be received */
115 int rx_received; /* How many bytes has been received */
117 int tx_irq;
118 const unsigned char *tx_buf;
119 int tx_len;
120 int tx_sent;
122 int sport_err_irq;
124 struct mutex mutex; /* mutual exclusion semaphore */
125 struct task_struct *task;
127 wait_queue_head_t waitq;
128 int wait_con;
129 struct sport_register *regs;
130 struct sport_config config;
133 #endif
135 #define SPORT_TCR1 0
136 #define SPORT_TCR2 1
137 #define SPORT_TCLKDIV 2
138 #define SPORT_TFSDIV 3
139 #define SPORT_RCR1 8
140 #define SPORT_RCR2 9
141 #define SPORT_RCLKDIV 10
142 #define SPORT_RFSDIV 11
143 #define SPORT_CHANNEL 13
144 #define SPORT_MCMC1 14
145 #define SPORT_MCMC2 15
146 #define SPORT_MTCS0 16
147 #define SPORT_MTCS1 17
148 #define SPORT_MTCS2 18
149 #define SPORT_MTCS3 19
150 #define SPORT_MRCS0 20
151 #define SPORT_MRCS1 21
152 #define SPORT_MRCS2 22
153 #define SPORT_MRCS3 23
155 #endif