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[linux-rt-nao.git] / drivers / net / ixgbe / ixgbe_82598.c
blobad5699d9ab0dacaaecf5fd6069b1268ff07d5e9c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34
35 #define IXGBE_82598_MAX_TX_QUEUES 32
36 #define IXGBE_82598_MAX_RX_QUEUES 64
37 #define IXGBE_82598_RAR_ENTRIES 16
38 #define IXGBE_82598_MC_TBL_SIZE 128
39 #define IXGBE_82598_VFT_TBL_SIZE 128
40
41 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
43 bool *autoneg);
44 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
45 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
46 ixgbe_link_speed speed,
47 bool autoneg,
48 bool autoneg_wait_to_complete);
49 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
50 u8 *eeprom_data);
51
52 /**
53 */
54 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
55 {
56 struct ixgbe_mac_info *mac = &hw->mac;
57 struct ixgbe_phy_info *phy = &hw->phy;
58 s32 ret_val = 0;
59 u16 list_offset, data_offset;
60
61 /* Call PHY identify routine to get the phy type */
62 ixgbe_identify_phy_generic(hw);
63
64 /* PHY Init */
65 switch (phy->type) {
66 case ixgbe_phy_tn:
67 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
68 phy->ops.get_firmware_version =
69 &ixgbe_get_phy_firmware_version_tnx;
70 break;
71 case ixgbe_phy_nl:
72 phy->ops.reset = &ixgbe_reset_phy_nl;
73
74 /* Call SFP+ identify routine to get the SFP+ module type */
75 ret_val = phy->ops.identify_sfp(hw);
76 if (ret_val != 0)
77 goto out;
78 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
79 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
80 goto out;
81 }
82
83 /* Check to see if SFP+ module is supported */
84 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
85 &list_offset,
86 &data_offset);
87 if (ret_val != 0) {
88 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
89 goto out;
90 }
91 break;
92 default:
93 break;
94 }
95
96 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
97 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
98 mac->ops.setup_link_speed =
99 &ixgbe_setup_copper_link_speed_82598;
100 mac->ops.get_link_capabilities =
101 &ixgbe_get_copper_link_capabilities_82598;
102 }
103
104 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
105 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
106 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
107 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
108 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
109
110 out:
111 return ret_val;
112 }
113
114 /**
115 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
116 * @hw: pointer to hardware structure
117 * @speed: pointer to link speed
118 * @autoneg: boolean auto-negotiation value
119 *
120 * Determines the link capabilities by reading the AUTOC register.
121 **/
122 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
123 ixgbe_link_speed *speed,
124 bool *autoneg)
125 {
126 s32 status = 0;
127 s32 autoc_reg;
128
129 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
130
131 if (hw->mac.link_settings_loaded) {
132 autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE;
133 autoc_reg &= ~IXGBE_AUTOC_LMS_MASK;
134 autoc_reg |= hw->mac.link_attach_type;
135 autoc_reg |= hw->mac.link_mode_select;
136 }
137
138 switch (autoc_reg & IXGBE_AUTOC_LMS_MASK) {
139 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
140 *speed = IXGBE_LINK_SPEED_1GB_FULL;
141 *autoneg = false;
142 break;
143
144 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
145 *speed = IXGBE_LINK_SPEED_10GB_FULL;
146 *autoneg = false;
147 break;
148
149 case IXGBE_AUTOC_LMS_1G_AN:
150 *speed = IXGBE_LINK_SPEED_1GB_FULL;
151 *autoneg = true;
152 break;
153
154 case IXGBE_AUTOC_LMS_KX4_AN:
155 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
156 *speed = IXGBE_LINK_SPEED_UNKNOWN;
157 if (autoc_reg & IXGBE_AUTOC_KX4_SUPP)
158 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
159 if (autoc_reg & IXGBE_AUTOC_KX_SUPP)
160 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
161 *autoneg = true;
162 break;
163
164 default:
165 status = IXGBE_ERR_LINK_SETUP;
166 break;
167 }
168
169 return status;
170 }
171
172 /**
173 * ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities
174 * @hw: pointer to hardware structure
175 * @speed: pointer to link speed
176 * @autoneg: boolean auto-negotiation value
177 *
178 * Determines the link capabilities by reading the AUTOC register.
179 **/
180 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
181 ixgbe_link_speed *speed,
182 bool *autoneg)
183 {
184 s32 status = IXGBE_ERR_LINK_SETUP;
185 u16 speed_ability;
186
187 *speed = 0;
188 *autoneg = true;
189
190 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
191 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
192 &speed_ability);
193
194 if (status == 0) {
195 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
196 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
197 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
198 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
199 }
200
201 return status;
202 }
203
204 /**
205 * ixgbe_get_media_type_82598 - Determines media type
206 * @hw: pointer to hardware structure
207 *
208 * Returns the media type (fiber, copper, backplane)
209 **/
210 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
211 {
212 enum ixgbe_media_type media_type;
213
214 /* Media type for I82598 is based on device ID */
215 switch (hw->device_id) {
216 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
217 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
218 case IXGBE_DEV_ID_82598EB_CX4:
219 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
220 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
221 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
222 case IXGBE_DEV_ID_82598EB_XF_LR:
223 case IXGBE_DEV_ID_82598EB_SFP_LOM:
224 media_type = ixgbe_media_type_fiber;
225 break;
226 case IXGBE_DEV_ID_82598AT:
227 media_type = ixgbe_media_type_copper;
228 break;
229 default:
230 media_type = ixgbe_media_type_unknown;
231 break;
232 }
233
234 return media_type;
235 }
236
237 /**
238 * ixgbe_setup_fc_82598 - Configure flow control settings
239 * @hw: pointer to hardware structure
240 * @packetbuf_num: packet buffer number (0-7)
241 *
242 * Configures the flow control settings based on SW configuration. This
243 * function is used for 802.3x flow control configuration only.
244 **/
245 static s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
246 {
247 u32 frctl_reg;
248 u32 rmcs_reg;
249
250 if (packetbuf_num < 0 || packetbuf_num > 7) {
251 hw_dbg(hw, "Invalid packet buffer number [%d], expected range is"
252 " 0-7\n", packetbuf_num);
253 }
254
255 frctl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
256 frctl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
257
258 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
259 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
260
261 /*
262 * 10 gig parts do not have a word in the EEPROM to determine the
263 * default flow control setting, so we explicitly set it to full.
264 */
265 if (hw->fc.type == ixgbe_fc_default)
266 hw->fc.type = ixgbe_fc_full;
267
268 /*
269 * We want to save off the original Flow Control configuration just in
270 * case we get disconnected and then reconnected into a different hub
271 * or switch with different Flow Control capabilities.
272 */
273 hw->fc.original_type = hw->fc.type;
274
275 /*
276 * The possible values of the "flow_control" parameter are:
277 * 0: Flow control is completely disabled
278 * 1: Rx flow control is enabled (we can receive pause frames but not
279 * send pause frames).
280 * 2: Tx flow control is enabled (we can send pause frames but we do not
281 * support receiving pause frames)
282 * 3: Both Rx and Tx flow control (symmetric) are enabled.
283 * other: Invalid.
284 */
285 switch (hw->fc.type) {
286 case ixgbe_fc_none:
287 break;
288 case ixgbe_fc_rx_pause:
289 /*
290 * Rx Flow control is enabled,
291 * and Tx Flow control is disabled.
292 */
293 frctl_reg |= IXGBE_FCTRL_RFCE;
294 break;
295 case ixgbe_fc_tx_pause:
296 /*
297 * Tx Flow control is enabled, and Rx Flow control is disabled,
298 * by a software over-ride.
299 */
300 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
301 break;
302 case ixgbe_fc_full:
303 /*
304 * Flow control (both Rx and Tx) is enabled by a software
305 * over-ride.
306 */
307 frctl_reg |= IXGBE_FCTRL_RFCE;
308 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
309 break;
310 default:
311 /* We should never get here. The value should be 0-3. */
312 hw_dbg(hw, "Flow control param set incorrectly\n");
313 break;
314 }
315
316 /* Enable 802.3x based flow control settings. */
317 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, frctl_reg);
318 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
319
320 /*
321 * Check for invalid software configuration, zeros are completely
322 * invalid for all parameters used past this point, and if we enable
323 * flow control with zero water marks, we blast flow control packets.
324 */
325 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
326 hw_dbg(hw, "Flow control structure initialized incorrectly\n");
327 return IXGBE_ERR_INVALID_LINK_SETTINGS;
328 }
329
330 /*
331 * We need to set up the Receive Threshold high and low water
332 * marks as well as (optionally) enabling the transmission of
333 * XON frames.
334 */
335 if (hw->fc.type & ixgbe_fc_tx_pause) {
336 if (hw->fc.send_xon) {
337 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
338 (hw->fc.low_water | IXGBE_FCRTL_XONE));
339 } else {
340 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
341 hw->fc.low_water);
342 }
343 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
344 (hw->fc.high_water)|IXGBE_FCRTH_FCEN);
345 }
346
347 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(0), hw->fc.pause_time);
348 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
349
350 return 0;
351 }
352
353 /**
354 * ixgbe_setup_mac_link_82598 - Configures MAC link settings
355 * @hw: pointer to hardware structure
356 *
357 * Configures link settings based on values in the ixgbe_hw struct.
358 * Restarts the link. Performs autonegotiation if needed.
359 **/
360 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
361 {
362 u32 autoc_reg;
363 u32 links_reg;
364 u32 i;
365 s32 status = 0;
366
367 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
368
369 if (hw->mac.link_settings_loaded) {
370 autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE;
371 autoc_reg &= ~IXGBE_AUTOC_LMS_MASK;
372 autoc_reg |= hw->mac.link_attach_type;
373 autoc_reg |= hw->mac.link_mode_select;
374
375 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
376 IXGBE_WRITE_FLUSH(hw);
377 msleep(50);
378 }
379
380 /* Restart link */
381 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
382 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
383
384 /* Only poll for autoneg to complete if specified to do so */
385 if (hw->phy.autoneg_wait_to_complete) {
386 if (hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN ||
387 hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
388 links_reg = 0; /* Just in case Autoneg time = 0 */
389 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
390 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
391 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
392 break;
393 msleep(100);
394 }
395 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
396 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
397 hw_dbg(hw, "Autonegotiation did not complete.\n");
398 }
399 }
400 }
401
402 /*
403 * We want to save off the original Flow Control configuration just in
404 * case we get disconnected and then reconnected into a different hub
405 * or switch with different Flow Control capabilities.
406 */
407 hw->fc.original_type = hw->fc.type;
408 ixgbe_setup_fc_82598(hw, 0);
409
410 /* Add delay to filter out noises during initial link setup */
411 msleep(50);
412
413 return status;
414 }
415
416 /**
417 * ixgbe_check_mac_link_82598 - Get link/speed status
418 * @hw: pointer to hardware structure
419 * @speed: pointer to link speed
420 * @link_up: true is link is up, false otherwise
421 * @link_up_wait_to_complete: bool used to wait for link up or not
422 *
423 * Reads the links register to determine if link is up and the current speed
424 **/
425 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
426 ixgbe_link_speed *speed, bool *link_up,
427 bool link_up_wait_to_complete)
428 {
429 u32 links_reg;
430 u32 i;
431 u16 link_reg, adapt_comp_reg;
432
433 /*
434 * SERDES PHY requires us to read link status from register 0xC79F.
435 * Bit 0 set indicates link is up/ready; clear indicates link down.
436 * 0xC00C is read to check that the XAUI lanes are active. Bit 0
437 * clear indicates active; set indicates inactive.
438 */
439 if (hw->phy.type == ixgbe_phy_nl) {
440 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
441 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
442 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
443 &adapt_comp_reg);
444 if (link_up_wait_to_complete) {
445 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
446 if ((link_reg & 1) &&
447 ((adapt_comp_reg & 1) == 0)) {
448 *link_up = true;
449 break;
450 } else {
451 *link_up = false;
452 }
453 msleep(100);
454 hw->phy.ops.read_reg(hw, 0xC79F,
455 IXGBE_TWINAX_DEV,
456 &link_reg);
457 hw->phy.ops.read_reg(hw, 0xC00C,
458 IXGBE_TWINAX_DEV,
459 &adapt_comp_reg);
460 }
461 } else {
462 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
463 *link_up = true;
464 else
465 *link_up = false;
466 }
467
468 if (*link_up == false)
469 goto out;
470 }
471
472 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
473 if (link_up_wait_to_complete) {
474 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
475 if (links_reg & IXGBE_LINKS_UP) {
476 *link_up = true;
477 break;
478 } else {
479 *link_up = false;
480 }
481 msleep(100);
482 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
483 }
484 } else {
485 if (links_reg & IXGBE_LINKS_UP)
486 *link_up = true;
487 else
488 *link_up = false;
489 }
490
491 if (links_reg & IXGBE_LINKS_SPEED)
492 *speed = IXGBE_LINK_SPEED_10GB_FULL;
493 else
494 *speed = IXGBE_LINK_SPEED_1GB_FULL;
495
496 out:
497 return 0;
498 }
499
500
501 /**
502 * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
503 * @hw: pointer to hardware structure
504 * @speed: new link speed
505 * @autoneg: true if auto-negotiation enabled
506 * @autoneg_wait_to_complete: true if waiting is needed to complete
507 *
508 * Set the link speed in the AUTOC register and restarts link.
509 **/
510 static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
511 ixgbe_link_speed speed, bool autoneg,
512 bool autoneg_wait_to_complete)
513 {
514 s32 status = 0;
515
516 /* If speed is 10G, then check for CX4 or XAUI. */
517 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
518 (!(hw->mac.link_attach_type & IXGBE_AUTOC_10G_KX4))) {
519 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
520 } else if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && (!autoneg)) {
521 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
522 } else if (autoneg) {
523 /* BX mode - Autonegotiate 1G */
524 if (!(hw->mac.link_attach_type & IXGBE_AUTOC_1G_PMA_PMD))
525 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_AN;
526 else /* KX/KX4 mode */
527 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN_1G_AN;
528 } else {
529 status = IXGBE_ERR_LINK_SETUP;
530 }
531
532 if (status == 0) {
533 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete;
534
535 hw->mac.link_settings_loaded = true;
536 /*
537 * Setup and restart the link based on the new values in
538 * ixgbe_hw This will write the AUTOC register based on the new
539 * stored values
540 */
541 ixgbe_setup_mac_link_82598(hw);
542 }
543
544 return status;
545 }
546
547
548 /**
549 * ixgbe_setup_copper_link_82598 - Setup copper link settings
550 * @hw: pointer to hardware structure
551 *
552 * Configures link settings based on values in the ixgbe_hw struct.
553 * Restarts the link. Performs autonegotiation if needed. Restart
554 * phy and wait for autonegotiate to finish. Then synchronize the
555 * MAC and PHY.
556 **/
557 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
558 {
559 s32 status;
560
561 /* Restart autonegotiation on PHY */
562 status = hw->phy.ops.setup_link(hw);
563
564 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */
565 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX);
566 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN;
567
568 /* Set up MAC */
569 ixgbe_setup_mac_link_82598(hw);
570
571 return status;
572 }
573
574 /**
575 * ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
576 * @hw: pointer to hardware structure
577 * @speed: new link speed
578 * @autoneg: true if autonegotiation enabled
579 * @autoneg_wait_to_complete: true if waiting is needed to complete
580 *
581 * Sets the link speed in the AUTOC register in the MAC and restarts link.
582 **/
583 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
584 ixgbe_link_speed speed,
585 bool autoneg,
586 bool autoneg_wait_to_complete)
587 {
588 s32 status;
589
590 /* Setup the PHY according to input speed */
591 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
592 autoneg_wait_to_complete);
593
594 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */
595 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX);
596 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN;
597
598 /* Set up MAC */
599 ixgbe_setup_mac_link_82598(hw);
600
601 return status;
602 }
603
604 /**
605 * ixgbe_reset_hw_82598 - Performs hardware reset
606 * @hw: pointer to hardware structure
607 *
608 * Resets the hardware by resetting the transmit and receive units, masks and
609 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
610 * reset.
611 **/
612 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
613 {
614 s32 status = 0;
615 u32 ctrl;
616 u32 gheccr;
617 u32 i;
618 u32 autoc;
619 u8 analog_val;
620
621 /* Call adapter stop to disable tx/rx and clear interrupts */
622 hw->mac.ops.stop_adapter(hw);
623
624 /*
625 * Power up the Atlas Tx lanes if they are currently powered down.
626 * Atlas Tx lanes are powered down for MAC loopback tests, but
627 * they are not automatically restored on reset.
628 */
629 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
630 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
631 /* Enable Tx Atlas so packets can be transmitted again */
632 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
633 &analog_val);
634 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
635 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
636 analog_val);
637
638 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
639 &analog_val);
640 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
641 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
642 analog_val);
643
644 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
645 &analog_val);
646 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
647 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
648 analog_val);
649
650 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
651 &analog_val);
652 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
653 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
654 analog_val);
655 }
656
657 /* Reset PHY */
658 if (hw->phy.reset_disable == false)
659 hw->phy.ops.reset(hw);
660
661 /*
662 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
663 * access and verify no pending requests before reset
664 */
665 if (ixgbe_disable_pcie_master(hw) != 0) {
666 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
667 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
668 }
669
670 /*
671 * Issue global reset to the MAC. This needs to be a SW reset.
672 * If link reset is used, it might reset the MAC when mng is using it
673 */
674 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
675 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
676 IXGBE_WRITE_FLUSH(hw);
677
678 /* Poll for reset bit to self-clear indicating reset is complete */
679 for (i = 0; i < 10; i++) {
680 udelay(1);
681 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
682 if (!(ctrl & IXGBE_CTRL_RST))
683 break;
684 }
685 if (ctrl & IXGBE_CTRL_RST) {
686 status = IXGBE_ERR_RESET_FAILED;
687 hw_dbg(hw, "Reset polling failed to complete.\n");
688 }
689
690 msleep(50);
691
692 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
693 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
694 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
695
696 /*
697 * AUTOC register which stores link settings gets cleared
698 * and reloaded from EEPROM after reset. We need to restore
699 * our stored value from init in case SW changed the attach
700 * type or speed. If this is the first time and link settings
701 * have not been stored, store default settings from AUTOC.
702 */
703 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
704 if (hw->mac.link_settings_loaded) {
705 autoc &= ~(IXGBE_AUTOC_LMS_ATTACH_TYPE);
706 autoc &= ~(IXGBE_AUTOC_LMS_MASK);
707 autoc |= hw->mac.link_attach_type;
708 autoc |= hw->mac.link_mode_select;
709 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
710 } else {
711 hw->mac.link_attach_type =
712 (autoc & IXGBE_AUTOC_LMS_ATTACH_TYPE);
713 hw->mac.link_mode_select = (autoc & IXGBE_AUTOC_LMS_MASK);
714 hw->mac.link_settings_loaded = true;
715 }
716
717 /* Store the permanent mac address */
718 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
719
720 return status;
721 }
722
723 /**
724 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
725 * @hw: pointer to hardware struct
726 * @rar: receive address register index to associate with a VMDq index
727 * @vmdq: VMDq set index
728 **/
729 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
730 {
731 u32 rar_high;
732
733 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
734 rar_high &= ~IXGBE_RAH_VIND_MASK;
735 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
736 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
737 return 0;
738 }
739
740 /**
741 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
742 * @hw: pointer to hardware struct
743 * @rar: receive address register index to associate with a VMDq index
744 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
745 **/
746 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
747 {
748 u32 rar_high;
749 u32 rar_entries = hw->mac.num_rar_entries;
750
751 if (rar < rar_entries) {
752 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
753 if (rar_high & IXGBE_RAH_VIND_MASK) {
754 rar_high &= ~IXGBE_RAH_VIND_MASK;
755 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
756 }
757 } else {
758 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
759 }
760
761 return 0;
762 }
763
764 /**
765 * ixgbe_set_vfta_82598 - Set VLAN filter table
766 * @hw: pointer to hardware structure
767 * @vlan: VLAN id to write to VLAN filter
768 * @vind: VMDq output index that maps queue to VLAN id in VFTA
769 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
770 *
771 * Turn on/off specified VLAN in the VLAN filter table.
772 **/
773 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
774 bool vlan_on)
775 {
776 u32 regindex;
777 u32 bitindex;
778 u32 bits;
779 u32 vftabyte;
780
781 if (vlan > 4095)
782 return IXGBE_ERR_PARAM;
783
784 /* Determine 32-bit word position in array */
785 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
786
787 /* Determine the location of the (VMD) queue index */
788 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
789 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
790
791 /* Set the nibble for VMD queue index */
792 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
793 bits &= (~(0x0F << bitindex));
794 bits |= (vind << bitindex);
795 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
796
797 /* Determine the location of the bit for this VLAN id */
798 bitindex = vlan & 0x1F; /* lower five bits */
799
800 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
801 if (vlan_on)
802 /* Turn on this VLAN id */
803 bits |= (1 << bitindex);
804 else
805 /* Turn off this VLAN id */
806 bits &= ~(1 << bitindex);
807 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
808
809 return 0;
810 }
811
812 /**
813 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
814 * @hw: pointer to hardware structure
815 *
816 * Clears the VLAN filer table, and the VMDq index associated with the filter
817 **/
818 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
819 {
820 u32 offset;
821 u32 vlanbyte;
822
823 for (offset = 0; offset < hw->mac.vft_size; offset++)
824 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
825
826 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
827 for (offset = 0; offset < hw->mac.vft_size; offset++)
828 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
829 0);
830
831 return 0;
832 }
833
834 /**
835 * ixgbe_blink_led_start_82598 - Blink LED based on index.
836 * @hw: pointer to hardware structure
837 * @index: led number to blink
838 **/
839 static s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index)
840 {
841 ixgbe_link_speed speed = 0;
842 bool link_up = 0;
843 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
844 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
845
846 /*
847 * Link must be up to auto-blink the LEDs on the 82598EB MAC;
848 * force it if link is down.
849 */
850 hw->mac.ops.check_link(hw, &speed, &link_up, false);
851
852 if (!link_up) {
853 autoc_reg |= IXGBE_AUTOC_FLU;
854 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
855 msleep(10);
856 }
857
858 led_reg &= ~IXGBE_LED_MODE_MASK(index);
859 led_reg |= IXGBE_LED_BLINK(index);
860 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
861 IXGBE_WRITE_FLUSH(hw);
862
863 return 0;
864 }
865
866 /**
867 * ixgbe_blink_led_stop_82598 - Stop blinking LED based on index.
868 * @hw: pointer to hardware structure
869 * @index: led number to stop blinking
870 **/
871 static s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index)
872 {
873 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
874 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
875
876 autoc_reg &= ~IXGBE_AUTOC_FLU;
877 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
878 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
879
880 led_reg &= ~IXGBE_LED_MODE_MASK(index);
881 led_reg &= ~IXGBE_LED_BLINK(index);
882 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
883 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
884 IXGBE_WRITE_FLUSH(hw);
885
886 return 0;
887 }
888
889 /**
890 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
891 * @hw: pointer to hardware structure
892 * @reg: analog register to read
893 * @val: read value
894 *
895 * Performs read operation to Atlas analog register specified.
896 **/
897 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
898 {
899 u32 atlas_ctl;
900
901 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
902 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
903 IXGBE_WRITE_FLUSH(hw);
904 udelay(10);
905 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
906 *val = (u8)atlas_ctl;
907
908 return 0;
909 }
910
911 /**
912 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
913 * @hw: pointer to hardware structure
914 * @reg: atlas register to write
915 * @val: value to write
916 *
917 * Performs write operation to Atlas analog register specified.
918 **/
919 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
920 {
921 u32 atlas_ctl;
922
923 atlas_ctl = (reg << 8) | val;
924 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
925 IXGBE_WRITE_FLUSH(hw);
926 udelay(10);
927
928 return 0;
929 }
930
931 /**
932 * ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module
933 * over I2C interface through an intermediate phy.
934 * @hw: pointer to hardware structure
935 * @byte_offset: EEPROM byte offset to read
936 * @eeprom_data: value read
937 *
938 * Performs byte read operation to SFP module's EEPROM over I2C interface.
939 **/
940 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
941 u8 *eeprom_data)
942 {
943 s32 status = 0;
944 u16 sfp_addr = 0;
945 u16 sfp_data = 0;
946 u16 sfp_stat = 0;
947 u32 i;
948
949 if (hw->phy.type == ixgbe_phy_nl) {
950 /*
951 * phy SDA/SCL registers are at addresses 0xC30A to
952 * 0xC30D. These registers are used to talk to the SFP+
953 * module's EEPROM through the SDA/SCL (I2C) interface.
954 */
955 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
956 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
957 hw->phy.ops.write_reg(hw,
958 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
959 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
960 sfp_addr);
961
962 /* Poll status */
963 for (i = 0; i < 100; i++) {
964 hw->phy.ops.read_reg(hw,
965 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
966 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
967 &sfp_stat);
968 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
969 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
970 break;
971 msleep(10);
972 }
973
974 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
975 hw_dbg(hw, "EEPROM read did not pass.\n");
976 status = IXGBE_ERR_SFP_NOT_PRESENT;
977 goto out;
978 }
979
980 /* Read data */
981 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
982 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
983
984 *eeprom_data = (u8)(sfp_data >> 8);
985 } else {
986 status = IXGBE_ERR_PHY;
987 goto out;
988 }
989
990 out:
991 return status;
992 }
993
994 /**
995 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
996 * @hw: pointer to hardware structure
997 *
998 * Determines physical layer capabilities of the current configuration.
999 **/
1000 static s32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1001 {
1002 s32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1003
1004 switch (hw->device_id) {
1005 case IXGBE_DEV_ID_82598EB_CX4:
1006 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
1007 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1008 break;
1009 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1010 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1011 break;
1012 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1013 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1014 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1015 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1016 break;
1017 case IXGBE_DEV_ID_82598EB_XF_LR:
1018 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1019 break;
1020 case IXGBE_DEV_ID_82598AT:
1021 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_T |
1022 IXGBE_PHYSICAL_LAYER_1000BASE_T);
1023 break;
1024 case IXGBE_DEV_ID_82598EB_SFP_LOM:
1025 hw->phy.ops.identify_sfp(hw);
1026
1027 switch (hw->phy.sfp_type) {
1028 case ixgbe_sfp_type_da_cu:
1029 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1030 break;
1031 case ixgbe_sfp_type_sr:
1032 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1033 break;
1034 case ixgbe_sfp_type_lr:
1035 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1036 break;
1037 default:
1038 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1039 break;
1040 }
1041 break;
1042
1043 default:
1044 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1045 break;
1046 }
1047
1048 return physical_layer;
1049 }
1050
1051 static struct ixgbe_mac_operations mac_ops_82598 = {
1052 .init_hw = &ixgbe_init_hw_generic,
1053 .reset_hw = &ixgbe_reset_hw_82598,
1054 .start_hw = &ixgbe_start_hw_generic,
1055 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
1056 .get_media_type = &ixgbe_get_media_type_82598,
1057 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
1058 .get_mac_addr = &ixgbe_get_mac_addr_generic,
1059 .stop_adapter = &ixgbe_stop_adapter_generic,
1060 .read_analog_reg8 = &ixgbe_read_analog_reg8_82598,
1061 .write_analog_reg8 = &ixgbe_write_analog_reg8_82598,
1062 .setup_link = &ixgbe_setup_mac_link_82598,
1063 .setup_link_speed = &ixgbe_setup_mac_link_speed_82598,
1064 .check_link = &ixgbe_check_mac_link_82598,
1065 .get_link_capabilities = &ixgbe_get_link_capabilities_82598,
1066 .led_on = &ixgbe_led_on_generic,
1067 .led_off = &ixgbe_led_off_generic,
1068 .blink_led_start = &ixgbe_blink_led_start_82598,
1069 .blink_led_stop = &ixgbe_blink_led_stop_82598,
1070 .set_rar = &ixgbe_set_rar_generic,
1071 .clear_rar = &ixgbe_clear_rar_generic,
1072 .set_vmdq = &ixgbe_set_vmdq_82598,
1073 .clear_vmdq = &ixgbe_clear_vmdq_82598,
1074 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
1075 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
1076 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1077 .enable_mc = &ixgbe_enable_mc_generic,
1078 .disable_mc = &ixgbe_disable_mc_generic,
1079 .clear_vfta = &ixgbe_clear_vfta_82598,
1080 .set_vfta = &ixgbe_set_vfta_82598,
1081 .setup_fc = &ixgbe_setup_fc_82598,
1082 };
1083
1084 static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1085 .init_params = &ixgbe_init_eeprom_params_generic,
1086 .read = &ixgbe_read_eeprom_generic,
1087 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1088 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1089 };
1090
1091 static struct ixgbe_phy_operations phy_ops_82598 = {
1092 .identify = &ixgbe_identify_phy_generic,
1093 .identify_sfp = &ixgbe_identify_sfp_module_generic,
1094 .reset = &ixgbe_reset_phy_generic,
1095 .read_reg = &ixgbe_read_phy_reg_generic,
1096 .write_reg = &ixgbe_write_phy_reg_generic,
1097 .setup_link = &ixgbe_setup_phy_link_generic,
1098 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
1099 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598,
1100 };
1101
1102 struct ixgbe_info ixgbe_82598_info = {
1103 .mac = ixgbe_mac_82598EB,
1104 .get_invariants = &ixgbe_get_invariants_82598,
1105 .mac_ops = &mac_ops_82598,
1106 .eeprom_ops = &eeprom_ops_82598,
1107 .phy_ops = &phy_ops_82598,
1108 };
1109
(Inofficial) Linux kernel tree running on the Nao robot