?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
repo init
[linux-rt-nao.git] / sound / soc / codecs / tlv320aic3x.c
blobaea0cb72d80a9ad96f81f43e0454231c613cffbf
1 /*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33.
16 *
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 is as follows:
19 * aic32 | aic31
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
33 */
34
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/pm.h>
40 #include <linux/i2c.h>
41 #include <linux/platform_device.h>
42 #include <sound/core.h>
43 #include <sound/pcm.h>
44 #include <sound/pcm_params.h>
45 #include <sound/soc.h>
46 #include <sound/soc-dapm.h>
47 #include <sound/initval.h>
48
49 #include "tlv320aic3x.h"
50
51 #define AIC3X_VERSION "0.2"
52
53 /* codec private data */
54 struct aic3x_priv {
55 unsigned int sysclk;
56 int master;
57 };
58
59 /*
60 * AIC3X register cache
61 * We can't read the AIC3X register space when we are
62 * using 2 wire for device control, so we cache them instead.
63 * There is no point in caching the reset register
64 */
65 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
66 0x00, 0x00, 0x00, 0x10, /* 0 */
67 0x04, 0x00, 0x00, 0x00, /* 4 */
68 0x00, 0x00, 0x00, 0x01, /* 8 */
69 0x00, 0x00, 0x00, 0x80, /* 12 */
70 0x80, 0xff, 0xff, 0x78, /* 16 */
71 0x78, 0x78, 0x78, 0x78, /* 20 */
72 0x78, 0x00, 0x00, 0xfe, /* 24 */
73 0x00, 0x00, 0xfe, 0x00, /* 28 */
74 0x18, 0x18, 0x00, 0x00, /* 32 */
75 0x00, 0x00, 0x00, 0x00, /* 36 */
76 0x00, 0x00, 0x00, 0x80, /* 40 */
77 0x80, 0x00, 0x00, 0x00, /* 44 */
78 0x00, 0x00, 0x00, 0x04, /* 48 */
79 0x00, 0x00, 0x00, 0x00, /* 52 */
80 0x00, 0x00, 0x04, 0x00, /* 56 */
81 0x00, 0x00, 0x00, 0x00, /* 60 */
82 0x00, 0x04, 0x00, 0x00, /* 64 */
83 0x00, 0x00, 0x00, 0x00, /* 68 */
84 0x04, 0x00, 0x00, 0x00, /* 72 */
85 0x00, 0x00, 0x00, 0x00, /* 76 */
86 0x00, 0x00, 0x00, 0x00, /* 80 */
87 0x00, 0x00, 0x00, 0x00, /* 84 */
88 0x00, 0x00, 0x00, 0x00, /* 88 */
89 0x00, 0x00, 0x00, 0x00, /* 92 */
90 0x00, 0x00, 0x00, 0x00, /* 96 */
91 0x00, 0x00, 0x02, /* 100 */
92 };
93
94 /*
95 * read aic3x register cache
96 */
97 static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec,
98 unsigned int reg)
99 {
100 u8 *cache = codec->reg_cache;
101 if (reg >= AIC3X_CACHEREGNUM)
102 return -1;
103 return cache[reg];
104 }
105
106 /*
107 * write aic3x register cache
108 */
109 static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec,
110 u8 reg, u8 value)
111 {
112 u8 *cache = codec->reg_cache;
113 if (reg >= AIC3X_CACHEREGNUM)
114 return;
115 cache[reg] = value;
116 }
117
118 /*
119 * write to the aic3x register space
120 */
121 static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg,
122 unsigned int value)
123 {
124 u8 data[2];
125
126 /* data is
127 * D15..D8 aic3x register offset
128 * D7...D0 register data
129 */
130 data[0] = reg & 0xff;
131 data[1] = value & 0xff;
132
133 aic3x_write_reg_cache(codec, data[0], data[1]);
134 if (codec->hw_write(codec->control_data, data, 2) == 2)
135 return 0;
136 else
137 return -EIO;
138 }
139
140 /*
141 * read from the aic3x register space
142 */
143 static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
144 u8 *value)
145 {
146 *value = reg & 0xff;
147 if (codec->hw_read(codec->control_data, value, 1) != 1)
148 return -EIO;
149
150 aic3x_write_reg_cache(codec, reg, *value);
151 return 0;
152 }
153
154 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
155 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
156 .info = snd_soc_info_volsw, \
157 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
158 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
159
160 /*
161 * All input lines are connected when !0xf and disconnected with 0xf bit field,
162 * so we have to use specific dapm_put call for input mixer
163 */
164 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
165 struct snd_ctl_elem_value *ucontrol)
166 {
167 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
168 struct soc_mixer_control *mc =
169 (struct soc_mixer_control *)kcontrol->private_value;
170 unsigned int reg = mc->reg;
171 unsigned int shift = mc->shift;
172 int max = mc->max;
173 unsigned int mask = (1 << fls(max)) - 1;
174 unsigned int invert = mc->invert;
175 unsigned short val, val_mask;
176 int ret;
177 struct snd_soc_dapm_path *path;
178 int found = 0;
179
180 val = (ucontrol->value.integer.value[0] & mask);
181
182 mask = 0xf;
183 if (val)
184 val = mask;
185
186 if (invert)
187 val = mask - val;
188 val_mask = mask << shift;
189 val = val << shift;
190
191 mutex_lock(&widget->codec->mutex);
192
193 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
194 /* find dapm widget path assoc with kcontrol */
195 list_for_each_entry(path, &widget->codec->dapm_paths, list) {
196 if (path->kcontrol != kcontrol)
197 continue;
198
199 /* found, now check type */
200 found = 1;
201 if (val)
202 /* new connection */
203 path->connect = invert ? 0 : 1;
204 else
205 /* old connection must be powered down */
206 path->connect = invert ? 1 : 0;
207 break;
208 }
209
210 if (found)
211 snd_soc_dapm_sync(widget->codec);
212 }
213
214 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
215
216 mutex_unlock(&widget->codec->mutex);
217 return ret;
218 }
219
220 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
221 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
222 static const char *aic3x_left_hpcom_mux[] =
223 { "differential of HPLOUT", "constant VCM", "single-ended" };
224 static const char *aic3x_right_hpcom_mux[] =
225 { "differential of HPROUT", "constant VCM", "single-ended",
226 "differential of HPLCOM", "external feedback" };
227 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
228 static const char *aic3x_adc_hpf[] =
229 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
230
231 #define LDAC_ENUM 0
232 #define RDAC_ENUM 1
233 #define LHPCOM_ENUM 2
234 #define RHPCOM_ENUM 3
235 #define LINE1L_ENUM 4
236 #define LINE1R_ENUM 5
237 #define LINE2L_ENUM 6
238 #define LINE2R_ENUM 7
239 #define ADC_HPF_ENUM 8
240
241 static const struct soc_enum aic3x_enum[] = {
242 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
243 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
244 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
245 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
246 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
247 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
248 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
249 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
250 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
251 };
252
253 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
254 /* Output */
255 SOC_DOUBLE_R("PCM Playback Volume", LDAC_VOL, RDAC_VOL, 0, 0x7f, 1),
256
257 SOC_DOUBLE_R("Line DAC Playback Volume", DACL1_2_LLOPM_VOL,
258 DACR1_2_RLOPM_VOL, 0, 0x7f, 1),
259 SOC_SINGLE("LineL Playback Switch", LLOPM_CTRL, 3, 0x01, 0),
260 SOC_SINGLE("LineR Playback Switch", RLOPM_CTRL, 3, 0x01, 0),
261 SOC_DOUBLE_R("LineL DAC Playback Volume", DACL1_2_LLOPM_VOL,
262 DACR1_2_LLOPM_VOL, 0, 0x7f, 1),
263 SOC_SINGLE("LineL Left PGA Bypass Playback Volume", PGAL_2_LLOPM_VOL,
264 0, 0x7f, 1),
265 SOC_SINGLE("LineR Right PGA Bypass Playback Volume", PGAR_2_RLOPM_VOL,
266 0, 0x7f, 1),
267 SOC_DOUBLE_R("LineL Line2 Bypass Playback Volume", LINE2L_2_LLOPM_VOL,
268 LINE2R_2_LLOPM_VOL, 0, 0x7f, 1),
269 SOC_DOUBLE_R("LineR Line2 Bypass Playback Volume", LINE2L_2_RLOPM_VOL,
270 LINE2R_2_RLOPM_VOL, 0, 0x7f, 1),
271
272 SOC_DOUBLE_R("Mono DAC Playback Volume", DACL1_2_MONOLOPM_VOL,
273 DACR1_2_MONOLOPM_VOL, 0, 0x7f, 1),
274 SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
275 SOC_DOUBLE_R("Mono PGA Bypass Playback Volume", PGAL_2_MONOLOPM_VOL,
276 PGAR_2_MONOLOPM_VOL, 0, 0x7f, 1),
277 SOC_DOUBLE_R("Mono Line2 Bypass Playback Volume", LINE2L_2_MONOLOPM_VOL,
278 LINE2R_2_MONOLOPM_VOL, 0, 0x7f, 1),
279
280 SOC_DOUBLE_R("HP DAC Playback Volume", DACL1_2_HPLOUT_VOL,
281 DACR1_2_HPROUT_VOL, 0, 0x7f, 1),
282 SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
283 0x01, 0),
284 SOC_DOUBLE_R("HP Right PGA Bypass Playback Volume", PGAR_2_HPLOUT_VOL,
285 PGAR_2_HPROUT_VOL, 0, 0x7f, 1),
286 SOC_SINGLE("HPL PGA Bypass Playback Volume", PGAL_2_HPLOUT_VOL,
287 0, 0x7f, 1),
288 SOC_SINGLE("HPR PGA Bypass Playback Volume", PGAL_2_HPROUT_VOL,
289 0, 0x7f, 1),
290 SOC_DOUBLE_R("HP Line2 Bypass Playback Volume", LINE2L_2_HPLOUT_VOL,
291 LINE2R_2_HPROUT_VOL, 0, 0x7f, 1),
292
293 SOC_DOUBLE_R("HPCOM DAC Playback Volume", DACL1_2_HPLCOM_VOL,
294 DACR1_2_HPRCOM_VOL, 0, 0x7f, 1),
295 SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
296 0x01, 0),
297 SOC_SINGLE("HPLCOM PGA Bypass Playback Volume", PGAL_2_HPLCOM_VOL,
298 0, 0x7f, 1),
299 SOC_SINGLE("HPRCOM PGA Bypass Playback Volume", PGAL_2_HPRCOM_VOL,
300 0, 0x7f, 1),
301 SOC_DOUBLE_R("HPCOM Line2 Bypass Playback Volume", LINE2L_2_HPLCOM_VOL,
302 LINE2R_2_HPRCOM_VOL, 0, 0x7f, 1),
303
304 /*
305 * Note: enable Automatic input Gain Controller with care. It can
306 * adjust PGA to max value when ADC is on and will never go back.
307 */
308 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
309
310 /* Input */
311 SOC_DOUBLE_R("PGA Capture Volume", LADC_VOL, RADC_VOL, 0, 0x7f, 0),
312 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
313
314 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
315 };
316
317 /* add non dapm controls */
318 static int aic3x_add_controls(struct snd_soc_codec *codec)
319 {
320 int err, i;
321
322 for (i = 0; i < ARRAY_SIZE(aic3x_snd_controls); i++) {
323 err = snd_ctl_add(codec->card,
324 snd_soc_cnew(&aic3x_snd_controls[i],
325 codec, NULL));
326 if (err < 0)
327 return err;
328 }
329
330 return 0;
331 }
332
333 /* Left DAC Mux */
334 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
335 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
336
337 /* Right DAC Mux */
338 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
339 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
340
341 /* Left HPCOM Mux */
342 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
343 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
344
345 /* Right HPCOM Mux */
346 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
347 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
348
349 /* Left DAC_L1 Mixer */
350 static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = {
351 SOC_DAPM_SINGLE("LineL Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
352 SOC_DAPM_SINGLE("LineR Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
353 SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
354 SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
355 SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
356 };
357
358 /* Right DAC_R1 Mixer */
359 static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = {
360 SOC_DAPM_SINGLE("LineL Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
361 SOC_DAPM_SINGLE("LineR Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
362 SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
363 SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
364 SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
365 };
366
367 /* Left PGA Mixer */
368 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
369 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
370 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
371 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
372 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
373 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
374 };
375
376 /* Right PGA Mixer */
377 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
378 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
379 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
380 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
381 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
382 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
383 };
384
385 /* Left Line1 Mux */
386 static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
387 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
388
389 /* Right Line1 Mux */
390 static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
391 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
392
393 /* Left Line2 Mux */
394 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
395 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
396
397 /* Right Line2 Mux */
398 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
399 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
400
401 /* Left PGA Bypass Mixer */
402 static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = {
403 SOC_DAPM_SINGLE("LineL Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
404 SOC_DAPM_SINGLE("LineR Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
405 SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
406 SOC_DAPM_SINGLE("HPL Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
407 SOC_DAPM_SINGLE("HPR Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
408 SOC_DAPM_SINGLE("HPLCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
409 SOC_DAPM_SINGLE("HPRCOM Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
410 };
411
412 /* Right PGA Bypass Mixer */
413 static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = {
414 SOC_DAPM_SINGLE("LineL Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
415 SOC_DAPM_SINGLE("LineR Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
416 SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
417 SOC_DAPM_SINGLE("HPL Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
418 SOC_DAPM_SINGLE("HPR Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
419 SOC_DAPM_SINGLE("HPLCOM Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
420 SOC_DAPM_SINGLE("HPRCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
421 };
422
423 /* Left Line2 Bypass Mixer */
424 static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = {
425 SOC_DAPM_SINGLE("LineL Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
426 SOC_DAPM_SINGLE("LineR Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
427 SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
428 SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
429 SOC_DAPM_SINGLE("HPLCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
430 };
431
432 /* Right Line2 Bypass Mixer */
433 static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = {
434 SOC_DAPM_SINGLE("LineL Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
435 SOC_DAPM_SINGLE("LineR Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
436 SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
437 SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
438 SOC_DAPM_SINGLE("HPRCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
439 };
440
441 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
442 /* Left DAC to Left Outputs */
443 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
444 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
445 &aic3x_left_dac_mux_controls),
446 SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0,
447 &aic3x_left_dac_mixer_controls[0],
448 ARRAY_SIZE(aic3x_left_dac_mixer_controls)),
449 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
450 &aic3x_left_hpcom_mux_controls),
451 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
452 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
453 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
454
455 /* Right DAC to Right Outputs */
456 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
457 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
458 &aic3x_right_dac_mux_controls),
459 SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0,
460 &aic3x_right_dac_mixer_controls[0],
461 ARRAY_SIZE(aic3x_right_dac_mixer_controls)),
462 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
463 &aic3x_right_hpcom_mux_controls),
464 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
465 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
466 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
467
468 /* Mono Output */
469 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
470
471 /* Inputs to Left ADC */
472 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
473 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
474 &aic3x_left_pga_mixer_controls[0],
475 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
476 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
477 &aic3x_left_line1_mux_controls),
478 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
479 &aic3x_left_line1_mux_controls),
480 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
481 &aic3x_left_line2_mux_controls),
482
483 /* Inputs to Right ADC */
484 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
485 LINE1R_2_RADC_CTRL, 2, 0),
486 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
487 &aic3x_right_pga_mixer_controls[0],
488 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
489 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
490 &aic3x_right_line1_mux_controls),
491 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
492 &aic3x_right_line1_mux_controls),
493 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
494 &aic3x_right_line2_mux_controls),
495
496 /*
497 * Not a real mic bias widget but similar function. This is for dynamic
498 * control of GPIO1 digital mic modulator clock output function when
499 * using digital mic.
500 */
501 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
502 AIC3X_GPIO1_REG, 4, 0xf,
503 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
504 AIC3X_GPIO1_FUNC_DISABLED),
505
506 /*
507 * Also similar function like mic bias. Selects digital mic with
508 * configurable oversampling rate instead of ADC converter.
509 */
510 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
511 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
512 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
513 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
514 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
515 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
516
517 /* Mic Bias */
518 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
519 MICBIAS_CTRL, 6, 3, 1, 0),
520 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
521 MICBIAS_CTRL, 6, 3, 2, 0),
522 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
523 MICBIAS_CTRL, 6, 3, 3, 0),
524
525 /* Left PGA to Left Output bypass */
526 SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
527 &aic3x_left_pga_bp_mixer_controls[0],
528 ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls)),
529
530 /* Right PGA to Right Output bypass */
531 SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
532 &aic3x_right_pga_bp_mixer_controls[0],
533 ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls)),
534
535 /* Left Line2 to Left Output bypass */
536 SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
537 &aic3x_left_line2_bp_mixer_controls[0],
538 ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)),
539
540 /* Right Line2 to Right Output bypass */
541 SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
542 &aic3x_right_line2_bp_mixer_controls[0],
543 ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)),
544
545 SND_SOC_DAPM_OUTPUT("LLOUT"),
546 SND_SOC_DAPM_OUTPUT("RLOUT"),
547 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
548 SND_SOC_DAPM_OUTPUT("HPLOUT"),
549 SND_SOC_DAPM_OUTPUT("HPROUT"),
550 SND_SOC_DAPM_OUTPUT("HPLCOM"),
551 SND_SOC_DAPM_OUTPUT("HPRCOM"),
552
553 SND_SOC_DAPM_INPUT("MIC3L"),
554 SND_SOC_DAPM_INPUT("MIC3R"),
555 SND_SOC_DAPM_INPUT("LINE1L"),
556 SND_SOC_DAPM_INPUT("LINE1R"),
557 SND_SOC_DAPM_INPUT("LINE2L"),
558 SND_SOC_DAPM_INPUT("LINE2R"),
559 };
560
561 static const struct snd_soc_dapm_route intercon[] = {
562 /* Left Output */
563 {"Left DAC Mux", "DAC_L1", "Left DAC"},
564 {"Left DAC Mux", "DAC_L2", "Left DAC"},
565 {"Left DAC Mux", "DAC_L3", "Left DAC"},
566
567 {"Left DAC_L1 Mixer", "LineL Switch", "Left DAC Mux"},
568 {"Left DAC_L1 Mixer", "LineR Switch", "Left DAC Mux"},
569 {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
570 {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
571 {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
572 {"Left Line Out", NULL, "Left DAC Mux"},
573 {"Left HP Out", NULL, "Left DAC Mux"},
574
575 {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
576 {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
577 {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
578
579 {"Left Line Out", NULL, "Left DAC_L1 Mixer"},
580 {"Mono Out", NULL, "Left DAC_L1 Mixer"},
581 {"Left HP Out", NULL, "Left DAC_L1 Mixer"},
582 {"Left HP Com", NULL, "Left HPCOM Mux"},
583
584 {"LLOUT", NULL, "Left Line Out"},
585 {"LLOUT", NULL, "Left Line Out"},
586 {"HPLOUT", NULL, "Left HP Out"},
587 {"HPLCOM", NULL, "Left HP Com"},
588
589 /* Right Output */
590 {"Right DAC Mux", "DAC_R1", "Right DAC"},
591 {"Right DAC Mux", "DAC_R2", "Right DAC"},
592 {"Right DAC Mux", "DAC_R3", "Right DAC"},
593
594 {"Right DAC_R1 Mixer", "LineL Switch", "Right DAC Mux"},
595 {"Right DAC_R1 Mixer", "LineR Switch", "Right DAC Mux"},
596 {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
597 {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
598 {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
599 {"Right Line Out", NULL, "Right DAC Mux"},
600 {"Right HP Out", NULL, "Right DAC Mux"},
601
602 {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
603 {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
604 {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
605 {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
606 {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
607
608 {"Right Line Out", NULL, "Right DAC_R1 Mixer"},
609 {"Mono Out", NULL, "Right DAC_R1 Mixer"},
610 {"Right HP Out", NULL, "Right DAC_R1 Mixer"},
611 {"Right HP Com", NULL, "Right HPCOM Mux"},
612
613 {"RLOUT", NULL, "Right Line Out"},
614 {"RLOUT", NULL, "Right Line Out"},
615 {"HPROUT", NULL, "Right HP Out"},
616 {"HPRCOM", NULL, "Right HP Com"},
617
618 /* Mono Output */
619 {"MONO_LOUT", NULL, "Mono Out"},
620 {"MONO_LOUT", NULL, "Mono Out"},
621
622 /* Left Input */
623 {"Left Line1L Mux", "single-ended", "LINE1L"},
624 {"Left Line1L Mux", "differential", "LINE1L"},
625
626 {"Left Line2L Mux", "single-ended", "LINE2L"},
627 {"Left Line2L Mux", "differential", "LINE2L"},
628
629 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
630 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
631 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
632 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
633 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
634
635 {"Left ADC", NULL, "Left PGA Mixer"},
636 {"Left ADC", NULL, "GPIO1 dmic modclk"},
637
638 /* Right Input */
639 {"Right Line1R Mux", "single-ended", "LINE1R"},
640 {"Right Line1R Mux", "differential", "LINE1R"},
641
642 {"Right Line2R Mux", "single-ended", "LINE2R"},
643 {"Right Line2R Mux", "differential", "LINE2R"},
644
645 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
646 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
647 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
648 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
649 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
650
651 {"Right ADC", NULL, "Right PGA Mixer"},
652 {"Right ADC", NULL, "GPIO1 dmic modclk"},
653
654 /* Left PGA Bypass */
655 {"Left PGA Bypass Mixer", "LineL Switch", "Left PGA Mixer"},
656 {"Left PGA Bypass Mixer", "LineR Switch", "Left PGA Mixer"},
657 {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
658 {"Left PGA Bypass Mixer", "HPL Switch", "Left PGA Mixer"},
659 {"Left PGA Bypass Mixer", "HPR Switch", "Left PGA Mixer"},
660 {"Left PGA Bypass Mixer", "HPLCOM Switch", "Left PGA Mixer"},
661 {"Left PGA Bypass Mixer", "HPRCOM Switch", "Left PGA Mixer"},
662
663 {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
664 {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
665 {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
666
667 {"Left Line Out", NULL, "Left PGA Bypass Mixer"},
668 {"Mono Out", NULL, "Left PGA Bypass Mixer"},
669 {"Left HP Out", NULL, "Left PGA Bypass Mixer"},
670
671 /* Right PGA Bypass */
672 {"Right PGA Bypass Mixer", "LineL Switch", "Right PGA Mixer"},
673 {"Right PGA Bypass Mixer", "LineR Switch", "Right PGA Mixer"},
674 {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
675 {"Right PGA Bypass Mixer", "HPL Switch", "Right PGA Mixer"},
676 {"Right PGA Bypass Mixer", "HPR Switch", "Right PGA Mixer"},
677 {"Right PGA Bypass Mixer", "HPLCOM Switch", "Right PGA Mixer"},
678 {"Right PGA Bypass Mixer", "HPRCOM Switch", "Right PGA Mixer"},
679
680 {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
681 {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
682 {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
683 {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
684 {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
685
686 {"Right Line Out", NULL, "Right PGA Bypass Mixer"},
687 {"Mono Out", NULL, "Right PGA Bypass Mixer"},
688 {"Right HP Out", NULL, "Right PGA Bypass Mixer"},
689
690 /* Left Line2 Bypass */
691 {"Left Line2 Bypass Mixer", "LineL Switch", "Left Line2L Mux"},
692 {"Left Line2 Bypass Mixer", "LineR Switch", "Left Line2L Mux"},
693 {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
694 {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
695 {"Left Line2 Bypass Mixer", "HPLCOM Switch", "Left Line2L Mux"},
696
697 {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
698 {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
699 {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
700
701 {"Left Line Out", NULL, "Left Line2 Bypass Mixer"},
702 {"Mono Out", NULL, "Left Line2 Bypass Mixer"},
703 {"Left HP Out", NULL, "Left Line2 Bypass Mixer"},
704
705 /* Right Line2 Bypass */
706 {"Right Line2 Bypass Mixer", "LineL Switch", "Right Line2R Mux"},
707 {"Right Line2 Bypass Mixer", "LineR Switch", "Right Line2R Mux"},
708 {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
709 {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
710 {"Right Line2 Bypass Mixer", "HPRCOM Switch", "Right Line2R Mux"},
711
712 {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
713 {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
714 {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
715 {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
716 {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
717
718 {"Right Line Out", NULL, "Right Line2 Bypass Mixer"},
719 {"Mono Out", NULL, "Right Line2 Bypass Mixer"},
720 {"Right HP Out", NULL, "Right Line2 Bypass Mixer"},
721
722 /*
723 * Logical path between digital mic enable and GPIO1 modulator clock
724 * output function
725 */
726 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
727 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
728 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
729 };
730
731 static int aic3x_add_widgets(struct snd_soc_codec *codec)
732 {
733 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets,
734 ARRAY_SIZE(aic3x_dapm_widgets));
735
736 /* set up audio path interconnects */
737 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
738
739 snd_soc_dapm_new_widgets(codec);
740 return 0;
741 }
742
743 static int aic3x_hw_params(struct snd_pcm_substream *substream,
744 struct snd_pcm_hw_params *params,
745 struct snd_soc_dai *dai)
746 {
747 struct snd_soc_pcm_runtime *rtd = substream->private_data;
748 struct snd_soc_device *socdev = rtd->socdev;
749 struct snd_soc_codec *codec = socdev->codec;
750 struct aic3x_priv *aic3x = codec->private_data;
751 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
752 u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
753 u16 pll_d = 1;
754
755 /* select data word length */
756 data =
757 aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
758 switch (params_format(params)) {
759 case SNDRV_PCM_FORMAT_S16_LE:
760 break;
761 case SNDRV_PCM_FORMAT_S20_3LE:
762 data |= (0x01 << 4);
763 break;
764 case SNDRV_PCM_FORMAT_S24_LE:
765 data |= (0x02 << 4);
766 break;
767 case SNDRV_PCM_FORMAT_S32_LE:
768 data |= (0x03 << 4);
769 break;
770 }
771 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data);
772
773 /* Fsref can be 44100 or 48000 */
774 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
775
776 /* Try to find a value for Q which allows us to bypass the PLL and
777 * generate CODEC_CLK directly. */
778 for (pll_q = 2; pll_q < 18; pll_q++)
779 if (aic3x->sysclk / (128 * pll_q) == fsref) {
780 bypass_pll = 1;
781 break;
782 }
783
784 if (bypass_pll) {
785 pll_q &= 0xf;
786 aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
787 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
788 } else
789 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
790
791 /* Route Left DAC to left channel input and
792 * right DAC to right channel input */
793 data = (LDAC2LCH | RDAC2RCH);
794 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
795 if (params_rate(params) >= 64000)
796 data |= DUAL_RATE_MODE;
797 aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
798
799 /* codec sample rate select */
800 data = (fsref * 20) / params_rate(params);
801 if (params_rate(params) < 64000)
802 data /= 2;
803 data /= 5;
804 data -= 2;
805 data |= (data << 4);
806 aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
807
808 if (bypass_pll)
809 return 0;
810
811 /* Use PLL
812 * find an apropriate setup for j, d, r and p by iterating over
813 * p and r - j and d are calculated for each fraction.
814 * Up to 128 values are probed, the closest one wins the game.
815 * The sysclk is divided by 1000 to prevent integer overflows.
816 */
817 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
818
819 for (r = 1; r <= 16; r++)
820 for (p = 1; p <= 8; p++) {
821 int clk, tmp = (codec_clk * pll_r * 10) / pll_p;
822 u8 j = tmp / 10000;
823 u16 d = tmp % 10000;
824
825 if (j > 63)
826 continue;
827
828 if (d != 0 && aic3x->sysclk < 10000000)
829 continue;
830
831 /* This is actually 1000 * ((j + (d/10000)) * r) / p
832 * The term had to be converted to get rid of the
833 * division by 10000 */
834 clk = ((10000 * j * r) + (d * r)) / (10 * p);
835
836 /* check whether this values get closer than the best
837 * ones we had before */
838 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
839 pll_j = j; pll_d = d; pll_r = r; pll_p = p;
840 last_clk = clk;
841 }
842
843 /* Early exit for exact matches */
844 if (clk == codec_clk)
845 break;
846 }
847
848 if (last_clk == 0) {
849 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
850 return -EINVAL;
851 }
852
853 data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
854 aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
855 aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
856 aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
857 aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
858 aic3x_write(codec, AIC3X_PLL_PROGD_REG,
859 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
860
861 return 0;
862 }
863
864 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
865 {
866 struct snd_soc_codec *codec = dai->codec;
867 u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON;
868 u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON;
869
870 if (mute) {
871 aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
872 aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
873 } else {
874 aic3x_write(codec, LDAC_VOL, ldac_reg);
875 aic3x_write(codec, RDAC_VOL, rdac_reg);
876 }
877
878 return 0;
879 }
880
881 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
882 int clk_id, unsigned int freq, int dir)
883 {
884 struct snd_soc_codec *codec = codec_dai->codec;
885 struct aic3x_priv *aic3x = codec->private_data;
886
887 aic3x->sysclk = freq;
888 return 0;
889 }
890
891 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
892 unsigned int fmt)
893 {
894 struct snd_soc_codec *codec = codec_dai->codec;
895 struct aic3x_priv *aic3x = codec->private_data;
896 u8 iface_areg, iface_breg;
897 int delay = 0;
898
899 iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
900 iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
901
902 /* set master/slave audio interface */
903 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
904 case SND_SOC_DAIFMT_CBM_CFM:
905 aic3x->master = 1;
906 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
907 break;
908 case SND_SOC_DAIFMT_CBS_CFS:
909 aic3x->master = 0;
910 break;
911 default:
912 return -EINVAL;
913 }
914
915 /*
916 * match both interface format and signal polarities since they
917 * are fixed
918 */
919 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
920 SND_SOC_DAIFMT_INV_MASK)) {
921 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
922 break;
923 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
924 delay = 1;
925 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
926 iface_breg |= (0x01 << 6);
927 break;
928 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
929 iface_breg |= (0x02 << 6);
930 break;
931 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
932 iface_breg |= (0x03 << 6);
933 break;
934 default:
935 return -EINVAL;
936 }
937
938 /* set iface */
939 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
940 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
941 aic3x_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
942
943 return 0;
944 }
945
946 static int aic3x_set_bias_level(struct snd_soc_codec *codec,
947 enum snd_soc_bias_level level)
948 {
949 struct aic3x_priv *aic3x = codec->private_data;
950 u8 reg;
951
952 switch (level) {
953 case SND_SOC_BIAS_ON:
954 /* all power is driven by DAPM system */
955 if (aic3x->master) {
956 /* enable pll */
957 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
958 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
959 reg | PLL_ENABLE);
960 }
961 break;
962 case SND_SOC_BIAS_PREPARE:
963 break;
964 case SND_SOC_BIAS_STANDBY:
965 /*
966 * all power is driven by DAPM system,
967 * so output power is safe if bypass was set
968 */
969 if (aic3x->master) {
970 /* disable pll */
971 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
972 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
973 reg & ~PLL_ENABLE);
974 }
975 break;
976 case SND_SOC_BIAS_OFF:
977 /* force all power off */
978 reg = aic3x_read_reg_cache(codec, LINE1L_2_LADC_CTRL);
979 aic3x_write(codec, LINE1L_2_LADC_CTRL, reg & ~LADC_PWR_ON);
980 reg = aic3x_read_reg_cache(codec, LINE1R_2_RADC_CTRL);
981 aic3x_write(codec, LINE1R_2_RADC_CTRL, reg & ~RADC_PWR_ON);
982
983 reg = aic3x_read_reg_cache(codec, DAC_PWR);
984 aic3x_write(codec, DAC_PWR, reg & ~(LDAC_PWR_ON | RDAC_PWR_ON));
985
986 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
987 aic3x_write(codec, HPLOUT_CTRL, reg & ~HPLOUT_PWR_ON);
988 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
989 aic3x_write(codec, HPROUT_CTRL, reg & ~HPROUT_PWR_ON);
990
991 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
992 aic3x_write(codec, HPLCOM_CTRL, reg & ~HPLCOM_PWR_ON);
993 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
994 aic3x_write(codec, HPRCOM_CTRL, reg & ~HPRCOM_PWR_ON);
995
996 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
997 aic3x_write(codec, MONOLOPM_CTRL, reg & ~MONOLOPM_PWR_ON);
998
999 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1000 aic3x_write(codec, LLOPM_CTRL, reg & ~LLOPM_PWR_ON);
1001 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1002 aic3x_write(codec, RLOPM_CTRL, reg & ~RLOPM_PWR_ON);
1003
1004 if (aic3x->master) {
1005 /* disable pll */
1006 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1007 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1008 reg & ~PLL_ENABLE);
1009 }
1010 break;
1011 }
1012 codec->bias_level = level;
1013
1014 return 0;
1015 }
1016
1017 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1018 {
1019 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1020 u8 bit = gpio ? 3: 0;
1021 u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit);
1022 aic3x_write(codec, reg, val | (!!state << bit));
1023 }
1024 EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1025
1026 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1027 {
1028 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1029 u8 val, bit = gpio ? 2: 1;
1030
1031 aic3x_read(codec, reg, &val);
1032 return (val >> bit) & 1;
1033 }
1034 EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1035
1036 void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
1037 int headset_debounce, int button_debounce)
1038 {
1039 u8 val;
1040
1041 val = ((detect & AIC3X_HEADSET_DETECT_MASK)
1042 << AIC3X_HEADSET_DETECT_SHIFT) |
1043 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK)
1044 << AIC3X_HEADSET_DEBOUNCE_SHIFT) |
1045 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK)
1046 << AIC3X_BUTTON_DEBOUNCE_SHIFT);
1047
1048 if (detect & AIC3X_HEADSET_DETECT_MASK)
1049 val |= AIC3X_HEADSET_DETECT_ENABLED;
1050
1051 aic3x_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
1052 }
1053 EXPORT_SYMBOL_GPL(aic3x_set_headset_detection);
1054
1055 int aic3x_headset_detected(struct snd_soc_codec *codec)
1056 {
1057 u8 val;
1058 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1059 return (val >> 4) & 1;
1060 }
1061 EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1062
1063 int aic3x_button_pressed(struct snd_soc_codec *codec)
1064 {
1065 u8 val;
1066 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1067 return (val >> 5) & 1;
1068 }
1069 EXPORT_SYMBOL_GPL(aic3x_button_pressed);
1070
1071 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1072 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1073 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1074
1075 struct snd_soc_dai aic3x_dai = {
1076 .name = "tlv320aic3x",
1077 .playback = {
1078 .stream_name = "Playback",
1079 .channels_min = 1,
1080 .channels_max = 2,
1081 .rates = AIC3X_RATES,
1082 .formats = AIC3X_FORMATS,},
1083 .capture = {
1084 .stream_name = "Capture",
1085 .channels_min = 1,
1086 .channels_max = 2,
1087 .rates = AIC3X_RATES,
1088 .formats = AIC3X_FORMATS,},
1089 .ops = {
1090 .hw_params = aic3x_hw_params,
1091 .digital_mute = aic3x_mute,
1092 .set_sysclk = aic3x_set_dai_sysclk,
1093 .set_fmt = aic3x_set_dai_fmt,
1094 }
1095 };
1096 EXPORT_SYMBOL_GPL(aic3x_dai);
1097
1098 static int aic3x_suspend(struct platform_device *pdev, pm_message_t state)
1099 {
1100 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1101 struct snd_soc_codec *codec = socdev->codec;
1102
1103 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1104
1105 return 0;
1106 }
1107
1108 static int aic3x_resume(struct platform_device *pdev)
1109 {
1110 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1111 struct snd_soc_codec *codec = socdev->codec;
1112 int i;
1113 u8 data[2];
1114 u8 *cache = codec->reg_cache;
1115
1116 /* Sync reg_cache with the hardware */
1117 for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) {
1118 data[0] = i;
1119 data[1] = cache[i];
1120 codec->hw_write(codec->control_data, data, 2);
1121 }
1122
1123 aic3x_set_bias_level(codec, codec->suspend_bias_level);
1124
1125 return 0;
1126 }
1127
1128 /*
1129 * initialise the AIC3X driver
1130 * register the mixer and dsp interfaces with the kernel
1131 */
1132 static int aic3x_init(struct snd_soc_device *socdev)
1133 {
1134 struct snd_soc_codec *codec = socdev->codec;
1135 struct aic3x_setup_data *setup = socdev->codec_data;
1136 int reg, ret = 0;
1137
1138 codec->name = "tlv320aic3x";
1139 codec->owner = THIS_MODULE;
1140 codec->read = aic3x_read_reg_cache;
1141 codec->write = aic3x_write;
1142 codec->set_bias_level = aic3x_set_bias_level;
1143 codec->dai = &aic3x_dai;
1144 codec->num_dai = 1;
1145 codec->reg_cache_size = ARRAY_SIZE(aic3x_reg);
1146 codec->reg_cache = kmemdup(aic3x_reg, sizeof(aic3x_reg), GFP_KERNEL);
1147 if (codec->reg_cache == NULL)
1148 return -ENOMEM;
1149
1150 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1151 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1152
1153 /* register pcms */
1154 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1155 if (ret < 0) {
1156 printk(KERN_ERR "aic3x: failed to create pcms\n");
1157 goto pcm_err;
1158 }
1159
1160 /* DAC default volume and mute */
1161 aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1162 aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1163
1164 /* DAC to HP default volume and route to Output mixer */
1165 aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1166 aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1167 aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1168 aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1169 /* DAC to Line Out default volume and route to Output mixer */
1170 aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1171 aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1172 /* DAC to Mono Line Out default volume and route to Output mixer */
1173 aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1174 aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1175
1176 /* unmute all outputs */
1177 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1178 aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE);
1179 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1180 aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE);
1181 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1182 aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1183 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1184 aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1185 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1186 aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE);
1187 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1188 aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1189 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1190 aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE);
1191
1192 /* ADC default volume and unmute */
1193 aic3x_write(codec, LADC_VOL, DEFAULT_GAIN);
1194 aic3x_write(codec, RADC_VOL, DEFAULT_GAIN);
1195 /* By default route Line1 to ADC PGA mixer */
1196 aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1197 aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1198
1199 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1200 aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1201 aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1202 aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1203 aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1204 /* PGA to Line Out default volume, disconnect from Output Mixer */
1205 aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1206 aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1207 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1208 aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1209 aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1210
1211 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1212 aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1213 aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1214 aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1215 aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1216 /* Line2 Line Out default volume, disconnect from Output Mixer */
1217 aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1218 aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1219 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1220 aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1221 aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1222
1223 /* off, with power on */
1224 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1225
1226 /* setup GPIO functions */
1227 aic3x_write(codec, AIC3X_GPIO1_REG, (setup->gpio_func[0] & 0xf) << 4);
1228 aic3x_write(codec, AIC3X_GPIO2_REG, (setup->gpio_func[1] & 0xf) << 4);
1229
1230 aic3x_add_controls(codec);
1231 aic3x_add_widgets(codec);
1232 ret = snd_soc_init_card(socdev);
1233 if (ret < 0) {
1234 printk(KERN_ERR "aic3x: failed to register card\n");
1235 goto card_err;
1236 }
1237
1238 return ret;
1239
1240 card_err:
1241 snd_soc_free_pcms(socdev);
1242 snd_soc_dapm_free(socdev);
1243 pcm_err:
1244 kfree(codec->reg_cache);
1245 return ret;
1246 }
1247
1248 static struct snd_soc_device *aic3x_socdev;
1249
1250 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1251 /*
1252 * AIC3X 2 wire address can be up to 4 devices with device addresses
1253 * 0x18, 0x19, 0x1A, 0x1B
1254 */
1255
1256 /*
1257 * If the i2c layer weren't so broken, we could pass this kind of data
1258 * around
1259 */
1260 static int aic3x_i2c_probe(struct i2c_client *i2c,
1261 const struct i2c_device_id *id)
1262 {
1263 struct snd_soc_device *socdev = aic3x_socdev;
1264 struct snd_soc_codec *codec = socdev->codec;
1265 int ret;
1266
1267 i2c_set_clientdata(i2c, codec);
1268 codec->control_data = i2c;
1269
1270 ret = aic3x_init(socdev);
1271 if (ret < 0)
1272 printk(KERN_ERR "aic3x: failed to initialise AIC3X\n");
1273 return ret;
1274 }
1275
1276 static int aic3x_i2c_remove(struct i2c_client *client)
1277 {
1278 struct snd_soc_codec *codec = i2c_get_clientdata(client);
1279 kfree(codec->reg_cache);
1280 return 0;
1281 }
1282
1283 static const struct i2c_device_id aic3x_i2c_id[] = {
1284 { "tlv320aic3x", 0 },
1285 { }
1286 };
1287 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1288
1289 /* machine i2c codec control layer */
1290 static struct i2c_driver aic3x_i2c_driver = {
1291 .driver = {
1292 .name = "aic3x I2C Codec",
1293 .owner = THIS_MODULE,
1294 },
1295 .probe = aic3x_i2c_probe,
1296 .remove = aic3x_i2c_remove,
1297 .id_table = aic3x_i2c_id,
1298 };
1299
1300 static int aic3x_i2c_read(struct i2c_client *client, u8 *value, int len)
1301 {
1302 value[0] = i2c_smbus_read_byte_data(client, value[0]);
1303 return (len == 1);
1304 }
1305
1306 static int aic3x_add_i2c_device(struct platform_device *pdev,
1307 const struct aic3x_setup_data *setup)
1308 {
1309 struct i2c_board_info info;
1310 struct i2c_adapter *adapter;
1311 struct i2c_client *client;
1312 int ret;
1313
1314 ret = i2c_add_driver(&aic3x_i2c_driver);
1315 if (ret != 0) {
1316 dev_err(&pdev->dev, "can't add i2c driver\n");
1317 return ret;
1318 }
1319
1320 memset(&info, 0, sizeof(struct i2c_board_info));
1321 info.addr = setup->i2c_address;
1322 strlcpy(info.type, "tlv320aic3x", I2C_NAME_SIZE);
1323
1324 adapter = i2c_get_adapter(setup->i2c_bus);
1325 if (!adapter) {
1326 dev_err(&pdev->dev, "can't get i2c adapter %d\n",
1327 setup->i2c_bus);
1328 goto err_driver;
1329 }
1330
1331 client = i2c_new_device(adapter, &info);
1332 i2c_put_adapter(adapter);
1333 if (!client) {
1334 dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
1335 (unsigned int)info.addr);
1336 goto err_driver;
1337 }
1338
1339 return 0;
1340
1341 err_driver:
1342 i2c_del_driver(&aic3x_i2c_driver);
1343 return -ENODEV;
1344 }
1345 #endif
1346
1347 static int aic3x_probe(struct platform_device *pdev)
1348 {
1349 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1350 struct aic3x_setup_data *setup;
1351 struct snd_soc_codec *codec;
1352 struct aic3x_priv *aic3x;
1353 int ret = 0;
1354
1355 printk(KERN_INFO "AIC3X Audio Codec %s\n", AIC3X_VERSION);
1356
1357 setup = socdev->codec_data;
1358 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1359 if (codec == NULL)
1360 return -ENOMEM;
1361
1362 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1363 if (aic3x == NULL) {
1364 kfree(codec);
1365 return -ENOMEM;
1366 }
1367
1368 codec->private_data = aic3x;
1369 socdev->codec = codec;
1370 mutex_init(&codec->mutex);
1371 INIT_LIST_HEAD(&codec->dapm_widgets);
1372 INIT_LIST_HEAD(&codec->dapm_paths);
1373
1374 aic3x_socdev = socdev;
1375 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1376 if (setup->i2c_address) {
1377 codec->hw_write = (hw_write_t) i2c_master_send;
1378 codec->hw_read = (hw_read_t) aic3x_i2c_read;
1379 ret = aic3x_add_i2c_device(pdev, setup);
1380 }
1381 #else
1382 /* Add other interfaces here */
1383 #endif
1384
1385 if (ret != 0) {
1386 kfree(codec->private_data);
1387 kfree(codec);
1388 }
1389 return ret;
1390 }
1391
1392 static int aic3x_remove(struct platform_device *pdev)
1393 {
1394 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1395 struct snd_soc_codec *codec = socdev->codec;
1396
1397 /* power down chip */
1398 if (codec->control_data)
1399 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1400
1401 snd_soc_free_pcms(socdev);
1402 snd_soc_dapm_free(socdev);
1403 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1404 i2c_unregister_device(codec->control_data);
1405 i2c_del_driver(&aic3x_i2c_driver);
1406 #endif
1407 kfree(codec->private_data);
1408 kfree(codec);
1409
1410 return 0;
1411 }
1412
1413 struct snd_soc_codec_device soc_codec_dev_aic3x = {
1414 .probe = aic3x_probe,
1415 .remove = aic3x_remove,
1416 .suspend = aic3x_suspend,
1417 .resume = aic3x_resume,
1418 };
1419 EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x);
1420
1421 static int __init aic3x_modinit(void)
1422 {
1423 return snd_soc_register_dai(&aic3x_dai);
1424 }
1425 module_init(aic3x_modinit);
1426
1427 static void __exit aic3x_exit(void)
1428 {
1429 snd_soc_unregister_dai(&aic3x_dai);
1430 }
1431 module_exit(aic3x_exit);
1432
1433 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1434 MODULE_AUTHOR("Vladimir Barinov");
1435 MODULE_LICENSE("GPL");
(Inofficial) Linux kernel tree running on the Nao robot