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Linux 6.14-rc1
[linux-stable.git] / drivers / parport / parport_serial.c
blob24d4f3a3ec3d0ee171876eb0c00736d05828606a
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Support for common PCI multi-I/O cards (which is most of them)
4 *
5 * Copyright (C) 2001 Tim Waugh <twaugh@redhat.com>
6 *
7 * Multi-function PCI cards are supposed to present separate logical
8 * devices on the bus. A common thing to do seems to be to just use
9 * one logical device with lots of base address registers for both
10 * parallel ports and serial ports. This driver is for dealing with
11 * that.
12 */
13
14 #include <linux/interrupt.h>
15 #include <linux/module.h>
16 #include <linux/parport.h>
17 #include <linux/parport_pc.h>
18 #include <linux/pci.h>
19 #include <linux/slab.h>
20 #include <linux/types.h>
21
22 #include <linux/8250_pci.h>
23
24 enum parport_pc_pci_cards {
25 titan_110l = 0,
26 titan_210l,
27 netmos_9xx5_combo,
28 netmos_9855,
29 netmos_9855_2p,
30 netmos_9900,
31 netmos_9900_2p,
32 netmos_99xx_1p,
33 avlab_1s1p,
34 avlab_1s2p,
35 avlab_2s1p,
36 siig_1s1p_10x,
37 siig_2s1p_10x,
38 siig_2p1s_20x,
39 siig_1s1p_20x,
40 siig_2s1p_20x,
41 timedia_4078a,
42 timedia_4079h,
43 timedia_4085h,
44 timedia_4088a,
45 timedia_4089a,
46 timedia_4095a,
47 timedia_4096a,
48 timedia_4078u,
49 timedia_4079a,
50 timedia_4085u,
51 timedia_4079r,
52 timedia_4079s,
53 timedia_4079d,
54 timedia_4079e,
55 timedia_4079f,
56 timedia_9079a,
57 timedia_9079b,
58 timedia_9079c,
59 wch_ch353_1s1p,
60 wch_ch353_2s1p,
61 wch_ch382_0s1p,
62 wch_ch382_2s1p,
63 brainboxes_5s1p,
64 sunix_4008a,
65 sunix_5069a,
66 sunix_5079a,
67 sunix_5099a,
68 brainboxes_uc257,
69 brainboxes_is300,
70 brainboxes_uc414,
71 brainboxes_px263,
72 };
73
74 /* each element directly indexed from enum list, above */
75 struct parport_pc_pci {
76 int numports;
77 struct { /* BAR (base address registers) numbers in the config
78 space header */
79 int lo;
80 int hi; /* -1 if not there, >6 for offset-method (max
81 BAR is 6) */
82 } addr[4];
83
84 /* If set, this is called immediately after pci_enable_device.
85 * If it returns non-zero, no probing will take place and the
86 * ports will not be used. */
87 int (*preinit_hook) (struct pci_dev *pdev, struct parport_pc_pci *card,
88 int autoirq, int autodma);
89
90 /* If set, this is called after probing for ports. If 'failed'
91 * is non-zero we couldn't use any of the ports. */
92 void (*postinit_hook) (struct pci_dev *pdev,
93 struct parport_pc_pci *card, int failed);
94 };
95
96 static int netmos_parallel_init(struct pci_dev *dev, struct parport_pc_pci *par,
97 int autoirq, int autodma)
98 {
99 /* the rule described below doesn't hold for this device */
100 if (dev->device == PCI_DEVICE_ID_NETMOS_9835 &&
101 dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
102 dev->subsystem_device == 0x0299)
103 return -ENODEV;
104
105 if (dev->device == PCI_DEVICE_ID_NETMOS_9912) {
106 par->numports = 1;
107 } else {
108 /*
109 * Netmos uses the subdevice ID to indicate the number of parallel
110 * and serial ports. The form is 0x00PS, where <P> is the number of
111 * parallel ports and <S> is the number of serial ports.
112 */
113 par->numports = (dev->subsystem_device & 0xf0) >> 4;
114 if (par->numports > ARRAY_SIZE(par->addr))
115 par->numports = ARRAY_SIZE(par->addr);
116 }
117
118 return 0;
119 }
120
121 static struct parport_pc_pci cards[] = {
122 /* titan_110l */ { 1, { { 3, -1 }, } },
123 /* titan_210l */ { 1, { { 3, -1 }, } },
124 /* netmos_9xx5_combo */ { 1, { { 2, -1 }, }, netmos_parallel_init },
125 /* netmos_9855 */ { 1, { { 0, -1 }, }, netmos_parallel_init },
126 /* netmos_9855_2p */ { 2, { { 0, -1 }, { 2, -1 }, } },
127 /* netmos_9900 */ {1, { { 3, 4 }, }, netmos_parallel_init },
128 /* netmos_9900_2p */ {2, { { 0, 1 }, { 3, 4 }, } },
129 /* netmos_99xx_1p */ {1, { { 0, 1 }, } },
130 /* avlab_1s1p */ { 1, { { 1, 2}, } },
131 /* avlab_1s2p */ { 2, { { 1, 2}, { 3, 4 },} },
132 /* avlab_2s1p */ { 1, { { 2, 3}, } },
133 /* siig_1s1p_10x */ { 1, { { 3, 4 }, } },
134 /* siig_2s1p_10x */ { 1, { { 4, 5 }, } },
135 /* siig_2p1s_20x */ { 2, { { 1, 2 }, { 3, 4 }, } },
136 /* siig_1s1p_20x */ { 1, { { 1, 2 }, } },
137 /* siig_2s1p_20x */ { 1, { { 2, 3 }, } },
138 /* timedia_4078a */ { 1, { { 2, -1 }, } },
139 /* timedia_4079h */ { 1, { { 2, 3 }, } },
140 /* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } },
141 /* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } },
142 /* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } },
143 /* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } },
144 /* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } },
145 /* timedia_4078u */ { 1, { { 2, -1 }, } },
146 /* timedia_4079a */ { 1, { { 2, 3 }, } },
147 /* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } },
148 /* timedia_4079r */ { 1, { { 2, 3 }, } },
149 /* timedia_4079s */ { 1, { { 2, 3 }, } },
150 /* timedia_4079d */ { 1, { { 2, 3 }, } },
151 /* timedia_4079e */ { 1, { { 2, 3 }, } },
152 /* timedia_4079f */ { 1, { { 2, 3 }, } },
153 /* timedia_9079a */ { 1, { { 2, 3 }, } },
154 /* timedia_9079b */ { 1, { { 2, 3 }, } },
155 /* timedia_9079c */ { 1, { { 2, 3 }, } },
156 /* wch_ch353_1s1p*/ { 1, { { 1, -1}, } },
157 /* wch_ch353_2s1p*/ { 1, { { 2, -1}, } },
158 /* wch_ch382_0s1p*/ { 1, { { 2, -1}, } },
159 /* wch_ch382_2s1p*/ { 1, { { 2, -1}, } },
160 /* brainboxes_5s1p */ { 1, { { 3, -1 }, } },
161 /* sunix_4008a */ { 1, { { 1, 2 }, } },
162 /* sunix_5069a */ { 1, { { 1, 2 }, } },
163 /* sunix_5079a */ { 1, { { 1, 2 }, } },
164 /* sunix_5099a */ { 1, { { 1, 2 }, } },
165 /* brainboxes_uc257 */ { 1, { { 3, -1 }, } },
166 /* brainboxes_is300 */ { 1, { { 3, -1 }, } },
167 /* brainboxes_uc414 */ { 1, { { 3, -1 }, } },
168 /* brainboxes_px263 */ { 1, { { 3, -1 }, } },
169 };
170
171 static struct pci_device_id parport_serial_pci_tbl[] = {
172 /* PCI cards */
173 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_110L,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_110l },
175 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_210L,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_210l },
177 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9735,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
179 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9745,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
181 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
183 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9845,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
185 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
186 0x1000, 0x0020, 0, 0, netmos_9855_2p },
187 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
188 0x1000, 0x0022, 0, 0, netmos_9855_2p },
189 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9855 },
191 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
192 0xA000, 0x3011, 0, 0, netmos_9900 },
193 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
194 0xA000, 0x3012, 0, 0, netmos_9900 },
195 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
196 0xA000, 0x3020, 0, 0, netmos_9900_2p },
197 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
198 0xA000, 0x2000, 0, 0, netmos_99xx_1p },
199 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
200 { PCI_VENDOR_ID_AFAVLAB, 0x2110,
201 PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
202 { PCI_VENDOR_ID_AFAVLAB, 0x2111,
203 PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
204 { PCI_VENDOR_ID_AFAVLAB, 0x2112,
205 PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
206 { PCI_VENDOR_ID_AFAVLAB, 0x2140,
207 PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
208 { PCI_VENDOR_ID_AFAVLAB, 0x2141,
209 PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
210 { PCI_VENDOR_ID_AFAVLAB, 0x2142,
211 PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
212 { PCI_VENDOR_ID_AFAVLAB, 0x2160,
213 PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
214 { PCI_VENDOR_ID_AFAVLAB, 0x2161,
215 PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
216 { PCI_VENDOR_ID_AFAVLAB, 0x2162,
217 PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
218 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_550,
219 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
220 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_650,
221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
222 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_850,
223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
224 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_550,
225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
226 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_650,
227 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
228 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_850,
229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
230 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_550,
231 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
232 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_650,
233 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
234 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_850,
235 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
236 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_550,
237 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
238 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_650,
239 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_20x },
240 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_850,
241 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_20x },
242 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_550,
243 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
244 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_650,
245 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
246 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_850,
247 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
248 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
249 { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a },
250 { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h },
251 { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h },
252 { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a },
253 { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a },
254 { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a },
255 { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a },
256 { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u },
257 { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a },
258 { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u },
259 { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r },
260 { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s },
261 { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d },
262 { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e },
263 { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f },
264 { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a },
265 { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b },
266 { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c },
267
268 /* WCH CARDS */
269 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH353_1S1P,
270 PCI_ANY_ID, PCI_ANY_ID, 0, 0, wch_ch353_1s1p },
271 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH353_2S1P,
272 0x4348, 0x3253, 0, 0, wch_ch353_2s1p },
273 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH382_0S1P,
274 0x1c00, 0x3050, 0, 0, wch_ch382_0s1p },
275 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH382_2S1P,
276 0x1c00, 0x3250, 0, 0, wch_ch382_2s1p },
277
278 /* BrainBoxes PX272/PX306 MIO card */
279 { PCI_VENDOR_ID_INTASHIELD, 0x4100,
280 PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_5s1p },
281
282 /* Sunix boards */
283 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, PCI_VENDOR_ID_SUNIX,
284 0x0100, 0, 0, sunix_4008a },
285 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, PCI_VENDOR_ID_SUNIX,
286 0x0101, 0, 0, sunix_5069a },
287 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, PCI_VENDOR_ID_SUNIX,
288 0x0102, 0, 0, sunix_5079a },
289 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, PCI_VENDOR_ID_SUNIX,
290 0x0104, 0, 0, sunix_5099a },
291
292 /* Brainboxes UC-203 */
293 { PCI_VENDOR_ID_INTASHIELD, 0x0bc1,
294 PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_uc257 },
295 { PCI_VENDOR_ID_INTASHIELD, 0x0bc2,
296 PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_uc257 },
297
298 /* Brainboxes UC-257 */
299 { PCI_VENDOR_ID_INTASHIELD, 0x0861,
300 PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_uc257 },
301 { PCI_VENDOR_ID_INTASHIELD, 0x0862,
302 PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_uc257 },
303 { PCI_VENDOR_ID_INTASHIELD, 0x0863,
304 PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_uc257 },
305
306 /* Brainboxes UC-414 */
307 { PCI_VENDOR_ID_INTASHIELD, 0x0e61,
308 PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_uc414 },
309
310 /* Brainboxes UC-475 */
311 { PCI_VENDOR_ID_INTASHIELD, 0x0981,
312 PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_uc257 },
313 { PCI_VENDOR_ID_INTASHIELD, 0x0982,
314 PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_uc257 },
315
316 /* Brainboxes IS-300/IS-500 */
317 { PCI_VENDOR_ID_INTASHIELD, 0x0da0,
318 PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_is300 },
319
320 /* Brainboxes PX-263/PX-295 */
321 { PCI_VENDOR_ID_INTASHIELD, 0x402c,
322 PCI_ANY_ID, PCI_ANY_ID, 0, 0, brainboxes_px263 },
323
324 { 0, } /* terminate list */
325 };
326 MODULE_DEVICE_TABLE(pci,parport_serial_pci_tbl);
327
328 /*
329 * This table describes the serial "geometry" of these boards. Any
330 * quirks for these can be found in drivers/serial/8250_pci.c
331 *
332 * Cards not tested are marked n/t
333 * If you have one of these cards and it works for you, please tell me..
334 */
335 static struct pciserial_board pci_parport_serial_boards[] = {
336 [titan_110l] = {
337 .flags = FL_BASE1 | FL_BASE_BARS,
338 .num_ports = 1,
339 .base_baud = 921600,
340 .uart_offset = 8,
341 },
342 [titan_210l] = {
343 .flags = FL_BASE1 | FL_BASE_BARS,
344 .num_ports = 2,
345 .base_baud = 921600,
346 .uart_offset = 8,
347 },
348 [netmos_9xx5_combo] = {
349 .flags = FL_BASE0 | FL_BASE_BARS,
350 .num_ports = 1,
351 .base_baud = 115200,
352 .uart_offset = 8,
353 },
354 [netmos_9855] = {
355 .flags = FL_BASE2 | FL_BASE_BARS,
356 .num_ports = 1,
357 .base_baud = 115200,
358 .uart_offset = 8,
359 },
360 [netmos_9855_2p] = {
361 .flags = FL_BASE4 | FL_BASE_BARS,
362 .num_ports = 1,
363 .base_baud = 115200,
364 .uart_offset = 8,
365 },
366 [netmos_9900] = { /* n/t */
367 .flags = FL_BASE0 | FL_BASE_BARS,
368 .num_ports = 1,
369 .base_baud = 115200,
370 .uart_offset = 8,
371 },
372 [netmos_9900_2p] = { /* parallel only */ /* n/t */
373 .flags = FL_BASE0,
374 .num_ports = 0,
375 .base_baud = 115200,
376 .uart_offset = 8,
377 },
378 [netmos_99xx_1p] = { /* parallel only */ /* n/t */
379 .flags = FL_BASE0,
380 .num_ports = 0,
381 .base_baud = 115200,
382 .uart_offset = 8,
383 },
384 [avlab_1s1p] = { /* n/t */
385 .flags = FL_BASE0 | FL_BASE_BARS,
386 .num_ports = 1,
387 .base_baud = 115200,
388 .uart_offset = 8,
389 },
390 [avlab_1s2p] = { /* n/t */
391 .flags = FL_BASE0 | FL_BASE_BARS,
392 .num_ports = 1,
393 .base_baud = 115200,
394 .uart_offset = 8,
395 },
396 [avlab_2s1p] = { /* n/t */
397 .flags = FL_BASE0 | FL_BASE_BARS,
398 .num_ports = 2,
399 .base_baud = 115200,
400 .uart_offset = 8,
401 },
402 [siig_1s1p_10x] = {
403 .flags = FL_BASE2,
404 .num_ports = 1,
405 .base_baud = 460800,
406 .uart_offset = 8,
407 },
408 [siig_2s1p_10x] = {
409 .flags = FL_BASE2,
410 .num_ports = 1,
411 .base_baud = 921600,
412 .uart_offset = 8,
413 },
414 [siig_2p1s_20x] = {
415 .flags = FL_BASE0,
416 .num_ports = 1,
417 .base_baud = 921600,
418 .uart_offset = 8,
419 },
420 [siig_1s1p_20x] = {
421 .flags = FL_BASE0,
422 .num_ports = 1,
423 .base_baud = 921600,
424 .uart_offset = 8,
425 },
426 [siig_2s1p_20x] = {
427 .flags = FL_BASE0,
428 .num_ports = 1,
429 .base_baud = 921600,
430 .uart_offset = 8,
431 },
432 [timedia_4078a] = {
433 .flags = FL_BASE0|FL_BASE_BARS,
434 .num_ports = 1,
435 .base_baud = 921600,
436 .uart_offset = 8,
437 },
438 [timedia_4079h] = {
439 .flags = FL_BASE0|FL_BASE_BARS,
440 .num_ports = 1,
441 .base_baud = 921600,
442 .uart_offset = 8,
443 },
444 [timedia_4085h] = {
445 .flags = FL_BASE0|FL_BASE_BARS,
446 .num_ports = 1,
447 .base_baud = 921600,
448 .uart_offset = 8,
449 },
450 [timedia_4088a] = {
451 .flags = FL_BASE0|FL_BASE_BARS,
452 .num_ports = 1,
453 .base_baud = 921600,
454 .uart_offset = 8,
455 },
456 [timedia_4089a] = {
457 .flags = FL_BASE0|FL_BASE_BARS,
458 .num_ports = 1,
459 .base_baud = 921600,
460 .uart_offset = 8,
461 },
462 [timedia_4095a] = {
463 .flags = FL_BASE0|FL_BASE_BARS,
464 .num_ports = 1,
465 .base_baud = 921600,
466 .uart_offset = 8,
467 },
468 [timedia_4096a] = {
469 .flags = FL_BASE0|FL_BASE_BARS,
470 .num_ports = 1,
471 .base_baud = 921600,
472 .uart_offset = 8,
473 },
474 [timedia_4078u] = {
475 .flags = FL_BASE0|FL_BASE_BARS,
476 .num_ports = 1,
477 .base_baud = 921600,
478 .uart_offset = 8,
479 },
480 [timedia_4079a] = {
481 .flags = FL_BASE0|FL_BASE_BARS,
482 .num_ports = 1,
483 .base_baud = 921600,
484 .uart_offset = 8,
485 },
486 [timedia_4085u] = {
487 .flags = FL_BASE0|FL_BASE_BARS,
488 .num_ports = 1,
489 .base_baud = 921600,
490 .uart_offset = 8,
491 },
492 [timedia_4079r] = {
493 .flags = FL_BASE0|FL_BASE_BARS,
494 .num_ports = 1,
495 .base_baud = 921600,
496 .uart_offset = 8,
497 },
498 [timedia_4079s] = {
499 .flags = FL_BASE0|FL_BASE_BARS,
500 .num_ports = 1,
501 .base_baud = 921600,
502 .uart_offset = 8,
503 },
504 [timedia_4079d] = {
505 .flags = FL_BASE0|FL_BASE_BARS,
506 .num_ports = 1,
507 .base_baud = 921600,
508 .uart_offset = 8,
509 },
510 [timedia_4079e] = {
511 .flags = FL_BASE0|FL_BASE_BARS,
512 .num_ports = 1,
513 .base_baud = 921600,
514 .uart_offset = 8,
515 },
516 [timedia_4079f] = {
517 .flags = FL_BASE0|FL_BASE_BARS,
518 .num_ports = 1,
519 .base_baud = 921600,
520 .uart_offset = 8,
521 },
522 [timedia_9079a] = {
523 .flags = FL_BASE0|FL_BASE_BARS,
524 .num_ports = 1,
525 .base_baud = 921600,
526 .uart_offset = 8,
527 },
528 [timedia_9079b] = {
529 .flags = FL_BASE0|FL_BASE_BARS,
530 .num_ports = 1,
531 .base_baud = 921600,
532 .uart_offset = 8,
533 },
534 [timedia_9079c] = {
535 .flags = FL_BASE0|FL_BASE_BARS,
536 .num_ports = 1,
537 .base_baud = 921600,
538 .uart_offset = 8,
539 },
540 [wch_ch353_1s1p] = {
541 .flags = FL_BASE0|FL_BASE_BARS,
542 .num_ports = 1,
543 .base_baud = 115200,
544 .uart_offset = 8,
545 },
546 [wch_ch353_2s1p] = {
547 .flags = FL_BASE0|FL_BASE_BARS,
548 .num_ports = 2,
549 .base_baud = 115200,
550 .uart_offset = 8,
551 },
552 [wch_ch382_0s1p] = {
553 .flags = FL_BASE0,
554 .num_ports = 0,
555 .base_baud = 115200,
556 .uart_offset = 8,
557 },
558 [wch_ch382_2s1p] = {
559 .flags = FL_BASE0,
560 .num_ports = 2,
561 .base_baud = 115200,
562 .uart_offset = 8,
563 .first_offset = 0xC0,
564 },
565 [brainboxes_5s1p] = {
566 .flags = FL_BASE2,
567 .num_ports = 5,
568 .base_baud = 921600,
569 .uart_offset = 8,
570 },
571 [sunix_4008a] = {
572 .num_ports = 0,
573 },
574 [sunix_5069a] = {
575 .num_ports = 1,
576 .base_baud = 921600,
577 .uart_offset = 0x8,
578 },
579 [sunix_5079a] = {
580 .num_ports = 2,
581 .base_baud = 921600,
582 .uart_offset = 0x8,
583 },
584 [sunix_5099a] = {
585 .num_ports = 4,
586 .base_baud = 921600,
587 .uart_offset = 0x8,
588 },
589 [brainboxes_uc257] = {
590 .flags = FL_BASE2,
591 .num_ports = 2,
592 .base_baud = 115200,
593 .uart_offset = 8,
594 },
595 [brainboxes_is300] = {
596 .flags = FL_BASE2,
597 .num_ports = 1,
598 .base_baud = 115200,
599 .uart_offset = 8,
600 },
601 [brainboxes_uc414] = {
602 .flags = FL_BASE2,
603 .num_ports = 4,
604 .base_baud = 115200,
605 .uart_offset = 8,
606 },
607 [brainboxes_px263] = {
608 .flags = FL_BASE2,
609 .num_ports = 4,
610 .base_baud = 921600,
611 .uart_offset = 8,
612 },
613 };
614
615 struct parport_serial_private {
616 struct serial_private *serial;
617 int num_par;
618 struct parport *port[PARPORT_MAX];
619 struct parport_pc_pci par;
620 };
621
622 /* Register the serial port(s) of a PCI card. */
623 static int serial_register(struct pci_dev *dev, const struct pci_device_id *id)
624 {
625 struct parport_serial_private *priv = pci_get_drvdata (dev);
626 struct pciserial_board *board;
627 struct serial_private *serial;
628
629 board = &pci_parport_serial_boards[id->driver_data];
630 if (board->num_ports == 0)
631 return 0;
632
633 serial = pciserial_init_ports(dev, board);
634 if (IS_ERR(serial))
635 return PTR_ERR(serial);
636
637 priv->serial = serial;
638 return 0;
639 }
640
641 /* Register the parallel port(s) of a PCI card. */
642 static int parport_register(struct pci_dev *dev, const struct pci_device_id *id)
643 {
644 struct parport_pc_pci *card;
645 struct parport_serial_private *priv = pci_get_drvdata (dev);
646 int n, success = 0;
647
648 priv->par = cards[id->driver_data];
649 card = &priv->par;
650 if (card->preinit_hook &&
651 card->preinit_hook (dev, card, PARPORT_IRQ_NONE, PARPORT_DMA_NONE))
652 return -ENODEV;
653
654 for (n = 0; n < card->numports; n++) {
655 struct parport *port;
656 int lo = card->addr[n].lo;
657 int hi = card->addr[n].hi;
658 unsigned long io_lo, io_hi;
659 int irq;
660
661 if (priv->num_par == ARRAY_SIZE (priv->port)) {
662 dev_warn(&dev->dev,
663 "only %zu parallel ports supported (%d reported)\n",
664 ARRAY_SIZE(priv->port), card->numports);
665 break;
666 }
667
668 io_lo = pci_resource_start (dev, lo);
669 io_hi = 0;
670 if ((hi >= 0) && (hi <= 6))
671 io_hi = pci_resource_start (dev, hi);
672 else if (hi > 6)
673 io_lo += hi; /* Reinterpret the meaning of
674 "hi" as an offset (see SYBA
675 def.) */
676 /* TODO: test if sharing interrupts works */
677 irq = pci_irq_vector(dev, 0);
678 if (irq < 0)
679 return irq;
680 if (irq == 0)
681 irq = PARPORT_IRQ_NONE;
682 if (irq == PARPORT_IRQ_NONE) {
683 dev_dbg(&dev->dev,
684 "PCI parallel port detected: I/O at %#lx(%#lx)\n",
685 io_lo, io_hi);
686 } else {
687 dev_dbg(&dev->dev,
688 "PCI parallel port detected: I/O at %#lx(%#lx), IRQ %d\n",
689 io_lo, io_hi, irq);
690 }
691 port = parport_pc_probe_port (io_lo, io_hi, irq,
692 PARPORT_DMA_NONE, &dev->dev, IRQF_SHARED);
693 if (port) {
694 priv->port[priv->num_par++] = port;
695 success = 1;
696 }
697 }
698
699 if (card->postinit_hook)
700 card->postinit_hook (dev, card, !success);
701
702 return 0;
703 }
704
705 static int parport_serial_pci_probe(struct pci_dev *dev,
706 const struct pci_device_id *id)
707 {
708 struct parport_serial_private *priv;
709 int err;
710
711 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
712 if (!priv)
713 return -ENOMEM;
714
715 pci_set_drvdata (dev, priv);
716
717 err = pcim_enable_device(dev);
718 if (err)
719 return err;
720
721 err = parport_register(dev, id);
722 if (err)
723 return err;
724
725 err = serial_register(dev, id);
726 if (err) {
727 int i;
728 for (i = 0; i < priv->num_par; i++)
729 parport_pc_unregister_port (priv->port[i]);
730 return err;
731 }
732
733 return 0;
734 }
735
736 static void parport_serial_pci_remove(struct pci_dev *dev)
737 {
738 struct parport_serial_private *priv = pci_get_drvdata (dev);
739 int i;
740
741 // Serial ports
742 if (priv->serial)
743 pciserial_remove_ports(priv->serial);
744
745 // Parallel ports
746 for (i = 0; i < priv->num_par; i++)
747 parport_pc_unregister_port (priv->port[i]);
748
749 return;
750 }
751
752 static int __maybe_unused parport_serial_pci_suspend(struct device *dev)
753 {
754 struct parport_serial_private *priv = dev_get_drvdata(dev);
755
756 if (priv->serial)
757 pciserial_suspend_ports(priv->serial);
758
759 /* FIXME: What about parport? */
760 return 0;
761 }
762
763 static int __maybe_unused parport_serial_pci_resume(struct device *dev)
764 {
765 struct parport_serial_private *priv = dev_get_drvdata(dev);
766
767 if (priv->serial)
768 pciserial_resume_ports(priv->serial);
769
770 /* FIXME: What about parport? */
771 return 0;
772 }
773
774 static SIMPLE_DEV_PM_OPS(parport_serial_pm_ops,
775 parport_serial_pci_suspend, parport_serial_pci_resume);
776
777 static struct pci_driver parport_serial_pci_driver = {
778 .name = "parport_serial",
779 .id_table = parport_serial_pci_tbl,
780 .probe = parport_serial_pci_probe,
781 .remove = parport_serial_pci_remove,
782 .driver = {
783 .pm = &parport_serial_pm_ops,
784 },
785 };
786 module_pci_driver(parport_serial_pci_driver);
787
788 MODULE_AUTHOR("Tim Waugh <twaugh@redhat.com>");
789 MODULE_DESCRIPTION("Driver for common parallel+serial multi-I/O PCI cards");
790 MODULE_LICENSE("GPL");
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