include/dt-bindings/memory/mt8186-memory-port.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (c) 2022 MediaTek Inc.
   4  *
   5  * Author: Anan Sun <anan.sun@mediatek.com>
   6  * Author: Yong Wu <yong.wu@mediatek.com>
   7  */
   8 #ifndef _DT_BINDINGS_MEMORY_MT8186_LARB_PORT_H_
   9 #define _DT_BINDINGS_MEMORY_MT8186_LARB_PORT_H_
  10
  11 #include <dt-bindings/memory/mtk-memory-port.h>
  12
  13 /*
  14  * MM IOMMU supports 16GB dma address. We separate it to four ranges:
  15  * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
  16  * locate in anyone region. BUT:
  17  * a) Make sure all the ports inside a larb are in one range.
  18  * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
  19  *
  20  * This is the suggested mapping in this SoC:
  21  *
  22  * modules    dma-address-region        larbs-ports
  23  * disp         0 ~ 4G                  larb0/1/2
  24  * vcodec      4G ~ 8G                  larb4/7
  25  * cam/mdp     8G ~ 12G                 the other larbs.
  26  * N/A         12G ~ 16G
  27  * CCU0   0x24000_0000 ~ 0x243ff_ffff   larb13: port 9/10
  28  * CCU1   0x24400_0000 ~ 0x247ff_ffff   larb14: port 4/5
  29  */
  30
  31 /* MM IOMMU ports */
  32 /* LARB 0 -- MMSYS */
  33 #define IOMMU_PORT_L0_DISP_POSTMASK0    MTK_M4U_ID(0, 0)
  34 #define IOMMU_PORT_L0_REVERSED          MTK_M4U_ID(0, 1)
  35 #define IOMMU_PORT_L0_OVL_RDMA0         MTK_M4U_ID(0, 2)
  36 #define IOMMU_PORT_L0_DISP_FAKE0        MTK_M4U_ID(0, 3)
  37
  38 /* LARB 1 -- MMSYS */
  39 #define IOMMU_PORT_L1_DISP_RDMA1        MTK_M4U_ID(1, 0)
  40 #define IOMMU_PORT_L1_OVL_2L_RDMA0      MTK_M4U_ID(1, 1)
  41 #define IOMMU_PORT_L1_DISP_RDMA0        MTK_M4U_ID(1, 2)
  42 #define IOMMU_PORT_L1_DISP_WDMA0        MTK_M4U_ID(1, 3)
  43 #define IOMMU_PORT_L1_DISP_FAKE1        MTK_M4U_ID(1, 4)
  44
  45 /* LARB 2 -- MMSYS */
  46 #define IOMMU_PORT_L2_MDP_RDMA0         MTK_M4U_ID(2, 0)
  47 #define IOMMU_PORT_L2_MDP_RDMA1         MTK_M4U_ID(2, 1)
  48 #define IOMMU_PORT_L2_MDP_WROT0         MTK_M4U_ID(2, 2)
  49 #define IOMMU_PORT_L2_MDP_WROT1         MTK_M4U_ID(2, 3)
  50 #define IOMMU_PORT_L2_DISP_FAKE0        MTK_M4U_ID(2, 4)
  51
  52 /* LARB 4 -- VDEC */
  53 #define IOMMU_PORT_L4_HW_VDEC_MC_EXT            MTK_M4U_ID(4, 0)
  54 #define IOMMU_PORT_L4_HW_VDEC_UFO_EXT           MTK_M4U_ID(4, 1)
  55 #define IOMMU_PORT_L4_HW_VDEC_PP_EXT            MTK_M4U_ID(4, 2)
  56 #define IOMMU_PORT_L4_HW_VDEC_PRED_RD_EXT       MTK_M4U_ID(4, 3)
  57 #define IOMMU_PORT_L4_HW_VDEC_PRED_WR_EXT       MTK_M4U_ID(4, 4)
  58 #define IOMMU_PORT_L4_HW_VDEC_PPWRAP_EXT        MTK_M4U_ID(4, 5)
  59 #define IOMMU_PORT_L4_HW_VDEC_TILE_EXT          MTK_M4U_ID(4, 6)
  60 #define IOMMU_PORT_L4_HW_VDEC_VLD_EXT           MTK_M4U_ID(4, 7)
  61 #define IOMMU_PORT_L4_HW_VDEC_VLD2_EXT          MTK_M4U_ID(4, 8)
  62 #define IOMMU_PORT_L4_HW_VDEC_AVC_MV_EXT        MTK_M4U_ID(4, 9)
  63 #define IOMMU_PORT_L4_HW_VDEC_UFO_ENC_EXT       MTK_M4U_ID(4, 10)
  64 #define IOMMU_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT   MTK_M4U_ID(4, 11)
  65 #define IOMMU_PORT_L4_HW_MINI_MDP_R0_EXT        MTK_M4U_ID(4, 12)
  66 #define IOMMU_PORT_L4_HW_MINI_MDP_W0_EXT        MTK_M4U_ID(4, 13)
  67
  68 /* LARB 7 -- VENC */
  69 #define IOMMU_PORT_L7_VENC_RCPU         MTK_M4U_ID(7, 0)
  70 #define IOMMU_PORT_L7_VENC_REC          MTK_M4U_ID(7, 1)
  71 #define IOMMU_PORT_L7_VENC_BSDMA        MTK_M4U_ID(7, 2)
  72 #define IOMMU_PORT_L7_VENC_SV_COMV      MTK_M4U_ID(7, 3)
  73 #define IOMMU_PORT_L7_VENC_RD_COMV      MTK_M4U_ID(7, 4)
  74 #define IOMMU_PORT_L7_VENC_CUR_LUMA     MTK_M4U_ID(7, 5)
  75 #define IOMMU_PORT_L7_VENC_CUR_CHROMA   MTK_M4U_ID(7, 6)
  76 #define IOMMU_PORT_L7_VENC_REF_LUMA     MTK_M4U_ID(7, 7)
  77 #define IOMMU_PORT_L7_VENC_REF_CHROMA   MTK_M4U_ID(7, 8)
  78 #define IOMMU_PORT_L7_JPGENC_Y_RDMA     MTK_M4U_ID(7, 9)
  79 #define IOMMU_PORT_L7_JPGENC_C_RDMA     MTK_M4U_ID(7, 10)
  80 #define IOMMU_PORT_L7_JPGENC_Q_TABLE    MTK_M4U_ID(7, 11)
  81 #define IOMMU_PORT_L7_JPGENC_BSDMA      MTK_M4U_ID(7, 12)
  82
  83 /* LARB 8 -- WPE */
  84 #define IOMMU_PORT_L8_WPE_RDMA_0        MTK_M4U_ID(8, 0)
  85 #define IOMMU_PORT_L8_WPE_RDMA_1        MTK_M4U_ID(8, 1)
  86 #define IOMMU_PORT_L8_WPE_WDMA_0        MTK_M4U_ID(8, 2)
  87
  88 /* LARB 9 -- IMG-1 */
  89 #define IOMMU_PORT_L9_IMG_IMGI_D1       MTK_M4U_ID(9, 0)
  90 #define IOMMU_PORT_L9_IMG_IMGBI_D1      MTK_M4U_ID(9, 1)
  91 #define IOMMU_PORT_L9_IMG_DMGI_D1       MTK_M4U_ID(9, 2)
  92 #define IOMMU_PORT_L9_IMG_DEPI_D1       MTK_M4U_ID(9, 3)
  93 #define IOMMU_PORT_L9_IMG_LCE_D1        MTK_M4U_ID(9, 4)
  94 #define IOMMU_PORT_L9_IMG_SMTI_D1       MTK_M4U_ID(9, 5)
  95 #define IOMMU_PORT_L9_IMG_SMTO_D2       MTK_M4U_ID(9, 6)
  96 #define IOMMU_PORT_L9_IMG_SMTO_D1       MTK_M4U_ID(9, 7)
  97 #define IOMMU_PORT_L9_IMG_CRZO_D1       MTK_M4U_ID(9, 8)
  98 #define IOMMU_PORT_L9_IMG_IMG3O_D1      MTK_M4U_ID(9, 9)
  99 #define IOMMU_PORT_L9_IMG_VIPI_D1       MTK_M4U_ID(9, 10)
 100 #define IOMMU_PORT_L9_IMG_SMTI_D5       MTK_M4U_ID(9, 11)
 101 #define IOMMU_PORT_L9_IMG_TIMGO_D1      MTK_M4U_ID(9, 12)
 102 #define IOMMU_PORT_L9_IMG_UFBC_W0       MTK_M4U_ID(9, 13)
 103 #define IOMMU_PORT_L9_IMG_UFBC_R0       MTK_M4U_ID(9, 14)
 104 #define IOMMU_PORT_L9_IMG_WPE_RDMA1     MTK_M4U_ID(9, 15)
 105 #define IOMMU_PORT_L9_IMG_WPE_RDMA0     MTK_M4U_ID(9, 16)
 106 #define IOMMU_PORT_L9_IMG_WPE_WDMA      MTK_M4U_ID(9, 17)
 107 #define IOMMU_PORT_L9_IMG_MFB_RDMA0     MTK_M4U_ID(9, 18)
 108 #define IOMMU_PORT_L9_IMG_MFB_RDMA1     MTK_M4U_ID(9, 19)
 109 #define IOMMU_PORT_L9_IMG_MFB_RDMA2     MTK_M4U_ID(9, 20)
 110 #define IOMMU_PORT_L9_IMG_MFB_RDMA3     MTK_M4U_ID(9, 21)
 111 #define IOMMU_PORT_L9_IMG_MFB_RDMA4     MTK_M4U_ID(9, 22)
 112 #define IOMMU_PORT_L9_IMG_MFB_RDMA5     MTK_M4U_ID(9, 23)
 113 #define IOMMU_PORT_L9_IMG_MFB_WDMA0     MTK_M4U_ID(9, 24)
 114 #define IOMMU_PORT_L9_IMG_MFB_WDMA1     MTK_M4U_ID(9, 25)
 115 #define IOMMU_PORT_L9_IMG_RESERVE6      MTK_M4U_ID(9, 26)
 116 #define IOMMU_PORT_L9_IMG_RESERVE7      MTK_M4U_ID(9, 27)
 117 #define IOMMU_PORT_L9_IMG_RESERVE8      MTK_M4U_ID(9, 28)
 118
 119 /* LARB 11 -- IMG-2 */
 120 #define IOMMU_PORT_L11_IMG_IMGI_D1      MTK_M4U_ID(11, 0)
 121 #define IOMMU_PORT_L11_IMG_IMGBI_D1     MTK_M4U_ID(11, 1)
 122 #define IOMMU_PORT_L11_IMG_DMGI_D1      MTK_M4U_ID(11, 2)
 123 #define IOMMU_PORT_L11_IMG_DEPI_D1      MTK_M4U_ID(11, 3)
 124 #define IOMMU_PORT_L11_IMG_LCE_D1       MTK_M4U_ID(11, 4)
 125 #define IOMMU_PORT_L11_IMG_SMTI_D1      MTK_M4U_ID(11, 5)
 126 #define IOMMU_PORT_L11_IMG_SMTO_D2      MTK_M4U_ID(11, 6)
 127 #define IOMMU_PORT_L11_IMG_SMTO_D1      MTK_M4U_ID(11, 7)
 128 #define IOMMU_PORT_L11_IMG_CRZO_D1      MTK_M4U_ID(11, 8)
 129 #define IOMMU_PORT_L11_IMG_IMG3O_D1     MTK_M4U_ID(11, 9)
 130 #define IOMMU_PORT_L11_IMG_VIPI_D1      MTK_M4U_ID(11, 10)
 131 #define IOMMU_PORT_L11_IMG_SMTI_D5      MTK_M4U_ID(11, 11)
 132 #define IOMMU_PORT_L11_IMG_TIMGO_D1     MTK_M4U_ID(11, 12)
 133 #define IOMMU_PORT_L11_IMG_UFBC_W0      MTK_M4U_ID(11, 13)
 134 #define IOMMU_PORT_L11_IMG_UFBC_R0      MTK_M4U_ID(11, 14)
 135 #define IOMMU_PORT_L11_IMG_WPE_RDMA1    MTK_M4U_ID(11, 15)
 136 #define IOMMU_PORT_L11_IMG_WPE_RDMA0    MTK_M4U_ID(11, 16)
 137 #define IOMMU_PORT_L11_IMG_WPE_WDMA     MTK_M4U_ID(11, 17)
 138 #define IOMMU_PORT_L11_IMG_MFB_RDMA0    MTK_M4U_ID(11, 18)
 139 #define IOMMU_PORT_L11_IMG_MFB_RDMA1    MTK_M4U_ID(11, 19)
 140 #define IOMMU_PORT_L11_IMG_MFB_RDMA2    MTK_M4U_ID(11, 20)
 141 #define IOMMU_PORT_L11_IMG_MFB_RDMA3    MTK_M4U_ID(11, 21)
 142 #define IOMMU_PORT_L11_IMG_MFB_RDMA4    MTK_M4U_ID(11, 22)
 143 #define IOMMU_PORT_L11_IMG_MFB_RDMA5    MTK_M4U_ID(11, 23)
 144 #define IOMMU_PORT_L11_IMG_MFB_WDMA0    MTK_M4U_ID(11, 24)
 145 #define IOMMU_PORT_L11_IMG_MFB_WDMA1    MTK_M4U_ID(11, 25)
 146 #define IOMMU_PORT_L11_IMG_RESERVE6     MTK_M4U_ID(11, 26)
 147 #define IOMMU_PORT_L11_IMG_RESERVE7     MTK_M4U_ID(11, 27)
 148 #define IOMMU_PORT_L11_IMG_RESERVE8     MTK_M4U_ID(11, 28)
 149
 150 /* LARB 13 -- CAM */
 151 #define IOMMU_PORT_L13_CAM_MRAWI        MTK_M4U_ID(13, 0)
 152 #define IOMMU_PORT_L13_CAM_MRAWO_0      MTK_M4U_ID(13, 1)
 153 #define IOMMU_PORT_L13_CAM_MRAWO_1      MTK_M4U_ID(13, 2)
 154 #define IOMMU_PORT_L13_CAM_CAMSV_4      MTK_M4U_ID(13, 6)
 155 #define IOMMU_PORT_L13_CAM_CAMSV_5      MTK_M4U_ID(13, 7)
 156 #define IOMMU_PORT_L13_CAM_CAMSV_6      MTK_M4U_ID(13, 8)
 157 #define IOMMU_PORT_L13_CAM_CCUI         MTK_M4U_ID(13, 9)
 158 #define IOMMU_PORT_L13_CAM_CCUO         MTK_M4U_ID(13, 10)
 159 #define IOMMU_PORT_L13_CAM_FAKE         MTK_M4U_ID(13, 11)
 160
 161 /* LARB 14 -- CAM */
 162 #define IOMMU_PORT_L14_CAM_CCUI         MTK_M4U_ID(14, 4)
 163 #define IOMMU_PORT_L14_CAM_CCUO         MTK_M4U_ID(14, 5)
 164
 165 /* LARB 16 -- RAW-A */
 166 #define IOMMU_PORT_L16_CAM_IMGO_R1_A    MTK_M4U_ID(16, 0)
 167 #define IOMMU_PORT_L16_CAM_RRZO_R1_A    MTK_M4U_ID(16, 1)
 168 #define IOMMU_PORT_L16_CAM_CQI_R1_A     MTK_M4U_ID(16, 2)
 169 #define IOMMU_PORT_L16_CAM_BPCI_R1_A    MTK_M4U_ID(16, 3)
 170 #define IOMMU_PORT_L16_CAM_YUVO_R1_A    MTK_M4U_ID(16, 4)
 171 #define IOMMU_PORT_L16_CAM_UFDI_R2_A    MTK_M4U_ID(16, 5)
 172 #define IOMMU_PORT_L16_CAM_RAWI_R2_A    MTK_M4U_ID(16, 6)
 173 #define IOMMU_PORT_L16_CAM_RAWI_R3_A    MTK_M4U_ID(16, 7)
 174 #define IOMMU_PORT_L16_CAM_AAO_R1_A     MTK_M4U_ID(16, 8)
 175 #define IOMMU_PORT_L16_CAM_AFO_R1_A     MTK_M4U_ID(16, 9)
 176 #define IOMMU_PORT_L16_CAM_FLKO_R1_A    MTK_M4U_ID(16, 10)
 177 #define IOMMU_PORT_L16_CAM_LCESO_R1_A   MTK_M4U_ID(16, 11)
 178 #define IOMMU_PORT_L16_CAM_CRZO_R1_A    MTK_M4U_ID(16, 12)
 179 #define IOMMU_PORT_L16_CAM_LTMSO_R1_A   MTK_M4U_ID(16, 13)
 180 #define IOMMU_PORT_L16_CAM_RSSO_R1_A    MTK_M4U_ID(16, 14)
 181 #define IOMMU_PORT_L16_CAM_AAHO_R1_A    MTK_M4U_ID(16, 15)
 182 #define IOMMU_PORT_L16_CAM_LSCI_R1_A    MTK_M4U_ID(16, 16)
 183
 184 /* LARB 17 -- RAW-B */
 185 #define IOMMU_PORT_L17_CAM_IMGO_R1_B    MTK_M4U_ID(17, 0)
 186 #define IOMMU_PORT_L17_CAM_RRZO_R1_B    MTK_M4U_ID(17, 1)
 187 #define IOMMU_PORT_L17_CAM_CQI_R1_B     MTK_M4U_ID(17, 2)
 188 #define IOMMU_PORT_L17_CAM_BPCI_R1_B    MTK_M4U_ID(17, 3)
 189 #define IOMMU_PORT_L17_CAM_YUVO_R1_B    MTK_M4U_ID(17, 4)
 190 #define IOMMU_PORT_L17_CAM_UFDI_R2_B    MTK_M4U_ID(17, 5)
 191 #define IOMMU_PORT_L17_CAM_RAWI_R2_B    MTK_M4U_ID(17, 6)
 192 #define IOMMU_PORT_L17_CAM_RAWI_R3_B    MTK_M4U_ID(17, 7)
 193 #define IOMMU_PORT_L17_CAM_AAO_R1_B     MTK_M4U_ID(17, 8)
 194 #define IOMMU_PORT_L17_CAM_AFO_R1_B     MTK_M4U_ID(17, 9)
 195 #define IOMMU_PORT_L17_CAM_FLKO_R1_B    MTK_M4U_ID(17, 10)
 196 #define IOMMU_PORT_L17_CAM_LCESO_R1_B   MTK_M4U_ID(17, 11)
 197 #define IOMMU_PORT_L17_CAM_CRZO_R1_B    MTK_M4U_ID(17, 12)
 198 #define IOMMU_PORT_L17_CAM_LTMSO_R1_B   MTK_M4U_ID(17, 13)
 199 #define IOMMU_PORT_L17_CAM_RSSO_R1_B    MTK_M4U_ID(17, 14)
 200 #define IOMMU_PORT_L17_CAM_AAHO_R1_B    MTK_M4U_ID(17, 15)
 201 #define IOMMU_PORT_L17_CAM_LSCI_R1_B    MTK_M4U_ID(17, 16)
 202
 203 /* LARB 19 -- IPE */
 204 #define IOMMU_PORT_L19_IPE_DVS_RDMA     MTK_M4U_ID(19, 0)
 205 #define IOMMU_PORT_L19_IPE_DVS_WDMA     MTK_M4U_ID(19, 1)
 206 #define IOMMU_PORT_L19_IPE_DVP_RDMA     MTK_M4U_ID(19, 2)
 207 #define IOMMU_PORT_L19_IPE_DVP_WDMA     MTK_M4U_ID(19, 3)
 208
 209 /* LARB 20 -- IPE */
 210 #define IOMMU_PORT_L20_IPE_FDVT_RDA     MTK_M4U_ID(20, 0)
 211 #define IOMMU_PORT_L20_IPE_FDVT_RDB     MTK_M4U_ID(20, 1)
 212 #define IOMMU_PORT_L20_IPE_FDVT_WRA     MTK_M4U_ID(20, 2)
 213 #define IOMMU_PORT_L20_IPE_FDVT_WRB     MTK_M4U_ID(20, 3)
 214 #define IOMMU_PORT_L20_IPE_RSC_RDMA0    MTK_M4U_ID(20, 4)
 215 #define IOMMU_PORT_L20_IPE_RSC_WDMA     MTK_M4U_ID(20, 5)
 216
 217 #endif