arch/loongarch/kvm/intc/pch_pic.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2024 Loongson Technology Corporation Limited
   4  */
   5
   6 #include <asm/kvm_eiointc.h>
   7 #include <asm/kvm_pch_pic.h>
   8 #include <asm/kvm_vcpu.h>
   9 #include <linux/count_zeros.h>
  10
  11 /* update the isr according to irq level and route irq to eiointc */
  12 static void pch_pic_update_irq(struct loongarch_pch_pic *s, int irq, int level)
  13 {
  14         u64 mask = BIT(irq);
  15
  16         /*
  17          * set isr and route irq to eiointc and
  18          * the route table is in htmsi_vector[]
  19          */
  20         if (level) {
  21                 if (mask & s->irr & ~s->mask) {
  22                         s->isr |= mask;
  23                         irq = s->htmsi_vector[irq];
  24                         eiointc_set_irq(s->kvm->arch.eiointc, irq, level);
  25                 }
  26         } else {
  27                 if (mask & s->isr & ~s->irr) {
  28                         s->isr &= ~mask;
  29                         irq = s->htmsi_vector[irq];
  30                         eiointc_set_irq(s->kvm->arch.eiointc, irq, level);
  31                 }
  32         }
  33 }
  34
  35 /* update batch irqs, the irq_mask is a bitmap of irqs */
  36 static void pch_pic_update_batch_irqs(struct loongarch_pch_pic *s, u64 irq_mask, int level)
  37 {
  38         int irq, bits;
  39
  40         /* find each irq by irqs bitmap and update each irq */
  41         bits = sizeof(irq_mask) * 8;
  42         irq = find_first_bit((void *)&irq_mask, bits);
  43         while (irq < bits) {
  44                 pch_pic_update_irq(s, irq, level);
  45                 bitmap_clear((void *)&irq_mask, irq, 1);
  46                 irq = find_first_bit((void *)&irq_mask, bits);
  47         }
  48 }
  49
  50 /* called when a irq is triggered in pch pic */
  51 void pch_pic_set_irq(struct loongarch_pch_pic *s, int irq, int level)
  52 {
  53         u64 mask = BIT(irq);
  54
  55         spin_lock(&s->lock);
  56         if (level)
  57                 s->irr |= mask; /* set irr */
  58         else {
  59                 /*
  60                  * In edge triggered mode, 0 does not mean to clear irq
  61                  * The irr register variable is cleared when cpu writes to the
  62                  * PCH_PIC_CLEAR_START address area
  63                  */
  64                 if (s->edge & mask) {
  65                         spin_unlock(&s->lock);
  66                         return;
  67                 }
  68                 s->irr &= ~mask;
  69         }
  70         pch_pic_update_irq(s, irq, level);
  71         spin_unlock(&s->lock);
  72 }
  73
  74 /* msi irq handler */
  75 void pch_msi_set_irq(struct kvm *kvm, int irq, int level)
  76 {
  77         eiointc_set_irq(kvm->arch.eiointc, irq, level);
  78 }
  79
  80 /*
  81  * pch pic register is 64-bit, but it is accessed by 32-bit,
  82  * so we use high to get whether low or high 32 bits we want
  83  * to read.
  84  */
  85 static u32 pch_pic_read_reg(u64 *s, int high)
  86 {
  87         u64 val = *s;
  88
  89         /* read the high 32 bits when high is 1 */
  90         return high ? (u32)(val >> 32) : (u32)val;
  91 }
  92
  93 /*
  94  * pch pic register is 64-bit, but it is accessed by 32-bit,
  95  * so we use high to get whether low or high 32 bits we want
  96  * to write.
  97  */
  98 static u32 pch_pic_write_reg(u64 *s, int high, u32 v)
  99 {
 100         u64 val = *s, data = v;
 101
 102         if (high) {
 103                 /*
 104                  * Clear val high 32 bits
 105                  * Write the high 32 bits when the high is 1
 106                  */
 107                 *s = (val << 32 >> 32) | (data << 32);
 108                 val >>= 32;
 109         } else
 110                 /*
 111                  * Clear val low 32 bits
 112                  * Write the low 32 bits when the high is 0
 113                  */
 114                 *s = (val >> 32 << 32) | v;
 115
 116         return (u32)val;
 117 }
 118
 119 static int loongarch_pch_pic_read(struct loongarch_pch_pic *s, gpa_t addr, int len, void *val)
 120 {
 121         int offset, index, ret = 0;
 122         u32 data = 0;
 123         u64 int_id = 0;
 124
 125         offset = addr - s->pch_pic_base;
 126
 127         spin_lock(&s->lock);
 128         switch (offset) {
 129         case PCH_PIC_INT_ID_START ... PCH_PIC_INT_ID_END:
 130                 /* int id version */
 131                 int_id |= (u64)PCH_PIC_INT_ID_VER << 32;
 132                 /* irq number */
 133                 int_id |= (u64)31 << (32 + 16);
 134                 /* int id value */
 135                 int_id |= PCH_PIC_INT_ID_VAL;
 136                 *(u64 *)val = int_id;
 137                 break;
 138         case PCH_PIC_MASK_START ... PCH_PIC_MASK_END:
 139                 offset -= PCH_PIC_MASK_START;
 140                 index = offset >> 2;
 141                 /* read mask reg */
 142                 data = pch_pic_read_reg(&s->mask, index);
 143                 *(u32 *)val = data;
 144                 break;
 145         case PCH_PIC_HTMSI_EN_START ... PCH_PIC_HTMSI_EN_END:
 146                 offset -= PCH_PIC_HTMSI_EN_START;
 147                 index = offset >> 2;
 148                 /* read htmsi enable reg */
 149                 data = pch_pic_read_reg(&s->htmsi_en, index);
 150                 *(u32 *)val = data;
 151                 break;
 152         case PCH_PIC_EDGE_START ... PCH_PIC_EDGE_END:
 153                 offset -= PCH_PIC_EDGE_START;
 154                 index = offset >> 2;
 155                 /* read edge enable reg */
 156                 data = pch_pic_read_reg(&s->edge, index);
 157                 *(u32 *)val = data;
 158                 break;
 159         case PCH_PIC_AUTO_CTRL0_START ... PCH_PIC_AUTO_CTRL0_END:
 160         case PCH_PIC_AUTO_CTRL1_START ... PCH_PIC_AUTO_CTRL1_END:
 161                 /* we only use default mode: fixed interrupt distribution mode */
 162                 *(u32 *)val = 0;
 163                 break;
 164         case PCH_PIC_ROUTE_ENTRY_START ... PCH_PIC_ROUTE_ENTRY_END:
 165                 /* only route to int0: eiointc */
 166                 *(u8 *)val = 1;
 167                 break;
 168         case PCH_PIC_HTMSI_VEC_START ... PCH_PIC_HTMSI_VEC_END:
 169                 offset -= PCH_PIC_HTMSI_VEC_START;
 170                 /* read htmsi vector */
 171                 data = s->htmsi_vector[offset];
 172                 *(u8 *)val = data;
 173                 break;
 174         case PCH_PIC_POLARITY_START ... PCH_PIC_POLARITY_END:
 175                 /* we only use defalut value 0: high level triggered */
 176                 *(u32 *)val = 0;
 177                 break;
 178         default:
 179                 ret = -EINVAL;
 180         }
 181         spin_unlock(&s->lock);
 182
 183         return ret;
 184 }
 185
 186 static int kvm_pch_pic_read(struct kvm_vcpu *vcpu,
 187                         struct kvm_io_device *dev,
 188                         gpa_t addr, int len, void *val)
 189 {
 190         int ret;
 191         struct loongarch_pch_pic *s = vcpu->kvm->arch.pch_pic;
 192
 193         if (!s) {
 194                 kvm_err("%s: pch pic irqchip not valid!\n", __func__);
 195                 return -EINVAL;
 196         }
 197
 198         /* statistics of pch pic reading */
 199         vcpu->kvm->stat.pch_pic_read_exits++;
 200         ret = loongarch_pch_pic_read(s, addr, len, val);
 201
 202         return ret;
 203 }
 204
 205 static int loongarch_pch_pic_write(struct loongarch_pch_pic *s, gpa_t addr,
 206                                         int len, const void *val)
 207 {
 208         int ret;
 209         u32 old, data, offset, index;
 210         u64 irq;
 211
 212         ret = 0;
 213         data = *(u32 *)val;
 214         offset = addr - s->pch_pic_base;
 215
 216         spin_lock(&s->lock);
 217         switch (offset) {
 218         case PCH_PIC_MASK_START ... PCH_PIC_MASK_END:
 219                 offset -= PCH_PIC_MASK_START;
 220                 /* get whether high or low 32 bits we want to write */
 221                 index = offset >> 2;
 222                 old = pch_pic_write_reg(&s->mask, index, data);
 223                 /* enable irq when mask value change to 0 */
 224                 irq = (old & ~data) << (32 * index);
 225                 pch_pic_update_batch_irqs(s, irq, 1);
 226                 /* disable irq when mask value change to 1 */
 227                 irq = (~old & data) << (32 * index);
 228                 pch_pic_update_batch_irqs(s, irq, 0);
 229                 break;
 230         case PCH_PIC_HTMSI_EN_START ... PCH_PIC_HTMSI_EN_END:
 231                 offset -= PCH_PIC_HTMSI_EN_START;
 232                 index = offset >> 2;
 233                 pch_pic_write_reg(&s->htmsi_en, index, data);
 234                 break;
 235         case PCH_PIC_EDGE_START ... PCH_PIC_EDGE_END:
 236                 offset -= PCH_PIC_EDGE_START;
 237                 index = offset >> 2;
 238                 /* 1: edge triggered, 0: level triggered */
 239                 pch_pic_write_reg(&s->edge, index, data);
 240                 break;
 241         case PCH_PIC_CLEAR_START ... PCH_PIC_CLEAR_END:
 242                 offset -= PCH_PIC_CLEAR_START;
 243                 index = offset >> 2;
 244                 /* write 1 to clear edge irq */
 245                 old = pch_pic_read_reg(&s->irr, index);
 246                 /*
 247                  * get the irq bitmap which is edge triggered and
 248                  * already set and to be cleared
 249                  */
 250                 irq = old & pch_pic_read_reg(&s->edge, index) & data;
 251                 /* write irr to the new state where irqs have been cleared */
 252                 pch_pic_write_reg(&s->irr, index, old & ~irq);
 253                 /* update cleared irqs */
 254                 pch_pic_update_batch_irqs(s, irq, 0);
 255                 break;
 256         case PCH_PIC_AUTO_CTRL0_START ... PCH_PIC_AUTO_CTRL0_END:
 257                 offset -= PCH_PIC_AUTO_CTRL0_START;
 258                 index = offset >> 2;
 259                 /* we only use default mode: fixed interrupt distribution mode */
 260                 pch_pic_write_reg(&s->auto_ctrl0, index, 0);
 261                 break;
 262         case PCH_PIC_AUTO_CTRL1_START ... PCH_PIC_AUTO_CTRL1_END:
 263                 offset -= PCH_PIC_AUTO_CTRL1_START;
 264                 index = offset >> 2;
 265                 /* we only use default mode: fixed interrupt distribution mode */
 266                 pch_pic_write_reg(&s->auto_ctrl1, index, 0);
 267                 break;
 268         case PCH_PIC_ROUTE_ENTRY_START ... PCH_PIC_ROUTE_ENTRY_END:
 269                 offset -= PCH_PIC_ROUTE_ENTRY_START;
 270                 /* only route to int0: eiointc */
 271                 s->route_entry[offset] = 1;
 272                 break;
 273         case PCH_PIC_HTMSI_VEC_START ... PCH_PIC_HTMSI_VEC_END:
 274                 /* route table to eiointc */
 275                 offset -= PCH_PIC_HTMSI_VEC_START;
 276                 s->htmsi_vector[offset] = (u8)data;
 277                 break;
 278         case PCH_PIC_POLARITY_START ... PCH_PIC_POLARITY_END:
 279                 offset -= PCH_PIC_POLARITY_START;
 280                 index = offset >> 2;
 281                 /* we only use defalut value 0: high level triggered */
 282                 pch_pic_write_reg(&s->polarity, index, 0);
 283                 break;
 284         default:
 285                 ret = -EINVAL;
 286                 break;
 287         }
 288         spin_unlock(&s->lock);
 289
 290         return ret;
 291 }
 292
 293 static int kvm_pch_pic_write(struct kvm_vcpu *vcpu,
 294                         struct kvm_io_device *dev,
 295                         gpa_t addr, int len, const void *val)
 296 {
 297         int ret;
 298         struct loongarch_pch_pic *s = vcpu->kvm->arch.pch_pic;
 299
 300         if (!s) {
 301                 kvm_err("%s: pch pic irqchip not valid!\n", __func__);
 302                 return -EINVAL;
 303         }
 304
 305         /* statistics of pch pic writing */
 306         vcpu->kvm->stat.pch_pic_write_exits++;
 307         ret = loongarch_pch_pic_write(s, addr, len, val);
 308
 309         return ret;
 310 }
 311
 312 static const struct kvm_io_device_ops kvm_pch_pic_ops = {
 313         .read   = kvm_pch_pic_read,
 314         .write  = kvm_pch_pic_write,
 315 };
 316
 317 static int kvm_pch_pic_init(struct kvm_device *dev, u64 addr)
 318 {
 319         int ret;
 320         struct kvm *kvm = dev->kvm;
 321         struct kvm_io_device *device;
 322         struct loongarch_pch_pic *s = dev->kvm->arch.pch_pic;
 323
 324         s->pch_pic_base = addr;
 325         device = &s->device;
 326         /* init device by pch pic writing and reading ops */
 327         kvm_iodevice_init(device, &kvm_pch_pic_ops);
 328         mutex_lock(&kvm->slots_lock);
 329         /* register pch pic device */
 330         ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, addr, PCH_PIC_SIZE, device);
 331         mutex_unlock(&kvm->slots_lock);
 332
 333         return (ret < 0) ? -EFAULT : 0;
 334 }
 335
 336 /* used by user space to get or set pch pic registers */
 337 static int kvm_pch_pic_regs_access(struct kvm_device *dev,
 338                                 struct kvm_device_attr *attr,
 339                                 bool is_write)
 340 {
 341         int addr, offset, len = 8, ret = 0;
 342         void __user *data;
 343         void *p = NULL;
 344         struct loongarch_pch_pic *s;
 345
 346         s = dev->kvm->arch.pch_pic;
 347         addr = attr->attr;
 348         data = (void __user *)attr->addr;
 349
 350         /* get pointer to pch pic register by addr */
 351         switch (addr) {
 352         case PCH_PIC_MASK_START:
 353                 p = &s->mask;
 354                 break;
 355         case PCH_PIC_HTMSI_EN_START:
 356                 p = &s->htmsi_en;
 357                 break;
 358         case PCH_PIC_EDGE_START:
 359                 p = &s->edge;
 360                 break;
 361         case PCH_PIC_AUTO_CTRL0_START:
 362                 p = &s->auto_ctrl0;
 363                 break;
 364         case PCH_PIC_AUTO_CTRL1_START:
 365                 p = &s->auto_ctrl1;
 366                 break;
 367         case PCH_PIC_ROUTE_ENTRY_START ... PCH_PIC_ROUTE_ENTRY_END:
 368                 offset = addr - PCH_PIC_ROUTE_ENTRY_START;
 369                 p = &s->route_entry[offset];
 370                 len = 1;
 371                 break;
 372         case PCH_PIC_HTMSI_VEC_START ... PCH_PIC_HTMSI_VEC_END:
 373                 offset = addr - PCH_PIC_HTMSI_VEC_START;
 374                 p = &s->htmsi_vector[offset];
 375                 len = 1;
 376                 break;
 377         case PCH_PIC_INT_IRR_START:
 378                 p = &s->irr;
 379                 break;
 380         case PCH_PIC_INT_ISR_START:
 381                 p = &s->isr;
 382                 break;
 383         case PCH_PIC_POLARITY_START:
 384                 p = &s->polarity;
 385                 break;
 386         default:
 387                 return -EINVAL;
 388         }
 389
 390         spin_lock(&s->lock);
 391         /* write or read value according to is_write */
 392         if (is_write) {
 393                 if (copy_from_user(p, data, len))
 394                         ret = -EFAULT;
 395         } else {
 396                 if (copy_to_user(data, p, len))
 397                         ret = -EFAULT;
 398         }
 399         spin_unlock(&s->lock);
 400
 401         return ret;
 402 }
 403
 404 static int kvm_pch_pic_get_attr(struct kvm_device *dev,
 405                                 struct kvm_device_attr *attr)
 406 {
 407         switch (attr->group) {
 408         case KVM_DEV_LOONGARCH_PCH_PIC_GRP_REGS:
 409                 return kvm_pch_pic_regs_access(dev, attr, false);
 410         default:
 411                 return -EINVAL;
 412         }
 413 }
 414
 415 static int kvm_pch_pic_set_attr(struct kvm_device *dev,
 416                                 struct kvm_device_attr *attr)
 417 {
 418         u64 addr;
 419         void __user *uaddr = (void __user *)(long)attr->addr;
 420
 421         switch (attr->group) {
 422         case KVM_DEV_LOONGARCH_PCH_PIC_GRP_CTRL:
 423                 switch (attr->attr) {
 424                 case KVM_DEV_LOONGARCH_PCH_PIC_CTRL_INIT:
 425                         if (copy_from_user(&addr, uaddr, sizeof(addr)))
 426                                 return -EFAULT;
 427
 428                         if (!dev->kvm->arch.pch_pic) {
 429                                 kvm_err("%s: please create pch_pic irqchip first!\n", __func__);
 430                                 return -ENODEV;
 431                         }
 432
 433                         return kvm_pch_pic_init(dev, addr);
 434                 default:
 435                         kvm_err("%s: unknown group (%d) attr (%lld)\n", __func__, attr->group,
 436                                         attr->attr);
 437                         return -EINVAL;
 438                 }
 439         case KVM_DEV_LOONGARCH_PCH_PIC_GRP_REGS:
 440                 return kvm_pch_pic_regs_access(dev, attr, true);
 441         default:
 442                 return -EINVAL;
 443         }
 444 }
 445
 446 static int kvm_setup_default_irq_routing(struct kvm *kvm)
 447 {
 448         int i, ret;
 449         u32 nr = KVM_IRQCHIP_NUM_PINS;
 450         struct kvm_irq_routing_entry *entries;
 451
 452         entries = kcalloc(nr, sizeof(*entries), GFP_KERNEL);
 453         if (!entries)
 454                 return -ENOMEM;
 455
 456         for (i = 0; i < nr; i++) {
 457                 entries[i].gsi = i;
 458                 entries[i].type = KVM_IRQ_ROUTING_IRQCHIP;
 459                 entries[i].u.irqchip.irqchip = 0;
 460                 entries[i].u.irqchip.pin = i;
 461         }
 462         ret = kvm_set_irq_routing(kvm, entries, nr, 0);
 463         kfree(entries);
 464
 465         return ret;
 466 }
 467
 468 static int kvm_pch_pic_create(struct kvm_device *dev, u32 type)
 469 {
 470         int ret;
 471         struct kvm *kvm = dev->kvm;
 472         struct loongarch_pch_pic *s;
 473
 474         /* pch pic should not has been created */
 475         if (kvm->arch.pch_pic)
 476                 return -EINVAL;
 477
 478         ret = kvm_setup_default_irq_routing(kvm);
 479         if (ret)
 480                 return -ENOMEM;
 481
 482         s = kzalloc(sizeof(struct loongarch_pch_pic), GFP_KERNEL);
 483         if (!s)
 484                 return -ENOMEM;
 485
 486         spin_lock_init(&s->lock);
 487         s->kvm = kvm;
 488         kvm->arch.pch_pic = s;
 489
 490         return 0;
 491 }
 492
 493 static void kvm_pch_pic_destroy(struct kvm_device *dev)
 494 {
 495         struct kvm *kvm;
 496         struct loongarch_pch_pic *s;
 497
 498         if (!dev || !dev->kvm || !dev->kvm->arch.pch_pic)
 499                 return;
 500
 501         kvm = dev->kvm;
 502         s = kvm->arch.pch_pic;
 503         /* unregister pch pic device and free it's memory */
 504         kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &s->device);
 505         kfree(s);
 506 }
 507
 508 static struct kvm_device_ops kvm_pch_pic_dev_ops = {
 509         .name = "kvm-loongarch-pch-pic",
 510         .create = kvm_pch_pic_create,
 511         .destroy = kvm_pch_pic_destroy,
 512         .set_attr = kvm_pch_pic_set_attr,
 513         .get_attr = kvm_pch_pic_get_attr,
 514 };
 515
 516 int kvm_loongarch_register_pch_pic_device(void)
 517 {
 518         return kvm_register_device_ops(&kvm_pch_pic_dev_ops, KVM_DEV_TYPE_LOONGARCH_PCHPIC);
 519 }