1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * LoongArch SIMD XOR operations
5 * Copyright (C) 2023 WANG Xuerui <git@xen0n.name>
11 * Process one cache line (64 bytes) per loop. This is assuming all future
12 * popular LoongArch cores are similar performance-characteristics-wise to the
17 #ifdef CONFIG_CPU_HAS_LSX
19 #define LD(reg, base, offset) \
20 "vld $vr" #reg ", %[" #base "], " #offset "\n\t"
21 #define ST(reg, base, offset) \
22 "vst $vr" #reg ", %[" #base "], " #offset "\n\t"
23 #define XOR(dj, k) "vxor.v $vr" #dj ", $vr" #dj ", $vr" #k "\n\t"
25 #define LD_INOUT_LINE(base) \
31 #define LD_AND_XOR_LINE(base) \
41 #define ST_LINE(base) \
47 #define XOR_FUNC_NAME(nr) __xor_lsx_##nr
48 #include "xor_template.c"
54 #undef LD_AND_XOR_LINE
58 #endif /* CONFIG_CPU_HAS_LSX */
60 #ifdef CONFIG_CPU_HAS_LASX
62 #define LD(reg, base, offset) \
63 "xvld $xr" #reg ", %[" #base "], " #offset "\n\t"
64 #define ST(reg, base, offset) \
65 "xvst $xr" #reg ", %[" #base "], " #offset "\n\t"
66 #define XOR(dj, k) "xvxor.v $xr" #dj ", $xr" #dj ", $xr" #k "\n\t"
68 #define LD_INOUT_LINE(base) \
72 #define LD_AND_XOR_LINE(base) \
78 #define ST_LINE(base) \
82 #define XOR_FUNC_NAME(nr) __xor_lasx_##nr
83 #include "xor_template.c"
89 #undef LD_AND_XOR_LINE
93 #endif /* CONFIG_CPU_HAS_LASX */