arch/openrisc/boot/dts/or1ksim.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3 / {
   4         compatible = "opencores,or1ksim";
   5         #address-cells = <1>;
   6         #size-cells = <1>;
   7         interrupt-parent = <&pic>;
   8
   9         aliases {
  10                 uart0 = &serial0;
  11         };
  12
  13         chosen {
  14                 bootargs = "earlycon";
  15                 stdout-path = "uart0:115200";
  16         };
  17
  18         memory@0 {
  19                 device_type = "memory";
  20                 reg = <0x00000000 0x02000000>;
  21         };
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26                 cpu@0 {
  27                         compatible = "opencores,or1200-rtlsvn481";
  28                         reg = <0>;
  29                         clock-frequency = <20000000>;
  30                 };
  31         };
  32
  33         /*
  34          * OR1K PIC is built into CPU and accessed via special purpose
  35          * registers.  It is not addressable and, hence, has no 'reg'
  36          * property.
  37          */
  38         pic: pic {
  39                 compatible = "opencores,or1k-pic";
  40                 #interrupt-cells = <1>;
  41                 interrupt-controller;
  42         };
  43
  44         serial0: serial@90000000 {
  45                 compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
  46                 reg = <0x90000000 0x100>;
  47                 interrupts = <2>;
  48                 clock-frequency = <20000000>;
  49         };
  50
  51         enet0: ethoc@92000000 {
  52                 compatible = "opencores,ethoc";
  53                 reg = <0x92000000 0x800>;
  54                 interrupts = <4>;
  55                 big-endian;
  56         };
  57 };