arch/sh/include/cpu-sh2/cpu/watchdog.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * include/asm-sh/cpu-sh2/watchdog.h
   4  *
   5  * Copyright (C) 2002, 2003 Paul Mundt
   6  */
   7 #ifndef __ASM_CPU_SH2_WATCHDOG_H
   8 #define __ASM_CPU_SH2_WATCHDOG_H
   9
  10 /*
  11  * More SH-2 brilliance .. its not good enough that we can't read
  12  * and write the same sizes to WTCNT, now we have to read and write
  13  * with different sizes at different addresses for WTCNT _and_ RSTCSR.
  14  *
  15  * At least on the bright side no one has managed to screw over WTCSR
  16  * in this fashion .. yet.
  17  */
  18 /* Register definitions */
  19 #define WTCNT           0xfffffe80
  20 #define WTCSR           0xfffffe80
  21 #define RSTCSR          0xfffffe82
  22
  23 #define WTCNT_R         (WTCNT + 1)
  24 #define RSTCSR_R        (RSTCSR + 1)
  25
  26 /* Bit definitions */
  27 #define WTCSR_IOVF      0x80
  28 #define WTCSR_WT        0x40
  29 #define WTCSR_TME       0x20
  30 #define WTCSR_RSTS      0x00
  31
  32 #define RSTCSR_RSTS     0x20
  33
  34 /**
  35  *      sh_wdt_read_rstcsr - Read from Reset Control/Status Register
  36  *
  37  *      Reads back the RSTCSR value.
  38  */
  39 static inline __u8 sh_wdt_read_rstcsr(void)
  40 {
  41         /*
  42          * Same read/write brain-damage as for WTCNT here..
  43          */
  44         return __raw_readb(RSTCSR_R);
  45 }
  46
  47 /**
  48  *      sh_wdt_write_csr - Write to Reset Control/Status Register
  49  *
  50  *      @val: Value to write
  51  *
  52  *      Writes the given value @val to the lower byte of the control/status
  53  *      register. The upper byte is set manually on each write.
  54  */
  55 static inline void sh_wdt_write_rstcsr(__u8 val)
  56 {
  57         /*
  58          * Note: Due to the brain-damaged nature of this register,
  59          * we can't presently touch the WOVF bit, since the upper byte
  60          * has to be swapped for this. So just leave it alone..
  61          */
  62         __raw_writeb((WTCNT_HIGH << 8) | (__u16)val, RSTCSR);
  63 }
  64
  65 #endif /* __ASM_CPU_SH2_WATCHDOG_H */
  66